Uses of Interface byucc.jhdl.base.CellInterface (JHDL API)

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Uses of Interface
byucc.jhdl.base.CellInterface

Packages that use CellInterface
byucc.jhdl.base
byucc.jhdl.contrib.modgen
byucc.jhdl.contrib.modgen.AddSubPack
byucc.jhdl.contrib.modgen.CordicPack
byucc.jhdl.contrib.modgen.IntDividePack
byucc.jhdl.contrib.modgen.MultArrayPack
byucc.jhdl.CSRC
byucc.jhdl.DRC
byucc.jhdl.DRC.Tester
byucc.jhdl.examples
byucc.jhdl.examples.des
byucc.jhdl.examples.editDistance
byucc.jhdl.examples.fsm
byucc.jhdl.examples.shifter
byucc.jhdl.examples.xr16cpu
byucc.jhdl.Logic.Modules
byucc.jhdl.Logic.Modules.CordicPack
byucc.jhdl.Logic.Modules.DigitSerial
byucc.jhdl.Logic.Modules.FloatingPoint
byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2
byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix4
byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8
byucc.jhdl.Logic.Modules.FloatingPoint.examples
byucc.jhdl.Logic.Modules.FloatingPoint.FPAddSubPack
byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack
byucc.jhdl.Logic.Modules.FloatingPoint.helpers
byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix2
byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix4
byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix8
byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack
byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix2
byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4
byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix8
byucc.jhdl.Logic.Modules.FloatingPoint.SqPack
byucc.jhdl.Logic.Modules.IntDividePack
byucc.jhdl.Logic.Modules.MultArrayPack
byucc.jhdl.Logic.Modules.ShiftRegPack
byucc.jhdl.parsers.xnf
byucc.jhdl.platforms.util
byucc.jhdl.TERA
byucc.jhdl.Xilinx
byucc.jhdl.Xilinx.demo
byucc.jhdl.Xilinx.Virtex
byucc.jhdl.Xilinx.Virtex.helpers
byucc.jhdl.Xilinx.Virtex.Modules
byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack
byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack
byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack
byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack
byucc.jhdl.Xilinx.Virtex.ramb4_wrapper
byucc.jhdl.Xilinx.Virtex2
byucc.jhdl.Xilinx.Virtex2.helpers
byucc.jhdl.Xilinx.Virtex2.Modules
byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint
byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack
byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack
byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack
byucc.jhdl.Xilinx.Virtex2.RamPack
byucc.jhdl.Xilinx.XC4000
byucc.jhdl.Xilinx.XC4000.carryLogic
byucc.jhdl.Xilinx.XC4000.Modules
byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack
byucc.jhdl.Xilinx.XC4000.techmap.helpers
byucc.jhdl.Xilinx.XC9000
byucc.jhdl.Xilinx.XC9000.helpers
byucc.jhdl.Xilinx.XC9000.Modules

Uses of CellInterface in byucc.jhdl.base

Classes in byucc.jhdl.base that implement CellInterface
`class`	`Parameter` This class allows the creation of arbitrarily typed parameters as part of a CellInterface.
`class`	`Port` This class represents a port within a cell's interface.

Fields in byucc.jhdl.base declared as CellInterface
`protected static CellInterface[]`	`Cell.implicit_interface` This defines a blank implicit interface.

Methods in byucc.jhdl.base that return CellInterface
`static CellInterface`	`Cell.port(java.lang.String name, int width, int type)` Creates the declaration for a port, to be used in the CellInterface[].
`static CellInterface`	`Cell.port(java.lang.String name, java.lang.String width, int type)` Creates the declaration for a port, to be used in the CellInterface[].
`static CellInterface`	`Cell.in(java.lang.String name, int width)` Creates the declaration for an in-port, to be used in the CellInterface[]
`static CellInterface`	`Cell.in(java.lang.String name, java.lang.String width)` Creates the declaration for an in-port, to be used in the CellInterface[]
`static CellInterface`	`Cell.out(java.lang.String name, int width)` Creates the declaration for an out-port, to be used in the CellInterface[]
`static CellInterface`	`Cell.out(java.lang.String name, java.lang.String width)` Creates the declaration for an out-port, to be used in the CellInterface[]
`static CellInterface`	`Cell.clk(java.lang.String name)` Creates the declaration for a clk-port, to be used in the CellInterface[].
`static CellInterface`	`Cell.inout(java.lang.String name, int width)` Creates the declaration for an inout-port, to be used in the CellInterface[]
`static CellInterface`	`Cell.inout(java.lang.String name, java.lang.String width)` Creates the declaration for an inout-port, to be used in the CellInterface[]
`static CellInterface`	`Cell.param(java.lang.String name, java.lang.Class type)` Creates the declaration of a Parameter, to be used in the CellInterface[]

Methods in byucc.jhdl.base with parameters of type CellInterface
`void`	`Cell.addPort(CellInterface portInterface)` Adds a port to the cell, after it has been created.
`void`	`Cell.addPorts(CellInterface[] portInterfaces)` Adds an array of ports to the cell, after it has been created.
`Cell`	`Cell.pushHierarchyNoImplicitPorts(CellInterface[] cell_interface, java.lang.String cellname, boolean unique_structure)` This call begins the creation of a subcell with no implicit ports inherited from any parent cell.
`Cell`	`Cell.pushHierarchyNoImplicitPorts(CellInterface[] cell_interface, java.lang.String cellname, boolean unique_structure, java.lang.String instance_name)` This call begins the creation of a subcell with no implicit ports inherited from any parent cell.
`Cell`	`Cell.pushHierarchy(CellInterface[] cell_interface, java.lang.String cellname)` This allows multiple levels of hierarchy within one class file
`Cell`	`Cell.pushHierarchy(CellInterface[] cell_interface, java.lang.String cellname, boolean unique_structure)` This allows multiple levels of hierarchy within one class file
`Cell`	`Cell.pushHierarchy(CellInterface[] cell_interface, java.lang.String cellname, java.lang.String instance_name)` This allows multiple levels of hierarchy within one class file
`Cell`	`Cell.pushHierarchy(CellInterface[] cell_interface, java.lang.String cellname, boolean unique_structure, java.lang.String instance_name)` This allows multiple levels of hierarchy within one class file, works in tandem with `Cell.popHierarchy()`.

Uses of CellInterface in byucc.jhdl.contrib.modgen

Fields in byucc.jhdl.contrib.modgen declared as CellInterface
`static CellInterface[]`	`booth.cell_interface`
`static CellInterface[]`	`srl_array.cell_interface`
`static CellInterface[]`	`Cordicl.cell_interface`
`static CellInterface[]`	`eq.cell_interface`
`static CellInterface[]`	`StageRP.cell_interface`
`static CellInterface[]`	`Cordic.cell_interface`
`static CellInterface[]`	`accum.cell_interface`
`static CellInterface[]`	`Sub.cell_interface` Deprecated.
`static CellInterface[]`	`rounder.cell_interface`
`static CellInterface[]`	`gt.cell_interface`
`static CellInterface[]`	`Adsu.cell_interface` Deprecated.
`static CellInterface[]`	`IntDivide.cell_interface` Standard JHDL CellInterface.
`static CellInterface[]`	`Add.cell_interface` Deprecated.
`static CellInterface[]`	`LFSR4.cell_interface`
`static CellInterface[]`	`downcnt.cell_interface`
`static CellInterface[]`	`downcnt.implicit_interface`
`static CellInterface[]`	`lt.cell_interface`
`static CellInterface[]`	`upcnt.cell_interface`
`static CellInterface[]`	`upcnt.implicit_interface`
`static CellInterface[]`	`arrayMult.cell_interface` Standard JHDL CellInterface.
`static CellInterface[]`	`CordicRP.cell_interface`

Uses of CellInterface in byucc.jhdl.contrib.modgen.AddSubPack

Fields in byucc.jhdl.contrib.modgen.AddSubPack declared as CellInterface
`static CellInterface[]`	`SUB_F_CI.cell_interface`
`static CellInterface[]`	`ADDSUB_F_CI.cell_interface`
`static CellInterface[]`	`SUB_G_F1.cell_interface`
`static CellInterface[]`	`ADDSUB_FG_CI.cell_interface`
`static CellInterface[]`	`ADDSUB_G_F1.cell_interface`
`static CellInterface[]`	`ADDSUB_G_F3_.cell_interface`
`static CellInterface[]`	`ADD_F_CI.cell_interface`
`static CellInterface[]`	`SUB_FG_CI.cell_interface`
`static CellInterface[]`	`ADD_G_F1.cell_interface`
`static CellInterface[]`	`SUB_G_1.cell_interface`
`static CellInterface[]`	`ADD_FG_CI.cell_interface`

Uses of CellInterface in byucc.jhdl.contrib.modgen.CordicPack

Fields in byucc.jhdl.contrib.modgen.CordicPack declared as CellInterface
`static CellInterface[]`	`Stage.cell_interface`
`static CellInterface[]`	`Tc_mux.cell_interface`
`static CellInterface[]`	`Init_rot.cell_interface`
`static CellInterface[]`	`Z_Mux.cell_interface`
`static CellInterface[]`	`Stagel.cell_interface`
`static CellInterface[]`	`Cordicl_ctrl.cell_interface`
`static CellInterface[]`	`Pipe_sigs.cell_interface`
`static CellInterface[]`	`Col_reg.cell_interface`
`static CellInterface[]`	`End_rot.cell_interface`
`static CellInterface[]`	`Cordic_ctrl.cell_interface`

Uses of CellInterface in byucc.jhdl.contrib.modgen.IntDividePack

Fields in byucc.jhdl.contrib.modgen.IntDividePack declared as CellInterface
`static CellInterface[]`	`AddPassVirtex.cell_interface`
`static CellInterface[]`	`AddPass.cell_interface`
`static CellInterface[]`	`AddPassXC4000.cell_interface`
`static CellInterface[]`	`AddPassGeneric.cell_interface`

Uses of CellInterface in byucc.jhdl.contrib.modgen.MultArrayPack

Fields in byucc.jhdl.contrib.modgen.MultArrayPack declared as CellInterface
`static CellInterface[]`	`MultAddVirtex.cell_interface`
`static CellInterface[]`	`MultSubXC4000.cell_interface`
`static CellInterface[]`	`EXAMINE_CI_Virtex.cell_interface`
`static CellInterface[]`	`MultSubGeneric.cell_interface`
`static CellInterface[]`	`MultAddXC4000.cell_interface`
`static CellInterface[]`	`MultSub.cell_interface`
`static CellInterface[]`	`And_fmap_g.cell_interface`
`static CellInterface[]`	`MultAdd.cell_interface`
`static CellInterface[]`	`MultAddGeneric.cell_interface`
`static CellInterface[]`	`MultSubVirtex.cell_interface`
`static CellInterface[]`	`multCol.cell_interface`

Uses of CellInterface in byucc.jhdl.CSRC

Fields in byucc.jhdl.CSRC declared as CellInterface
`static CellInterface[]`	`dffr_dp.cell_interface` The port interface for: dffr_dp i_1 : implicit (1) i_0 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`dffse_dp.cell_interface` The port interface for: dffse_dp i_1 : implicit (1) i_0 : in (1) i_2 : in (1) i_3 : in (1) o_0 : out (1)
`static CellInterface[]`	`dffe_dp.cell_interface` The port interface for: dffe_dp i_1 : implicit (1) i_0 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`dff_dp.cell_interface` The port interface for: dff_dp i_1 : implicit (1) i_0 : in (1) o_0 : out (1)
`static CellInterface[]`	`maj3.cell_interface` The port interface for: maj3 a : in (1) b : in (1) c : in (1) q : out (1)
`static CellInterface[]`	`mux3_dp.cell_interface` The port interface for: mux3_dp i_0 : in (1) i_1 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`buf.cell_interface` The port interface for: buf A : in (1) Q : out (1)
`static CellInterface[]`	`OB.cell_interface` The port interface for: OB A : in (1) Y : out (1)
`static CellInterface[]`	`OBT.cell_interface` The port interface for: OBT A : in (1) OE : in (1) Y : out (1)
`static CellInterface[]`	`not_dp.cell_interface` The port interface for: not_dp i_0 : in (1) o_0 : out (1)
`static CellInterface[]`	`DL_ONE.cell_interface` The port interface for: DL_ONE Y : out (1)
`static CellInterface[]`	`dffs_dp.cell_interface` The port interface for: dffs_dp i_1 : implicit (1) i_0 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`dffre_dp.cell_interface` The port interface for: dffre_dp i_1 : implicit (1) i_0 : in (1) i_2 : in (1) i_3 : in (1) o_0 : out (1)
`static CellInterface[]`	`IB.cell_interface` The port interface for: IB A : in (1) Y : out (1)
`static CellInterface[]`	`DL_ZERO.cell_interface` The port interface for: DL_ZERO Y : out (1)
`static CellInterface[]`	`xnor9_dp.cell_interface`
`static CellInterface[]`	`xnor8_dp.cell_interface`
`static CellInterface[]`	`xnor7_dp.cell_interface`
`static CellInterface[]`	`xnor6_dp.cell_interface`
`static CellInterface[]`	`xnor5_dp.cell_interface`
`static CellInterface[]`	`xnor4_dp.cell_interface`
`static CellInterface[]`	`xnor3_dp_g.cell_interface`
`static CellInterface[]`	`xnor2_dp_g.cell_interface`
`static CellInterface[]`	`xnor3_dp.cell_interface` The port interface for: xnor3_dp i_0 : in (1) i_1 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`xnor2_dp.cell_interface` The port interface for: xnor2_dp i_0 : in (1) i_1 : in (1) o_0 : out (1)
`static CellInterface[]`	`xor9_dp.cell_interface`
`static CellInterface[]`	`xor8_dp.cell_interface`
`static CellInterface[]`	`xor7_dp.cell_interface`
`static CellInterface[]`	`xor6_dp.cell_interface`
`static CellInterface[]`	`xor5_dp.cell_interface`
`static CellInterface[]`	`xor4_dp.cell_interface`
`static CellInterface[]`	`xor3_dp_g.cell_interface`
`static CellInterface[]`	`xor2_dp_g.cell_interface`
`static CellInterface[]`	`xor3_dp.cell_interface` The port interface for: xor3_dp i_0 : in (1) i_1 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`xor2_dp.cell_interface` The port interface for: xor2_dp i_0 : in (1) i_1 : in (1) o_0 : out (1)
`static CellInterface[]`	`nor9_dp.cell_interface`
`static CellInterface[]`	`nor8_dp.cell_interface`
`static CellInterface[]`	`nor7_dp.cell_interface`
`static CellInterface[]`	`nor6_dp.cell_interface`
`static CellInterface[]`	`nor5_dp.cell_interface`
`static CellInterface[]`	`nor4_dp.cell_interface`
`static CellInterface[]`	`nor3_dp_g.cell_interface`
`static CellInterface[]`	`nor2_dp_g.cell_interface`
`static CellInterface[]`	`nor3_dp.cell_interface` The port interface for: nor3_dp i_0 : in (1) i_1 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`nor2_dp.cell_interface` The port interface for: nor2_dp i_0 : in (1) i_1 : in (1) o_0 : out (1)
`static CellInterface[]`	`or9_dp.cell_interface`
`static CellInterface[]`	`or8_dp.cell_interface`
`static CellInterface[]`	`or7_dp.cell_interface`
`static CellInterface[]`	`or6_dp.cell_interface`
`static CellInterface[]`	`or5_dp.cell_interface`
`static CellInterface[]`	`or4_dp.cell_interface`
`static CellInterface[]`	`or3_dp_g.cell_interface`
`static CellInterface[]`	`or2_dp_g.cell_interface`
`static CellInterface[]`	`or3_dp.cell_interface` The port interface for: or3_dp i_0 : in (1) i_1 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`or2_dp.cell_interface` The port interface for: or2_dp i_0 : in (1) i_1 : in (1) o_0 : out (1)
`static CellInterface[]`	`nand9_dp.cell_interface`
`static CellInterface[]`	`nand8_dp.cell_interface`
`static CellInterface[]`	`nand7_dp.cell_interface`
`static CellInterface[]`	`nand6_dp.cell_interface`
`static CellInterface[]`	`nand5_dp.cell_interface`
`static CellInterface[]`	`nand4_dp.cell_interface`
`static CellInterface[]`	`nand3_dp_g.cell_interface`
`static CellInterface[]`	`nand2_dp_g.cell_interface`
`static CellInterface[]`	`nand3_dp.cell_interface` The port interface for: nand3_dp i_0 : in (1) i_1 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`nand2_dp.cell_interface` The port interface for: nand2_dp i_0 : in (1) i_1 : in (1) o_0 : out (1)
`static CellInterface[]`	`and9_dp.cell_interface`
`static CellInterface[]`	`and8_dp.cell_interface`
`static CellInterface[]`	`and7_dp.cell_interface`
`static CellInterface[]`	`and6_dp.cell_interface`
`static CellInterface[]`	`and5_dp.cell_interface`
`static CellInterface[]`	`and4_dp.cell_interface`
`static CellInterface[]`	`and3_dp_g.cell_interface`
`static CellInterface[]`	`and2_dp_g.cell_interface`
`static CellInterface[]`	`and3_dp.cell_interface` The port interface for: and3_dp i_0 : in (1) i_1 : in (1) i_2 : in (1) o_0 : out (1)
`static CellInterface[]`	`and2_dp.cell_interface` The port interface for: and2_dp i_0 : in (1) i_1 : in (1) o_0 : out (1)
`static CellInterface[]`	`OBX.cell_interface`
`static CellInterface[]`	`dffre_dpX.cell_interface`
`static CellInterface[]`	`addsubX.cell_interface`
`static CellInterface[]`	`subX.cell_interface`
`static CellInterface[]`	`dffs_dpX.cell_interface`
`static CellInterface[]`	`bufX.cell_interface`
`static CellInterface[]`	`notX.cell_interface`
`static CellInterface[]`	`dffse_dpX.cell_interface`
`static CellInterface[]`	`addX.cell_interface`
`static CellInterface[]`	`mux_dpX.cell_interface`
`static CellInterface[]`	`dffe_dpX.cell_interface`
`static CellInterface[]`	`gndX.cell_interface`
`static CellInterface[]`	`vccX.cell_interface`
`static CellInterface[]`	`OBTX.cell_interface`
`static CellInterface[]`	`dffr_dpX.cell_interface`
`static CellInterface[]`	`dff_dpX.cell_interface`
`static CellInterface[]`	`IBX.cell_interface`
`static CellInterface[]`	`orX.cell_interface`
`static CellInterface[]`	`nandX.cell_interface`
`static CellInterface[]`	`norX.cell_interface`
`static CellInterface[]`	`xorX.cell_interface`
`static CellInterface[]`	`xnorX.cell_interface`
`static CellInterface[]`	`andX.cell_interface`
`static CellInterface[]`	`Shifter.cell_interface`
`static CellInterface[]`	`CSRCClockDriver.cell_interface`
`static CellInterface[]`	`Constant.cell_interface` The port interface for Constant: o: out("n") parameter: "n" (INTEGER).
`static CellInterface[]`	`CSRCCL.implicit_interface`
`static CellInterface[]`	`CSRCFD.implicit_interface`

Uses of CellInterface in byucc.jhdl.DRC

Fields in byucc.jhdl.DRC declared as CellInterface
`static CellInterface[]`	`Toggler.cell_interface`

Uses of CellInterface in byucc.jhdl.DRC.Tester

Fields in byucc.jhdl.DRC.Tester declared as CellInterface
`static CellInterface[]`	`LogicMisplacement.cell_interface`
`static CellInterface[]`	`NoBufg.cell_interface`
`static CellInterface[]`	`MultiplePuts.cell_interface`

Uses of CellInterface in byucc.jhdl.examples

Fields in byucc.jhdl.examples declared as CellInterface
`static CellInterface[]`	`FullAdder.cell_interface`
`static CellInterface[]`	`NBitAdder.cell_interface`

Uses of CellInterface in byucc.jhdl.examples.des

Fields in byucc.jhdl.examples.des declared as CellInterface
`static CellInterface[]`	`DES.cell_interface`
`static CellInterface[]`	`SBoxes.cell_interface`
`static CellInterface[]`	`DESRoundC.cell_interface`

Uses of CellInterface in byucc.jhdl.examples.editDistance

Fields in byucc.jhdl.examples.editDistance declared as CellInterface
`static CellInterface[]`	`edistance2.cell_interface`
`static CellInterface[]`	`charcomp2.cell_interface`
`static CellInterface[]`	`upDownCounter.cell_interface`
`static CellInterface[]`	`char_slice2.cell_interface`
`static CellInterface[]`	`char_fsm2.cell_interface`
`static CellInterface[]`	`left_edge2.cell_interface`
`static CellInterface[]`	`mod4count2.cell_interface`

Uses of CellInterface in byucc.jhdl.examples.fsm

Fields in byucc.jhdl.examples.fsm declared as CellInterface
`static CellInterface[]`	`fsmMemCtl.cell_interface`
`static CellInterface[]`	`parity.cell_interface`

Uses of CellInterface in byucc.jhdl.examples.shifter

Fields in byucc.jhdl.examples.shifter declared as CellInterface
`static CellInterface[]`	`VarShiftR.cell_interface`
`static CellInterface[]`	`ShiftMuxR.cell_interface`

Uses of CellInterface in byucc.jhdl.examples.xr16cpu

Fields in byucc.jhdl.examples.xr16cpu declared as CellInterface
`static CellInterface[]`	`logicops.cell_interface`
`static CellInterface[]`	`lcdoutport.cell_interface`
`static CellInterface[]`	`bram_4k.cell_interface`
`static CellInterface[]`	`adsuovf1.cell_interface`
`static CellInterface[]`	`datapath.cell_interface`
`static CellInterface[]`	`sport.cell_interface`
`static CellInterface[]`	`bram_1k.cell_interface`
`static CellInterface[]`	`timerefs.cell_interface`
`static CellInterface[]`	`uat.cell_interface`
`static CellInterface[]`	`xr16vxcpu.cell_interface`
`static CellInterface[]`	`brir.cell_interface`
`static CellInterface[]`	`uar.cell_interface`
`static CellInterface[]`	`xr16vx_4k.cell_interface`
`static CellInterface[]`	`regfile.cell_interface`
`static CellInterface[]`	`adsuovf16.cell_interface`
`static CellInterface[]`	`paroutport.cell_interface`
`static CellInterface[]`	`dec16.cell_interface`
`static CellInterface[]`	`xr16vx_1k.cell_interface`
`static CellInterface[]`	`control.cell_interface`
`static CellInterface[]`	`parinport.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules

Fields in byucc.jhdl.Logic.Modules declared as CellInterface
`static CellInterface[]`	`rounder.cell_interface`
`static CellInterface[]`	`FreeRunTimer.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`upcnt.cell_interface`
`static CellInterface[]`	`ParallelLeftShiftReg.cell_interface`
`static CellInterface[]`	`eq.cell_interface`
`static CellInterface[]`	`decoder5_32.cell_interface`
`static CellInterface[]`	`decoder7_128.cell_interface`
`static CellInterface[]`	`Duplicate.cell_interface`
`static CellInterface[]`	`delay.cell_interface`
`static CellInterface[]`	`UpDownCount.cell_interface`
`static CellInterface[]`	`LogShiftL.cell_interface`
`static CellInterface[]`	`gt.cell_interface`
`static CellInterface[]`	`booth.cell_interface`
`static CellInterface[]`	`Decoder.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`downcnt.cell_interface`
`static CellInterface[]`	`toggle.cell_interface`
`static CellInterface[]`	`decoder1_2.cell_interface`
`static CellInterface[]`	`Encoder.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`IntDivide.cell_interface` Standard JHDL CellInterface.
`static CellInterface[]`	`Cordic.cell_interface`
`static CellInterface[]`	`Reverse.cell_interface`
`static CellInterface[]`	`decoder8_256.cell_interface`
`static CellInterface[]`	`lt.cell_interface`
`static CellInterface[]`	`accum.cell_interface`
`static CellInterface[]`	`decoder2_4.cell_interface`
`static CellInterface[]`	`arrayMult.cell_interface` Standard JHDL CellInterface.
`static CellInterface[]`	`decoder6_64.cell_interface`
`static CellInterface[]`	`LogShiftR.cell_interface`
`static CellInterface[]`	`decoder4_16.cell_interface`
`static CellInterface[]`	`ParallelRightShiftReg.cell_interface`
`static CellInterface[]`	`decoder3_8.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.CordicPack

Fields in byucc.jhdl.Logic.Modules.CordicPack declared as CellInterface
`static CellInterface[]`	`Tc_mux.cell_interface`
`static CellInterface[]`	`Stage.cell_interface`
`static CellInterface[]`	`Pipe_sigs.cell_interface`
`static CellInterface[]`	`Adsu.cell_interface`
`static CellInterface[]`	`Z_Mux.cell_interface`
`static CellInterface[]`	`Col_reg.cell_interface`
`static CellInterface[]`	`End_rot.cell_interface`
`static CellInterface[]`	`carryLogic.cell_interface`
`static CellInterface[]`	`Cordic_ctrl.cell_interface`
`static CellInterface[]`	`Init_rot.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.DigitSerial

Fields in byucc.jhdl.Logic.Modules.DigitSerial declared as CellInterface
`static CellInterface[]`	`DSadder.cell_interface`
`static CellInterface[]`	`DScontrol.cell_interface`
`static CellInterface[]`	`DSmultiplier.cell_interface`
`static CellInterface[]`	`DS_FIR_module.cell_interface`
`static CellInterface[]`	`SPR.cell_interface`
`static CellInterface[]`	`PSR.cell_interface`
`static CellInterface[]`	`DSPR.cell_interface`
`static CellInterface[]`	`DPSR.cell_interface`
`static CellInterface[]`	`DSmult_module.cell_interface`
`static CellInterface[]`	`DScross.cell_interface`
`static CellInterface[]`	`DSmult_module_last.cell_interface`
`static CellInterface[]`	`DS_FIR.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint

Fields in byucc.jhdl.Logic.Modules.FloatingPoint declared as CellInterface
`static CellInterface[]`	`Pipe_SquareRoot.cell_interface`
`static CellInterface[]`	`FPMult.cell_interface`
`static CellInterface[]`	`SquareRoot.cell_interface`
`static CellInterface[]`	`toFixed.cell_interface`
`static CellInterface[]`	`FPDivide.cell_interface`
`static CellInterface[]`	`FPAddSub.cell_interface`
`static CellInterface[]`	`toFloat.cell_interface`
`static CellInterface[]`	`FPCompare.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2 declared as CellInterface
`static CellInterface[]`	`stages.cell_interface`
`static CellInterface[]`	`scale_back.cell_interface`
`static CellInterface[]`	`FPDiv_radix2.cell_interface`
`static CellInterface[]`	`scale.cell_interface`
`static CellInterface[]`	`stage.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix4

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix4 declared as CellInterface
`static CellInterface[]`	`scale_back.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`
`static CellInterface[]`	`scale.cell_interface`
`static CellInterface[]`	`FPDiv_radix4.cell_interface`
`static CellInterface[]`	`stage.cell_interface`
`static CellInterface[]`	`stages.cell_interface`
`static CellInterface[]`	`table.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8 declared as CellInterface
`static CellInterface[]`	`scale_back.cell_interface`
`static CellInterface[]`	`stages.cell_interface`
`static CellInterface[]`	`stage.cell_interface`
`static CellInterface[]`	`scale.cell_interface`
`static CellInterface[]`	`table.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`
`static CellInterface[]`	`FPDiv_radix8.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.examples

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.examples declared as CellInterface
`static CellInterface[]`	`toFloatExample.cell_interface` The cell interface

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.FPAddSubPack

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.FPAddSubPack declared as CellInterface
`static CellInterface[]`	`Round.cell_interface`
`static CellInterface[]`	`Normalize.cell_interface`
`static CellInterface[]`	`FPExponentMatch.cell_interface`
`static CellInterface[]`	`TestOverflow.cell_interface`
`static CellInterface[]`	`FP_ALU.cell_interface`
`static CellInterface[]`	`Maximum.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack declared as CellInterface
`static CellInterface[]`	`UIntDivide.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.helpers

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.helpers declared as CellInterface
`static CellInterface[]`	`FPUnpack.cell_interface`
`static CellInterface[]`	`FPPack.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix2

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix2 declared as CellInterface
`static CellInterface[]`	`stages.cell_interface`
`static CellInterface[]`	`scale.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`
`static CellInterface[]`	`scale_back.cell_interface`
`static CellInterface[]`	`FPDiv_radix2.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix4

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix4 declared as CellInterface
`static CellInterface[]`	`scale.cell_interface`
`static CellInterface[]`	`table.cell_interface`
`static CellInterface[]`	`scale_back.cell_interface`
`static CellInterface[]`	`FPDiv_radix4.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`
`static CellInterface[]`	`stages.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix8

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix8 declared as CellInterface
`static CellInterface[]`	`FPDiv_radix8.cell_interface`
`static CellInterface[]`	`scale.cell_interface`
`static CellInterface[]`	`table.cell_interface`
`static CellInterface[]`	`stages.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`
`static CellInterface[]`	`scale_back.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack declared as CellInterface
`static CellInterface[]`	`Pipe_Scale.cell_interface`
`static CellInterface[]`	`Pipe_Stages.cell_interface`
`static CellInterface[]`	`Pipe_Square_root.cell_interface`
`static CellInterface[]`	`Pipe_algorithm.cell_interface`
`static CellInterface[]`	`Pipe_Reg_f.cell_interface`
`static CellInterface[]`	`Pipe_Scale_back.cell_interface`
`static CellInterface[]`	`Pipe_Frac.cell_interface`
`static CellInterface[]`	`Pipe_Remainder.cell_interface`
`static CellInterface[]`	`Pipe_Algorithm_Stage.cell_interface`
`static CellInterface[]`	`Pipe_Reg_e.cell_interface`
`static CellInterface[]`	`Pipe_Stage.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix2

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix2 declared as CellInterface
`static CellInterface[]`	`stages.cell_interface`
`static CellInterface[]`	`FPDiv_radix2.cell_interface`
`static CellInterface[]`	`scale_back.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`
`static CellInterface[]`	`stage.cell_interface`
`static CellInterface[]`	`scale.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4 declared as CellInterface
`static CellInterface[]`	`stages.cell_interface`
`static CellInterface[]`	`scale_back.cell_interface`
`static CellInterface[]`	`FPDiv_radix4.cell_interface`
`static CellInterface[]`	`stage.cell_interface`
`static CellInterface[]`	`scale.cell_interface`
`static CellInterface[]`	`table.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix8

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix8 declared as CellInterface
`static CellInterface[]`	`FPDiv_radix8.cell_interface`
`static CellInterface[]`	`stages.cell_interface`
`static CellInterface[]`	`scale.cell_interface`
`static CellInterface[]`	`scale_back.cell_interface`
`static CellInterface[]`	`stage.cell_interface`
`static CellInterface[]`	`specialHandler.cell_interface`
`static CellInterface[]`	`table.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.FloatingPoint.SqPack

Fields in byucc.jhdl.Logic.Modules.FloatingPoint.SqPack declared as CellInterface
`static CellInterface[]`	`Scale.cell_interface`
`static CellInterface[]`	`Remainder.cell_interface`
`static CellInterface[]`	`counter.cell_interface`
`static CellInterface[]`	`Square_root.cell_interface`
`static CellInterface[]`	`Frac.cell_interface`
`static CellInterface[]`	`Exponent.cell_interface`
`static CellInterface[]`	`Scale_back.cell_interface`
`static CellInterface[]`	`Valid.cell_interface`
`static CellInterface[]`	`Algorithm.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.IntDividePack

Fields in byucc.jhdl.Logic.Modules.IntDividePack declared as CellInterface
`static CellInterface[]`	`AddPass.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.MultArrayPack

Fields in byucc.jhdl.Logic.Modules.MultArrayPack declared as CellInterface
`static CellInterface[]`	`MultSub.cell_interface`
`static CellInterface[]`	`MultAdd.cell_interface`
`static CellInterface[]`	`multCol.cell_interface`

Uses of CellInterface in byucc.jhdl.Logic.Modules.ShiftRegPack

Fields in byucc.jhdl.Logic.Modules.ShiftRegPack declared as CellInterface
`static CellInterface[]`	`ShiftRegBit.cell_interface`

Uses of CellInterface in byucc.jhdl.parsers.xnf

Methods in byucc.jhdl.parsers.xnf that return CellInterface
`CellInterface`	`XNFCellPort.getCellInterface()`

Uses of CellInterface in byucc.jhdl.platforms.util

Fields in byucc.jhdl.platforms.util declared as CellInterface
`static CellInterface[]`	`XC4000_IOB.cell_interface`
`static CellInterface[]`	`Virtex_IOB.cell_interface` Cell Interface for the class.

Uses of CellInterface in byucc.jhdl.TERA

Fields in byucc.jhdl.TERA declared as CellInterface
`static CellInterface[]`	`tera_inv.cell_interface` The port interface for: tera_inv A : in (1) Z : out (1)
`static CellInterface[]`	`tera_mux4.cell_interface` The port interface for: tera_mux4 D0 : in (1) D1 : in (1) D2 : in (1) D3 : in (1) A : in (1) B : in (1) Z : out (1)
`static CellInterface[]`	`tera_mem.cell_interface` The port interface for: tera_mem A : in (1) Z : out (1)
`static CellInterface[]`	`tera_add.cell_interface` The port interface for: tera_add A : in (1) B : in (1) C : in (1) COUT : out (1) SUM : out (1)
`static CellInterface[]`	`tera_dff.cell_interface` The port interface for: tera_dff c : implicit (1) D : in (1) Q : out (1)
`static CellInterface[]`	`tera_low.cell_interface` The port interface for: tera_low Z : out (1)
`static CellInterface[]`	`tera_high.cell_interface` The port interface for: tera_high Z : out (1)
`static CellInterface[]`	`tera_mux2.cell_interface` The port interface for: tera_mux2 A : in (1) B : in (1) S : in (1) Z : out (1)
`static CellInterface[]`	`tera_buf.cell_interface` The port interface for: tera_buf A : in (1) Z : out (1)
`static CellInterface[]`	`tera_xnor8_g.cell_interface`
`static CellInterface[]`	`tera_xnor7_g.cell_interface`
`static CellInterface[]`	`tera_xnor6_g.cell_interface`
`static CellInterface[]`	`tera_xnor5_g.cell_interface`
`static CellInterface[]`	`tera_xnor4_g.cell_interface`
`static CellInterface[]`	`tera_xnor3_g.cell_interface`
`static CellInterface[]`	`tera_xnor2_g.cell_interface`
`static CellInterface[]`	`tera_xnor8.cell_interface` The port interface for: tera_xnor8 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) H : in (1) Z : out (1)
`static CellInterface[]`	`tera_xnor7.cell_interface` The port interface for: tera_xnor7 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) Z : out (1)
`static CellInterface[]`	`tera_xnor6.cell_interface` The port interface for: tera_xnor6 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) Z : out (1)
`static CellInterface[]`	`tera_xnor5.cell_interface` The port interface for: tera_xnor5 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) Z : out (1)
`static CellInterface[]`	`tera_xnor4.cell_interface` The port interface for: tera_xnor4 A : in (1) B : in (1) C : in (1) D : in (1) Z : out (1)
`static CellInterface[]`	`tera_xnor3.cell_interface` The port interface for: tera_xnor3 A : in (1) B : in (1) C : in (1) Z : out (1)
`static CellInterface[]`	`tera_xnor2.cell_interface` The port interface for: tera_xnor2 A : in (1) B : in (1) Z : out (1)
`static CellInterface[]`	`tera_xor8_g.cell_interface`
`static CellInterface[]`	`tera_xor7_g.cell_interface`
`static CellInterface[]`	`tera_xor6_g.cell_interface`
`static CellInterface[]`	`tera_xor5_g.cell_interface`
`static CellInterface[]`	`tera_xor4_g.cell_interface`
`static CellInterface[]`	`tera_xor3_g.cell_interface`
`static CellInterface[]`	`tera_xor2_g.cell_interface`
`static CellInterface[]`	`tera_xor8.cell_interface` The port interface for: tera_xor8 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) H : in (1) Z : out (1)
`static CellInterface[]`	`tera_xor7.cell_interface` The port interface for: tera_xor7 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) Z : out (1)
`static CellInterface[]`	`tera_xor6.cell_interface` The port interface for: tera_xor6 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) Z : out (1)
`static CellInterface[]`	`tera_xor5.cell_interface` The port interface for: tera_xor5 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) Z : out (1)
`static CellInterface[]`	`tera_xor4.cell_interface` The port interface for: tera_xor4 A : in (1) B : in (1) C : in (1) D : in (1) Z : out (1)
`static CellInterface[]`	`tera_xor3.cell_interface` The port interface for: tera_xor3 A : in (1) B : in (1) C : in (1) Z : out (1)
`static CellInterface[]`	`tera_xor2.cell_interface` The port interface for: tera_xor2 A : in (1) B : in (1) Z : out (1)
`static CellInterface[]`	`tera_nor8_g.cell_interface`
`static CellInterface[]`	`tera_nor7_g.cell_interface`
`static CellInterface[]`	`tera_nor6_g.cell_interface`
`static CellInterface[]`	`tera_nor5_g.cell_interface`
`static CellInterface[]`	`tera_nor4_g.cell_interface`
`static CellInterface[]`	`tera_nor3_g.cell_interface`
`static CellInterface[]`	`tera_nor2_g.cell_interface`
`static CellInterface[]`	`tera_nor8.cell_interface` The port interface for: tera_nor8 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) H : in (1) Z : out (1)
`static CellInterface[]`	`tera_nor7.cell_interface` The port interface for: tera_nor7 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) Z : out (1)
`static CellInterface[]`	`tera_nor6.cell_interface` The port interface for: tera_nor6 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) Z : out (1)
`static CellInterface[]`	`tera_nor5.cell_interface` The port interface for: tera_nor5 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) Z : out (1)
`static CellInterface[]`	`tera_nor4.cell_interface` The port interface for: tera_nor4 A : in (1) B : in (1) C : in (1) D : in (1) Z : out (1)
`static CellInterface[]`	`tera_nor3.cell_interface` The port interface for: tera_nor3 A : in (1) B : in (1) C : in (1) Z : out (1)
`static CellInterface[]`	`tera_nor2.cell_interface` The port interface for: tera_nor2 A : in (1) B : in (1) Z : out (1)
`static CellInterface[]`	`tera_or8_g.cell_interface`
`static CellInterface[]`	`tera_or7_g.cell_interface`
`static CellInterface[]`	`tera_or6_g.cell_interface`
`static CellInterface[]`	`tera_or5_g.cell_interface`
`static CellInterface[]`	`tera_or4_g.cell_interface`
`static CellInterface[]`	`tera_or3_g.cell_interface`
`static CellInterface[]`	`tera_or2_g.cell_interface`
`static CellInterface[]`	`tera_or8.cell_interface` The port interface for: tera_or8 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) H : in (1) Z : out (1)
`static CellInterface[]`	`tera_or7.cell_interface` The port interface for: tera_or7 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) Z : out (1)
`static CellInterface[]`	`tera_or6.cell_interface` The port interface for: tera_or6 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) Z : out (1)
`static CellInterface[]`	`tera_or5.cell_interface` The port interface for: tera_or5 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) Z : out (1)
`static CellInterface[]`	`tera_or4.cell_interface` The port interface for: tera_or4 A : in (1) B : in (1) C : in (1) D : in (1) Z : out (1)
`static CellInterface[]`	`tera_or3.cell_interface` The port interface for: tera_or3 A : in (1) B : in (1) C : in (1) Z : out (1)
`static CellInterface[]`	`tera_or2.cell_interface` The port interface for: tera_or2 A : in (1) B : in (1) Z : out (1)
`static CellInterface[]`	`tera_nand8_g.cell_interface`
`static CellInterface[]`	`tera_nand7_g.cell_interface`
`static CellInterface[]`	`tera_nand6_g.cell_interface`
`static CellInterface[]`	`tera_nand5_g.cell_interface`
`static CellInterface[]`	`tera_nand4_g.cell_interface`
`static CellInterface[]`	`tera_nand3_g.cell_interface`
`static CellInterface[]`	`tera_nand2_g.cell_interface`
`static CellInterface[]`	`tera_nand8.cell_interface` The port interface for: tera_nand8 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) H : in (1) Z : out (1)
`static CellInterface[]`	`tera_nand7.cell_interface` The port interface for: tera_nand7 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) Z : out (1)
`static CellInterface[]`	`tera_nand6.cell_interface` The port interface for: tera_nand6 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) Z : out (1)
`static CellInterface[]`	`tera_nand5.cell_interface` The port interface for: tera_nand5 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) Z : out (1)
`static CellInterface[]`	`tera_nand4.cell_interface` The port interface for: tera_nand4 A : in (1) B : in (1) C : in (1) D : in (1) Z : out (1)
`static CellInterface[]`	`tera_nand3.cell_interface` The port interface for: tera_nand3 A : in (1) B : in (1) C : in (1) Z : out (1)
`static CellInterface[]`	`tera_nand2.cell_interface` The port interface for: tera_nand2 A : in (1) B : in (1) Z : out (1)
`static CellInterface[]`	`tera_and8_g.cell_interface`
`static CellInterface[]`	`tera_and7_g.cell_interface`
`static CellInterface[]`	`tera_and6_g.cell_interface`
`static CellInterface[]`	`tera_and5_g.cell_interface`
`static CellInterface[]`	`tera_and4_g.cell_interface`
`static CellInterface[]`	`tera_and3_g.cell_interface`
`static CellInterface[]`	`tera_and2_g.cell_interface`
`static CellInterface[]`	`tera_and8.cell_interface` The port interface for: tera_and8 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) H : in (1) Z : out (1)
`static CellInterface[]`	`tera_and7.cell_interface` The port interface for: tera_and7 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) G : in (1) Z : out (1)
`static CellInterface[]`	`tera_and6.cell_interface` The port interface for: tera_and6 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) F : in (1) Z : out (1)
`static CellInterface[]`	`tera_and5.cell_interface` The port interface for: tera_and5 A : in (1) B : in (1) C : in (1) D : in (1) E : in (1) Z : out (1)
`static CellInterface[]`	`tera_and4.cell_interface` The port interface for: tera_and4 A : in (1) B : in (1) C : in (1) D : in (1) Z : out (1)
`static CellInterface[]`	`tera_and3.cell_interface` The port interface for: tera_and3 A : in (1) B : in (1) C : in (1) Z : out (1)
`static CellInterface[]`	`tera_and2.cell_interface` The port interface for: tera_and2 A : in (1) B : in (1) Z : out (1)
`static CellInterface[]`	`gndX.cell_interface`
`static CellInterface[]`	`addsubX.cell_interface`
`static CellInterface[]`	`regX.cell_interface`
`static CellInterface[]`	`subX.cell_interface`
`static CellInterface[]`	`muxX.cell_interface`
`static CellInterface[]`	`bufX.cell_interface`
`static CellInterface[]`	`vccX.cell_interface`
`static CellInterface[]`	`notX.cell_interface`
`static CellInterface[]`	`addX.cell_interface`
`static CellInterface[]`	`TERACL.implicit_interface`
`static CellInterface[]`	`Constant.cell_interface` The port interface for Constant: o: out("n") parameter: "n" (INTEGER).
`static CellInterface[]`	`ClockDriver.cell_interface`
`static CellInterface[]`	`FD.implicit_interface`
`static CellInterface[]`	`Shifter.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx

Fields in byucc.jhdl.Xilinx declared as CellInterface
`static CellInterface[]`	`ram_base.implicit_interface`
`static CellInterface[]`	`XilinxMemoryCL.implicit_interface`
`static CellInterface[]`	`ram_synch_shift.cell_interface` Deprecated.
`static CellInterface[]`	`ram_prop.cell_interface` Deprecated.
`static CellInterface[]`	`ram_prop.implicit_interface` Deprecated.
`static CellInterface[]`	`XilinxMemorySynch.implicit_interface`
`static CellInterface[]`	`bufg.cell_interface` The port interface for bufg: i: in (1) o: out (1)
`static CellInterface[]`	`vcc.cell_interface` The port interface for vcc: VCC: out (1)
`static CellInterface[]`	`XilinxClockDriver.cell_interface`
`static CellInterface[]`	`XilinxLatch.implicit_interface`
`static CellInterface[]`	`ram_synch.cell_interface` Deprecated.
`static CellInterface[]`	`gnd.cell_interface` The port interface for gnd: GND: out (1)
`static CellInterface[]`	`XilinxFD_1.implicit_interface`
`static CellInterface[]`	`XilinxMemorySynch_1.implicit_interface`
`static CellInterface[]`	`ramd_prop.cell_interface` Deprecated.
`static CellInterface[]`	`ramd_prop.implicit_interface` Deprecated.
`static CellInterface[]`	`XilinxCL.implicit_interface`
`static CellInterface[]`	`ramd_prop_1.cell_interface` Deprecated.
`static CellInterface[]`	`ramd_prop_1.implicit_interface` Deprecated.
`static CellInterface[]`	`Memory_1.implicit_interface`
`static CellInterface[]`	`XilinxFD.implicit_interface`
`static CellInterface[]`	`Constant.cell_interface` The port interface for Constant: o: out("n") param: "n" (INTEGER).
`static CellInterface[]`	`XilinxBasicMemoryCL.implicit_interface`
`static CellInterface[]`	`ram_synch_1.cell_interface` Deprecated.
`static CellInterface[]`	`Memory.implicit_interface`
`static CellInterface[]`	`ram_prop_1.cell_interface` Deprecated.
`static CellInterface[]`	`ram_prop_1.implicit_interface` Deprecated.

Uses of CellInterface in byucc.jhdl.Xilinx.demo

Fields in byucc.jhdl.Xilinx.demo declared as CellInterface
`static CellInterface[]`	`inc4.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex

Fields in byucc.jhdl.Xilinx.Virtex declared as CellInterface
`static CellInterface[]`	`fdce.cell_interface` The port interface for: fdce c : implicit (1) d : in (1) ce : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`ofd.cell_interface` The port interface for: ofd c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ildx_1.cell_interface` The port interface for: ildx_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ipad.cell_interface` Deprecated. The port interface for: ipad ipad : out (1)
`static CellInterface[]`	`fdce_g.cell_interface`
`static CellInterface[]`	`ram32x4s.cell_interface` The port interface for: ram32x4s d : sin (4) we : sin (1) a : sain (5) o : aout (4) wclk : implicit (1)
`static CellInterface[]`	`ram32x8s.cell_interface` The port interface for: ram32x8s d : sin (8) we : sin (1) a : sain (5) o : aout (8) wclk : implicit (1)
`static CellInterface[]`	`fmap.cell_interface` The port interface for: fmap i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`d3_8e.cell_interface` The port interface for: d3_8e a0 : in (1) a1 : in (1) a2 : in (1) e : in (1) d0 : out (1) d1 : out (1) d2 : out (1) d3 : out (1) d4 : out (1) d5 : out (1) d6 : out (1) d7 : out (1)
`static CellInterface[]`	`ofdxi.cell_interface` The port interface for: ofdxi c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdse_1_g.cell_interface`
`static CellInterface[]`	`buf_g.cell_interface`
`static CellInterface[]`	`fdr_1_g.cell_interface`
`static CellInterface[]`	`ram32x1s.cell_interface` The port interface for: ram32x1s d : sin (1) we : sin (1) a : sain (5) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`ldce.cell_interface` The port interface for: ldce clr : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdrs_1_g.cell_interface`
`static CellInterface[]`	`ibuf.cell_interface` The port interface for: ibuf i : in (1) o : out (1)
`static CellInterface[]`	`opad.cell_interface` Deprecated. The port interface for: opad opad : in (1)
`static CellInterface[]`	`ifdxi.cell_interface` The port interface for: ifdxi c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`ram16x4s.cell_interface` The port interface for: ram16x4s d : sin (4) we : sin (1) a : sain (4) o : aout (4) wclk : implicit (1)
`static CellInterface[]`	`obuft.cell_interface` The port interface for: obuft i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`fdp_1_g.cell_interface`
`static CellInterface[]`	`ofde.cell_interface` The port interface for: ofde c : implicit (1) d : in (1) e : in (1) o : out (1)
`static CellInterface[]`	`fdrse_1_g.cell_interface`
`static CellInterface[]`	`fdrs_1.cell_interface` The port interface for: fdrs_1 c : implicit (1) d : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`pullup_g.cell_interface`
`static CellInterface[]`	`pulldown_g.cell_interface`
`static CellInterface[]`	`fdrse_1.cell_interface` The port interface for: fdrse_1 c : implicit (1) d : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ibuf_g.cell_interface`
`static CellInterface[]`	`bufe.cell_interface` The port interface for: bufe i : in (1) e : in (1) o : out (1)
`static CellInterface[]`	`ldce_1.cell_interface` The port interface for: ldce_1 clr : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`obuf.cell_interface` The port interface for: obuf i : in (1) o : out (1)
`static CellInterface[]`	`fdc_1_g.cell_interface`
`static CellInterface[]`	`fdse_1.cell_interface` The port interface for: fdse_1 c : implicit (1) d : in (1) ce : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`iopad.cell_interface` Deprecated. The port interface for: iopad io : inout (1)
`static CellInterface[]`	`buf.cell_interface` The port interface for: buf i : in (1) o : out (1)
`static CellInterface[]`	`fdse.cell_interface` The port interface for: fdse c : implicit (1) d : in (1) ce : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`upad.cell_interface` The port interface for: upad io : inout (1)
`static CellInterface[]`	`ram16x4d.cell_interface` The port interface for: ram16x4d d : sin (4) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (4) dpo : aout (4) wclk : implicit (1)
`static CellInterface[]`	`ram16x8d.cell_interface` The port interface for: ram16x8d d : sin (8) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (8) dpo : aout (8) wclk : implicit (1)
`static CellInterface[]`	`ofdt.cell_interface` The port interface for: ofdt c : implicit (1) d : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`m2_1.cell_interface` The port interface for: m2_1 d0 : in (1) d1 : in (1) s0 : in (1) o : out (1)
`static CellInterface[]`	`ifd_1.cell_interface` The port interface for: ifd_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`pulldown.cell_interface` The port interface for: pulldown o : out (1)
`static CellInterface[]`	`fdpe.cell_interface` The port interface for: fdpe c : implicit (1) d : in (1) ce : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fds_1.cell_interface` The port interface for: fds_1 c : implicit (1) d : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`inv.cell_interface` The port interface for: inv i : in (1) o : out (1)
`static CellInterface[]`	`buft.cell_interface` The port interface for: buft i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ram16x1d.cell_interface` The port interface for: ram16x1d d : sin (1) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`ildxi_1.cell_interface` The port interface for: ildxi_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`rom16x1.cell_interface` The port interface for: rom16x1 a : in (4) o : out (1)
`static CellInterface[]`	`ipad_sim.cell_interface` Deprecated. The port interface for: ipad_sim i : in (1) ipad : out (1)
`static CellInterface[]`	`obuft_g.cell_interface`
`static CellInterface[]`	`ram16x8s.cell_interface` The port interface for: ram16x8s d : sin (8) we : sin (1) a : sain (4) o : aout (8) wclk : implicit (1)
`static CellInterface[]`	`ram32x2s.cell_interface` The port interface for: ram32x2s d : sin (2) we : sin (1) a : sain (5) o : aout (2) wclk : implicit (1)
`static CellInterface[]`	`fdp_1.cell_interface` The port interface for: fdp_1 c : implicit (1) d : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`ram16x2d.cell_interface` The port interface for: ram16x2d d : sin (2) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (2) dpo : aout (2) wclk : implicit (1)
`static CellInterface[]`	`ifd.cell_interface` The port interface for: ifd c : implicit (1) d : in (1) q : out (1) gsr : optionin (1)
`static CellInterface[]`	`fds_1_g.cell_interface`
`static CellInterface[]`	`fd_1.cell_interface` The port interface for: fd_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdrse.cell_interface` The port interface for: fdrse c : implicit (1) d : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ram16x1s.cell_interface` The port interface for: ram16x1s d : sin (1) we : sin (1) a : sain (4) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`fdpe_1.cell_interface` The port interface for: fdpe_1 c : implicit (1) d : in (1) ce : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`obuf_ann.cell_interface` The port interface for: obuf_ann i : in (1) o : out (1)
`static CellInterface[]`	`ifdi_1.cell_interface` The port interface for: ifdi_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ifdi.cell_interface` The port interface for: ifdi c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`m2_1_g.cell_interface`
`static CellInterface[]`	`ofdtxi.cell_interface` The port interface for: ofdtxi c : implicit (1) d : in (1) t : in (1) ce : in (1) o : out (1)
`static CellInterface[]`	`ram16x2s.cell_interface` The port interface for: ram16x2s d : sin (2) we : sin (1) a : sain (4) o : aout (2) wclk : implicit (1)
`static CellInterface[]`	`fdre_1.cell_interface` The port interface for: fdre_1 c : implicit (1) d : in (1) ce : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`fd.cell_interface` The port interface for: fd c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`rom32x1.cell_interface` The port interface for: rom32x1 a : in (5) o : out (1)
`static CellInterface[]`	`fdre_1_g.cell_interface`
`static CellInterface[]`	`ifdx.cell_interface` The port interface for: ifdx c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdr_1.cell_interface` The port interface for: fdr_1 c : implicit (1) d : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`inv_g.cell_interface`
`static CellInterface[]`	`pullup.cell_interface` The port interface for: pullup o : out (1)
`static CellInterface[]`	`ofdi.cell_interface` The port interface for: ofdi d : in (1) c : implicit (1) q : out (1)
`static CellInterface[]`	`ibuf_ann.cell_interface` The port interface for: ibuf_ann i : in (1) o : out (1)
`static CellInterface[]`	`ofdtx.cell_interface` The port interface for: ofdtx c : implicit (1) d : in (1) t : in (1) ce : in (1) o : out (1)
`static CellInterface[]`	`buft_g.cell_interface`
`static CellInterface[]`	`opad_sim.cell_interface` Deprecated. The port interface for: opad_sim opad : in (1) o : out (1)
`static CellInterface[]`	`fdrs.cell_interface` The port interface for: fdrs c : implicit (1) d : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`fdre.cell_interface` The port interface for: fdre c : implicit (1) d : in (1) ce : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`fdrs_g.cell_interface`
`static CellInterface[]`	`obuf_g.cell_interface`
`static CellInterface[]`	`ofdx.cell_interface` The port interface for: ofdx c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdpe_g.cell_interface`
`static CellInterface[]`	`fdrse_g.cell_interface`
`static CellInterface[]`	`xnor9.cell_interface`
`static CellInterface[]`	`xnor8.cell_interface`
`static CellInterface[]`	`xnor7.cell_interface`
`static CellInterface[]`	`xnor6.cell_interface`
`static CellInterface[]`	`xnor5.cell_interface`
`static CellInterface[]`	`xnor4_g.cell_interface`
`static CellInterface[]`	`xnor3_g.cell_interface`
`static CellInterface[]`	`xnor2_g.cell_interface`
`static CellInterface[]`	`xnor4.cell_interface` The port interface for: xnor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`xnor3.cell_interface` The port interface for: xnor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`xnor2.cell_interface` The port interface for: xnor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`xor9.cell_interface`
`static CellInterface[]`	`xor8.cell_interface`
`static CellInterface[]`	`xor7.cell_interface`
`static CellInterface[]`	`xor6.cell_interface`
`static CellInterface[]`	`xor5.cell_interface`
`static CellInterface[]`	`xor4_g.cell_interface`
`static CellInterface[]`	`xor3_g.cell_interface`
`static CellInterface[]`	`xor2_g.cell_interface`
`static CellInterface[]`	`xor4.cell_interface` The port interface for: xor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`xor3.cell_interface` The port interface for: xor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`xor2.cell_interface` The port interface for: xor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor9.cell_interface`
`static CellInterface[]`	`nor8.cell_interface`
`static CellInterface[]`	`nor7.cell_interface`
`static CellInterface[]`	`nor6.cell_interface`
`static CellInterface[]`	`nor5.cell_interface`
`static CellInterface[]`	`nor4_g.cell_interface`
`static CellInterface[]`	`nor3_g.cell_interface`
`static CellInterface[]`	`nor2_g.cell_interface`
`static CellInterface[]`	`nor4b4.cell_interface` The port interface for: nor4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b3.cell_interface` The port interface for: nor4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b2.cell_interface` The port interface for: nor4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b1.cell_interface` The port interface for: nor4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4.cell_interface` The port interface for: nor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor3b3.cell_interface` The port interface for: nor3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3b2.cell_interface` The port interface for: nor3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3b1.cell_interface` The port interface for: nor3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3.cell_interface` The port interface for: nor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor2b2.cell_interface` The port interface for: nor2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor2b1.cell_interface` The port interface for: nor2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor2.cell_interface` The port interface for: nor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or9.cell_interface`
`static CellInterface[]`	`or8.cell_interface`
`static CellInterface[]`	`or7.cell_interface`
`static CellInterface[]`	`or6.cell_interface`
`static CellInterface[]`	`or5.cell_interface`
`static CellInterface[]`	`or4_g.cell_interface`
`static CellInterface[]`	`or3_g.cell_interface`
`static CellInterface[]`	`or2_g.cell_interface`
`static CellInterface[]`	`or4b4.cell_interface` The port interface for: or4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b3.cell_interface` The port interface for: or4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b2.cell_interface` The port interface for: or4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b1.cell_interface` The port interface for: or4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4.cell_interface` The port interface for: or4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or3b3.cell_interface` The port interface for: or3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3b2.cell_interface` The port interface for: or3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3b1.cell_interface` The port interface for: or3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3.cell_interface` The port interface for: or3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or2b2.cell_interface` The port interface for: or2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or2b1.cell_interface` The port interface for: or2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or2.cell_interface` The port interface for: or2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand9.cell_interface`
`static CellInterface[]`	`nand8.cell_interface`
`static CellInterface[]`	`nand7.cell_interface`
`static CellInterface[]`	`nand6.cell_interface`
`static CellInterface[]`	`nand5.cell_interface`
`static CellInterface[]`	`nand4_g.cell_interface`
`static CellInterface[]`	`nand3_g.cell_interface`
`static CellInterface[]`	`nand2_g.cell_interface`
`static CellInterface[]`	`nand4b4.cell_interface` The port interface for: nand4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b3.cell_interface` The port interface for: nand4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b2.cell_interface` The port interface for: nand4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b1.cell_interface` The port interface for: nand4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4.cell_interface` The port interface for: nand4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand3b3.cell_interface` The port interface for: nand3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3b2.cell_interface` The port interface for: nand3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3b1.cell_interface` The port interface for: nand3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3.cell_interface` The port interface for: nand3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand2b2.cell_interface` The port interface for: nand2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand2b1.cell_interface` The port interface for: nand2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand2.cell_interface` The port interface for: nand2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and9.cell_interface`
`static CellInterface[]`	`and8.cell_interface`
`static CellInterface[]`	`and7.cell_interface`
`static CellInterface[]`	`and6.cell_interface`
`static CellInterface[]`	`and5.cell_interface`
`static CellInterface[]`	`and4_g.cell_interface`
`static CellInterface[]`	`and3_g.cell_interface`
`static CellInterface[]`	`and2_g.cell_interface`
`static CellInterface[]`	`and4b4.cell_interface` The port interface for: and4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b3.cell_interface` The port interface for: and4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b2.cell_interface` The port interface for: and4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b1.cell_interface` The port interface for: and4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4.cell_interface` The port interface for: and4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and3b3.cell_interface` The port interface for: and3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3b2.cell_interface` The port interface for: and3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3b1.cell_interface` The port interface for: and3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3.cell_interface` The port interface for: and3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and2b2.cell_interface` The port interface for: and2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and2b1.cell_interface` The port interface for: and2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and2.cell_interface` The port interface for: and2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`muxf6_d.cell_interface` The port interface for: muxf6_d i0 : in (1) i1 : in (1) s : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`lut3_d.cell_interface` The port interface for: lut3_d i : in (3) lo : out (1) o : out (1)
`static CellInterface[]`	`nandX.cell_interface`
`static CellInterface[]`	`ldcpe_1.cell_interface` The port interface for: ldcpe_1 clr : in (1) pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`xorcy_l.cell_interface` The port interface for: xorcy_l li : in (1) ci : in (1) lo : out (1)
`static CellInterface[]`	`fdcp_1.cell_interface` The port interface for: fdcp_1 c : implicit (1) d : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`ldc.cell_interface` The port interface for: ldc clr : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdr.cell_interface` The port interface for: fdr c : implicit (1) d : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`muxcy_l.cell_interface` The port interface for: muxcy_l di : in (1) ci : in (1) s : in (1) lo : out (1)
`static CellInterface[]`	`xnorX.cell_interface`
`static CellInterface[]`	`fdc_g.cell_interface`
`static CellInterface[]`	`obuft_agp.cell_interface` The port interface for: obuft_agp i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_ctt.cell_interface` The port interface for: obuft_ctt i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_sstl3_ii.cell_interface` The port interface for: obuft_sstl3_ii i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_sstl3_i.cell_interface` The port interface for: obuft_sstl3_i i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_sstl2_ii.cell_interface` The port interface for: obuft_sstl2_ii i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_sstl2_i.cell_interface` The port interface for: obuft_sstl2_i i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_hstl_iv.cell_interface` The port interface for: obuft_hstl_iv i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_hstl_iii.cell_interface` The port interface for: obuft_hstl_iii i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_hstl_i.cell_interface` The port interface for: obuft_hstl_i i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_gtlp.cell_interface` The port interface for: obuft_gtlp i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_gtl.cell_interface` The port interface for: obuft_gtl i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_pci66_3.cell_interface` The port interface for: obuft_pci66_3 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_pci33_5.cell_interface` The port interface for: obuft_pci33_5 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_pci33_3.cell_interface` The port interface for: obuft_pci33_3 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_lvcmos2.cell_interface` The port interface for: obuft_lvcmos2 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_24.cell_interface` The port interface for: obuft_f_24 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_16.cell_interface` The port interface for: obuft_f_16 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_12.cell_interface` The port interface for: obuft_f_12 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_8.cell_interface` The port interface for: obuft_f_8 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_6.cell_interface` The port interface for: obuft_f_6 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_4.cell_interface` The port interface for: obuft_f_4 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_2.cell_interface` The port interface for: obuft_f_2 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_24.cell_interface` The port interface for: obuft_s_24 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_16.cell_interface` The port interface for: obuft_s_16 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_12.cell_interface` The port interface for: obuft_s_12 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_8.cell_interface` The port interface for: obuft_s_8 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_6.cell_interface` The port interface for: obuft_s_6 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_4.cell_interface` The port interface for: obuft_s_4 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_2.cell_interface` The port interface for: obuft_s_2 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`fdce_1.cell_interface` The port interface for: fdce_1 c : implicit (1) d : in (1) ce : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`fdcp.cell_interface` The port interface for: fdcp c : implicit (1) d : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fdse_g.cell_interface`
`static CellInterface[]`	`muxf6_l.cell_interface` The port interface for: muxf6_l i0 : in (1) i1 : in (1) s : in (1) lo : out (1)
`static CellInterface[]`	`lut3_l.cell_interface` The port interface for: lut3_l i : in (3) lo : out (1)
`static CellInterface[]`	`ldcpe.cell_interface` The port interface for: ldcpe clr : in (1) pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`lut1.cell_interface` The port interface for: lut1 i0 : in (1) o : out (1)
`static CellInterface[]`	`fds_g.cell_interface`
`static CellInterface[]`	`ram32x1s_ack.cell_interface` The port interface for: ram32x1s_ack d : in (1) we : in (1) ra : in (5) wa : in (5) o : out (1) wclk : implicit (1)
`static CellInterface[]`	`fds.cell_interface` The port interface for: fds c : implicit (1) d : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`fde.cell_interface` The port interface for: fde c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`bufgs.cell_interface` The port interface for: bufgs i : in (1) o : out (1)
`static CellInterface[]`	`ld.cell_interface` The port interface for: ld g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`bufge.cell_interface` The port interface for: bufge i : in (1) o : out (1)
`static CellInterface[]`	`ram16x1s_1.cell_interface` The port interface for: ram16x1s_1 d : sin (1) we : sin (1) a : sain (4) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`xorcy.cell_interface` The port interface for: xorcy li : in (1) ci : in (1) o : out (1)
`static CellInterface[]`	`ldcp.cell_interface` The port interface for: ldcp clr : in (1) pre : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ldc_1.cell_interface` The port interface for: ldc_1 clr : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`lut2.cell_interface` The port interface for: lut2 i : in (2) o : out (1)
`static CellInterface[]`	`lde.cell_interface` The port interface for: lde ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`bufcf.cell_interface` The port interface for: bufcf i : in (1) o : out (1)
`static CellInterface[]`	`muxf5_d.cell_interface` The port interface for: muxf5_d i0 : in (1) i1 : in (1) s : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`lut2_d.cell_interface` The port interface for: lut2_d i : in (2) lo : out (1) o : out (1)
`static CellInterface[]`	`srl16e_1.cell_interface` The port interface for: srl16e_1 CLK : implicit (1) d : sin (1) ce : sin (1) a : ain (4) q : aout (1)
`static CellInterface[]`	`bscan_virtex.cell_interface` The port interface for: bscan_virtex tdo1 : in (1) tdo2 : in (1) update : out (1) shift : out (1) reset : out (1) tdi : out (1) sel1 : out (1) drck1 : out (1) sel2 : out (1) drck2 : out (1)
`static CellInterface[]`	`keeper.cell_interface` The port interface for: keeper o : out (1)
`static CellInterface[]`	`xorX.cell_interface`
`static CellInterface[]`	`clkdll.cell_interface` The port interface for: clkdll clkin : clk (1) clkfb : clk (1) rst : in (1) clk0 : out (1) clk90 : out (1) clk180 : out (1) clk270 : out (1) clk2x : out (1) clkdv : out (1) locked : out (1)
`static CellInterface[]`	`clkdll.implicit_interface`
`static CellInterface[]`	`ram32x1s_1.cell_interface` The port interface for: ram32x1s_1 d : sin (1) we : sin (1) a : sain (5) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`lut3.cell_interface` The port interface for: lut3 i : in (3) o : out (1)
`static CellInterface[]`	`mult_and.cell_interface` The port interface for: mult_and i0 : in (1) i1 : in (1) lo : out (1)
`static CellInterface[]`	`ldpe.cell_interface` The port interface for: ldpe pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ldp_1.cell_interface` The port interface for: ldp_1 pre : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`muxf5_l.cell_interface` The port interface for: muxf5_l i0 : in (1) i1 : in (1) s : in (1) lo : out (1)
`static CellInterface[]`	`andX.cell_interface`
`static CellInterface[]`	`lut2_l.cell_interface` The port interface for: lut2_l i : in (2) lo : out (1)
`static CellInterface[]`	`muxcy.cell_interface` The port interface for: muxcy di : in (1) ci : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`bufg_ann.cell_interface` The port interface for: bufg_ann i : in (1) o : out (1)
`static CellInterface[]`	`fdr_g.cell_interface`
`static CellInterface[]`	`orX.cell_interface`
`static CellInterface[]`	`fdre_g.cell_interface`
`static CellInterface[]`	`fdcpe.cell_interface` The port interface for: fdcpe c : implicit (1) d : in (1) ce : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`lde_1.cell_interface` The port interface for: lde_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`lut4.cell_interface` The port interface for: lut4 i : in (4) o : out (1)
`static CellInterface[]`	`bufgls.cell_interface` The port interface for: bufgls i : in (1) o : out (1)
`static CellInterface[]`	`ld_1.cell_interface` The port interface for: ld_1 g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`lut4_d.cell_interface` The port interface for: lut4_d i : in (4) lo : out (1) o : out (1)
`static CellInterface[]`	`ldpe_1.cell_interface` The port interface for: ldpe_1 pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ldcp_1.cell_interface` The port interface for: ldcp_1 clr : in (1) pre : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`capture_virtex.cell_interface` The port interface for: capture_virtex cap : in (1) clk : in (1)
`static CellInterface[]`	`fdc_1.cell_interface` The port interface for: fdc_1 c : implicit (1) d : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`lut1_d.cell_interface` The port interface for: lut1_d i0 : in (1) lo : out (1) o : out (1)
`static CellInterface[]`	`srl16e.cell_interface` The port interface for: srl16e CLK : implicit (1) d : sin (1) ce : sin (1) a : ain (4) q : aout (1)
`static CellInterface[]`	`muxf5.cell_interface` The port interface for: muxf5 i0 : in (1) i1 : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`fdcpe_1.cell_interface` The port interface for: fdcpe_1 c : implicit (1) d : in (1) ce : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fdp.cell_interface` The port interface for: fdp c : implicit (1) d : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`obuf_agp.cell_interface` The port interface for: obuf_agp i : in (1) o : out (1)
`static CellInterface[]`	`obuf_ctt.cell_interface` The port interface for: obuf_ctt i : in (1) o : out (1)
`static CellInterface[]`	`obuf_sstl3_ii.cell_interface` The port interface for: obuf_sstl3_ii i : in (1) o : out (1)
`static CellInterface[]`	`obuf_sstl3_i.cell_interface` The port interface for: obuf_sstl3_i i : in (1) o : out (1)
`static CellInterface[]`	`obuf_sstl2_ii.cell_interface` The port interface for: obuf_sstl2_ii i : in (1) o : out (1)
`static CellInterface[]`	`obuf_sstl2_i.cell_interface` The port interface for: obuf_sstl2_i i : in (1) o : out (1)
`static CellInterface[]`	`obuf_hstl_iv.cell_interface` The port interface for: obuf_hstl_iv i : in (1) o : out (1)
`static CellInterface[]`	`obuf_hstl_iii.cell_interface` The port interface for: obuf_hstl_iii i : in (1) o : out (1)
`static CellInterface[]`	`obuf_hstl_i.cell_interface` The port interface for: obuf_hstl_i i : in (1) o : out (1)
`static CellInterface[]`	`obuf_gtlp.cell_interface` The port interface for: obuf_gtlp i : in (1) o : out (1)
`static CellInterface[]`	`obuf_gtl.cell_interface` The port interface for: obuf_gtl i : in (1) o : out (1)
`static CellInterface[]`	`obuf_pci66_3.cell_interface` The port interface for: obuf_pci66_3 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_pci33_5.cell_interface` The port interface for: obuf_pci33_5 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_pci33_3.cell_interface` The port interface for: obuf_pci33_3 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_lvcmos2.cell_interface` The port interface for: obuf_lvcmos2 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_24.cell_interface` The port interface for: obuf_f_24 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_16.cell_interface` The port interface for: obuf_f_16 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_12.cell_interface` The port interface for: obuf_f_12 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_8.cell_interface` The port interface for: obuf_f_8 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_6.cell_interface` The port interface for: obuf_f_6 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_4.cell_interface` The port interface for: obuf_f_4 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_2.cell_interface` The port interface for: obuf_f_2 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_24.cell_interface` The port interface for: obuf_s_24 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_16.cell_interface` The port interface for: obuf_s_16 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_12.cell_interface` The port interface for: obuf_s_12 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_8.cell_interface` The port interface for: obuf_s_8 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_6.cell_interface` The port interface for: obuf_s_6 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_4.cell_interface` The port interface for: obuf_s_4 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_2.cell_interface` The port interface for: obuf_s_2 i : in (1) o : out (1)
`static CellInterface[]`	`ram16x1d_1.cell_interface` The port interface for: ram16x1d_1 d : sin (1) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`lut4_l.cell_interface` The port interface for: lut4_l i : in (4) lo : out (1)
`static CellInterface[]`	`ibufg_agp.cell_interface` The port interface for: ibufg_agp i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_ctt.cell_interface` The port interface for: ibufg_ctt i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl3_ii.cell_interface` The port interface for: ibufg_sstl3_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl3_i.cell_interface` The port interface for: ibufg_sstl3_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl2_ii.cell_interface` The port interface for: ibufg_sstl2_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl2_i.cell_interface` The port interface for: ibufg_sstl2_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_iv.cell_interface` The port interface for: ibufg_hstl_iv i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_iii.cell_interface` The port interface for: ibufg_hstl_iii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_i.cell_interface` The port interface for: ibufg_hstl_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_gtlp.cell_interface` The port interface for: ibufg_gtlp i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_gtl.cell_interface` The port interface for: ibufg_gtl i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci66_3.cell_interface` The port interface for: ibufg_pci66_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci33_5.cell_interface` The port interface for: ibufg_pci33_5 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci33_3.cell_interface` The port interface for: ibufg_pci33_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_lvcmos2.cell_interface` The port interface for: ibufg_lvcmos2 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg.cell_interface` The port interface for: ibufg i : in (1) o : out (1)
`static CellInterface[]`	`clkdllhf.cell_interface` The port interface for: clkdllhf clkin : clk (1) clkfb : clk (1) rst : in (1) clk0 : out (1) clk180 : out (1) clkdv : out (1) locked : out (1)
`static CellInterface[]`	`clkdllhf.implicit_interface`
`static CellInterface[]`	`lut1_l.cell_interface` The port interface for: lut1_l i0 : in (1) lo : out (1)
`static CellInterface[]`	`xorcy_d.cell_interface` The port interface for: xorcy_d li : in (1) ci : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`srl16_1.cell_interface` The port interface for: srl16_1 CLK : implicit (1) d : sin (1) a : ain (4) q : aout (1)
`static CellInterface[]`	`ldp.cell_interface` The port interface for: ldp pre : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`muxf6.cell_interface` The port interface for: muxf6 i0 : in (1) i1 : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`muxcy_d.cell_interface` The port interface for: muxcy_d di : in (1) ci : in (1) s : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`fdc.cell_interface` The port interface for: fdc c : implicit (1) d : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`norX.cell_interface`
`static CellInterface[]`	`fdp_g.cell_interface`
`static CellInterface[]`	`startup_virtex.cell_interface` The port interface for: startup_virtex gsr : in (1) gts : in (1) clk : clk ()
`static CellInterface[]`	`fde_1.cell_interface` The port interface for: fde_1 c : implicit (1) ce : in (1) d : in (1) q : out (1)
`static CellInterface[]`	`srl16.cell_interface` The port interface for: srl16 CLK : implicit (1) d : sin (1) a : ain (4) q : aout (1)
`static CellInterface[]`	`ibuf_agp.cell_interface` The port interface for: ibuf_agp i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_ctt.cell_interface` The port interface for: ibuf_ctt i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_sstl3_ii.cell_interface` The port interface for: ibuf_sstl3_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_sstl3_i.cell_interface` The port interface for: ibuf_sstl3_i i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_sstl2_ii.cell_interface` The port interface for: ibuf_sstl2_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_sstl2_i.cell_interface` The port interface for: ibuf_sstl2_i i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_hstl_iv.cell_interface` The port interface for: ibuf_hstl_iv i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_hstl_iii.cell_interface` The port interface for: ibuf_hstl_iii i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_hstl_i.cell_interface` The port interface for: ibuf_hstl_i i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_gtlp.cell_interface` The port interface for: ibuf_gtlp i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_gtl.cell_interface` The port interface for: ibuf_gtl i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_pci66_3.cell_interface` The port interface for: ibuf_pci66_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_pci33_5.cell_interface` The port interface for: ibuf_pci33_5 i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_pci33_3.cell_interface` The port interface for: ibuf_pci33_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_lvcmos2.cell_interface` The port interface for: ibuf_lvcmos2 i : in (1) o : out (1)
`static CellInterface[]`	`iobuf_agp.cell_interface` The port interface for: iobuf_agp i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_ctt.cell_interface` The port interface for: iobuf_ctt i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_sstl3_ii.cell_interface` The port interface for: iobuf_sstl3_ii i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_sstl3_i.cell_interface` The port interface for: iobuf_sstl3_i i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_sstl2_ii.cell_interface` The port interface for: iobuf_sstl2_ii i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_sstl2_i.cell_interface` The port interface for: iobuf_sstl2_i i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_hstl_iv.cell_interface` The port interface for: iobuf_hstl_iv i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_hstl_iii.cell_interface` The port interface for: iobuf_hstl_iii i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_hstl_i.cell_interface` The port interface for: iobuf_hstl_i i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_gtlp.cell_interface` The port interface for: iobuf_gtlp i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_gtl.cell_interface` The port interface for: iobuf_gtl i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_pci66_3.cell_interface` The port interface for: iobuf_pci66_3 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_pci33_5.cell_interface` The port interface for: iobuf_pci33_5 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_pci33_3.cell_interface` The port interface for: iobuf_pci33_3 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_lvcmos2.cell_interface` The port interface for: iobuf_lvcmos2 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_24.cell_interface` The port interface for: iobuf_f_24 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_16.cell_interface` The port interface for: iobuf_f_16 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_12.cell_interface` The port interface for: iobuf_f_12 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_8.cell_interface` The port interface for: iobuf_f_8 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_6.cell_interface` The port interface for: iobuf_f_6 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_4.cell_interface` The port interface for: iobuf_f_4 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_2.cell_interface` The port interface for: iobuf_f_2 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_24.cell_interface` The port interface for: iobuf_s_24 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_16.cell_interface` The port interface for: iobuf_s_16 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_12.cell_interface` The port interface for: iobuf_s_12 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_8.cell_interface` The port interface for: iobuf_s_8 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_6.cell_interface` The port interface for: iobuf_s_6 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_4.cell_interface` The port interface for: iobuf_s_4 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_2.cell_interface` The port interface for: iobuf_s_2 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf.cell_interface` The port interface for: iobuf i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`SimulationBuffer.cell_interface`
`static CellInterface[]`	`norX_g.cell_interface`
`static CellInterface[]`	`vcc.cell_interface` The port interface for vcc: VCC: out (1)
`static CellInterface[]`	`RAMB4Single.implicit_interface`
`static CellInterface[]`	`RAMB4Single.cell_interface`
`static CellInterface[]`	`BlockRam.implicit_interface` Deprecated.
`static CellInterface[]`	`BlockRam.cell_interface` Deprecated.
`static CellInterface[]`	`nandX_g.cell_interface`
`static CellInterface[]`	`RAMB4Dual_rb.cell_interface`
`static CellInterface[]`	`RAMB4Single_rb.cell_interface`
`static CellInterface[]`	`orX_g.cell_interface`
`static CellInterface[]`	`bufg.cell_interface` The port interface for bufg: i: in (1) o: out (1)
`static CellInterface[]`	`gnd.cell_interface` The port interface for gnd: GND: out (1)
`static CellInterface[]`	`BlockRamView.implicit_interface`
`static CellInterface[]`	`BlockRamView.cell_interface`
`static CellInterface[]`	`andX_g.cell_interface`
`static CellInterface[]`	`RAMB4Dual.implicit_interface`
`static CellInterface[]`	`RAMB4Dual.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex.helpers

Fields in byucc.jhdl.Xilinx.Virtex.helpers declared as CellInterface
`static CellInterface[]`	`adder.cell_interface`
`static CellInterface[]`	`Subtractor.cell_interface`
`static CellInterface[]`	`adderSubtractor.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex.Modules

Fields in byucc.jhdl.Xilinx.Virtex.Modules declared as CellInterface
`static CellInterface[]`	`P2DSconv.cell_interface`
`static CellInterface[]`	`KCMMult.cell_interface`
`static CellInterface[]`	`ramrom.cell_interface`
`static CellInterface[]`	`S2Pconv.cell_interface`
`static CellInterface[]`	`Equals.cell_interface` The ports and parameters of this module.
`static CellInterface[]`	`srl_array.cell_interface` Deprecated.
`static CellInterface[]`	`ParellelDSMult.cell_interface`
`static CellInterface[]`	`PriorityEncoder.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`DS2Pconv.cell_interface`
`static CellInterface[]`	`Shifter.cell_interface`
`static CellInterface[]`	`mux81.cell_interface`
`static CellInterface[]`	`SRLFifo.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`upcnt.cell_interface`
`static CellInterface[]`	`upcnt.implicit_interface`
`static CellInterface[]`	`DSMult.cell_interface`
`static CellInterface[]`	`SRLArray.cell_interface`
`static CellInterface[]`	`Priority.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`Mux.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`downcnt.cell_interface`
`static CellInterface[]`	`downcnt.implicit_interface`
`static CellInterface[]`	`arrayMult.cell_interface` Standard JHDL CellInterface.
`static CellInterface[]`	`delay.cell_interface`
`static CellInterface[]`	`mux41.cell_interface`
`static CellInterface[]`	`booth.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack

Fields in byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack declared as CellInterface
`static CellInterface[]`	`MultCell.cell_interface`
`static CellInterface[]`	`MultRow.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack

Fields in byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack declared as CellInterface
`static CellInterface[]`	`KCM_ROM.cell_interface`
`static CellInterface[]`	`KCMRom_Adder.cell_interface`
`static CellInterface[]`	`KCMRom_AdderBit.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack

Fields in byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack declared as CellInterface
`static CellInterface[]`	`MultAddVirtex.cell_interface`
`static CellInterface[]`	`MultSub.cell_interface`
`static CellInterface[]`	`And_fmap_g.cell_interface`
`static CellInterface[]`	`MultAdd.cell_interface`
`static CellInterface[]`	`multCol.cell_interface`
`static CellInterface[]`	`EXAMINE_CI_Virtex.cell_interface`
`static CellInterface[]`	`MultSubVirtex.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack

Fields in byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack declared as CellInterface
`static CellInterface[]`	`ShiftBit.cell_interface`
`static CellInterface[]`	`RightShiftReg.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex.ramb4_wrapper

Fields in byucc.jhdl.Xilinx.Virtex.ramb4_wrapper declared as CellInterface
`static CellInterface[]`	`RAMB4_Single.implicit_interface`
`static CellInterface[]`	`RAMB4_Single.cell_interface`
`static CellInterface[]`	`RAMB4_Dual.implicit_interface`
`static CellInterface[]`	`RAMB4_Dual.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex2

Fields in byucc.jhdl.Xilinx.Virtex2 declared as CellInterface
`static CellInterface[]`	`fdce.cell_interface` The port interface for: fdce c : implicit (1) d : in (1) ce : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`ofd.cell_interface` The port interface for: ofd c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ildx_1.cell_interface` The port interface for: ildx_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ipad.cell_interface` Deprecated. The port interface for: ipad ipad : out (1)
`static CellInterface[]`	`fdce_g.cell_interface`
`static CellInterface[]`	`ram32x4s.cell_interface` The port interface for: ram32x4s d : sin (4) we : sin (1) a : sain (5) o : aout (4) wclk : implicit (1)
`static CellInterface[]`	`ram32x8s.cell_interface` The port interface for: ram32x8s d : sin (8) we : sin (1) a : sain (5) o : aout (8) wclk : implicit (1)
`static CellInterface[]`	`fmap.cell_interface` The port interface for: fmap i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`d3_8e.cell_interface` The port interface for: d3_8e a0 : in (1) a1 : in (1) a2 : in (1) e : in (1) d0 : out (1) d1 : out (1) d2 : out (1) d3 : out (1) d4 : out (1) d5 : out (1) d6 : out (1) d7 : out (1)
`static CellInterface[]`	`ofdxi.cell_interface` The port interface for: ofdxi c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdse_1_g.cell_interface`
`static CellInterface[]`	`buf_g.cell_interface`
`static CellInterface[]`	`fdr_1_g.cell_interface`
`static CellInterface[]`	`ram32x1s.cell_interface` The port interface for: ram32x1s d : sin (1) we : sin (1) a : sain (5) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`fdrs_1_g.cell_interface`
`static CellInterface[]`	`ibuf.cell_interface` The port interface for: ibuf i : in (1) o : out (1)
`static CellInterface[]`	`opad.cell_interface` Deprecated. The port interface for: opad opad : in (1)
`static CellInterface[]`	`ifdxi.cell_interface` The port interface for: ifdxi c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`ram16x4s.cell_interface` The port interface for: ram16x4s d : sin (4) we : sin (1) a : sain (4) o : aout (4) wclk : implicit (1)
`static CellInterface[]`	`obuft.cell_interface` The port interface for: obuft i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ibufgds_lvdsext_25.cell_interface` The port interface for: ibufgds_lvdsext_25 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`fdp_1_g.cell_interface`
`static CellInterface[]`	`ofde.cell_interface` The port interface for: ofde c : implicit (1) d : in (1) e : in (1) o : out (1)
`static CellInterface[]`	`fde.cell_interface` The port interface for: fde c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdrse_1_g.cell_interface`
`static CellInterface[]`	`fdrs_1.cell_interface` The port interface for: fdrs_1 c : implicit (1) d : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`pullup_g.cell_interface`
`static CellInterface[]`	`pulldown_g.cell_interface`
`static CellInterface[]`	`fdrse_1.cell_interface` The port interface for: fdrse_1 c : implicit (1) d : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ibuf_g.cell_interface`
`static CellInterface[]`	`bufe.cell_interface` The port interface for: bufe i : in (1) e : in (1) o : out (1)
`static CellInterface[]`	`iobuf_sstl2_ii_dci.cell_interface` The port interface for: iobuf_sstl2_ii_dci i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`fdc_1.cell_interface` The port interface for: fdc_1 c : implicit (1) d : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`obuf.cell_interface` The port interface for: obuf i : in (1) o : out (1)
`static CellInterface[]`	`fdc_1_g.cell_interface`
`static CellInterface[]`	`fdse_1.cell_interface` The port interface for: fdse_1 c : implicit (1) d : in (1) ce : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`iopad.cell_interface` Deprecated. The port interface for: iopad io : inout (1)
`static CellInterface[]`	`buf.cell_interface` The port interface for: buf i : in (1) o : out (1)
`static CellInterface[]`	`fdse.cell_interface` The port interface for: fdse c : implicit (1) d : in (1) ce : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`rom256x1.implicit_interface`
`static CellInterface[]`	`rom256x1.cell_interface`
`static CellInterface[]`	`upad.cell_interface` The port interface for: upad io : inout (1)
`static CellInterface[]`	`ram16x4d.cell_interface` The port interface for: ram16x4d d : sin (4) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (4) dpo : aout (4) wclk : implicit (1)
`static CellInterface[]`	`ram16x8d.cell_interface` The port interface for: ram16x8d d : sin (8) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (8) dpo : aout (8) wclk : implicit (1)
`static CellInterface[]`	`ofdt.cell_interface` The port interface for: ofdt c : implicit (1) d : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`m2_1.cell_interface` The port interface for: m2_1 d0 : in (1) d1 : in (1) s0 : in (1) o : out (1)
`static CellInterface[]`	`ifd_1.cell_interface` The port interface for: ifd_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`pulldown.cell_interface` The port interface for: pulldown o : out (1)
`static CellInterface[]`	`fdpe.cell_interface` The port interface for: fdpe c : implicit (1) d : in (1) ce : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fds_1.cell_interface` The port interface for: fds_1 c : implicit (1) d : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`inv.cell_interface` The port interface for: inv i : in (1) o : out (1)
`static CellInterface[]`	`buft.cell_interface` The port interface for: buft i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ram16x1d.cell_interface` The port interface for: ram16x1d d : sin (1) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`ildxi_1.cell_interface` The port interface for: ildxi_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`rom16x1.cell_interface` The port interface for: rom16x1 a : in (4) o : out (1)
`static CellInterface[]`	`ipad_sim.cell_interface` Deprecated. The port interface for: ipad_sim i : in (1) ipad : out (1)
`static CellInterface[]`	`rom64x1.implicit_interface`
`static CellInterface[]`	`rom64x1.cell_interface`
`static CellInterface[]`	`ibufg_lvttl.cell_interface` The port interface for: ibufg_lvttl i : in (1) o : out (1)
`static CellInterface[]`	`obuft_g.cell_interface`
`static CellInterface[]`	`fdp_1.cell_interface` The port interface for: fdp_1 c : implicit (1) d : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`obuf_sstl2_i_dci.cell_interface` The port interface for: obuf_sstl2_i_dci i : in (1) o : out (1)
`static CellInterface[]`	`obuf_lvttl_f_12.cell_interface` The port interface for: obuf_lvttl_f_12 i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_lvttl.cell_interface` The port interface for: ibuf_lvttl i : in (1) o : out (1)
`static CellInterface[]`	`ram32x2s.cell_interface` The port interface for: ram32x2s d : sin (2) we : sin (1) a : sain (5) o : aout (2) wclk : implicit (1)
`static CellInterface[]`	`ram16x2d.cell_interface` The port interface for: ram16x2d d : sin (2) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (2) dpo : aout (2) wclk : implicit (1)
`static CellInterface[]`	`ifd.cell_interface` The port interface for: ifd c : implicit (1) d : in (1) q : out (1) gsr : optionin (1)
`static CellInterface[]`	`fds_1_g.cell_interface`
`static CellInterface[]`	`fd_1.cell_interface` The port interface for: fd_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdrse.cell_interface` The port interface for: fdrse c : implicit (1) d : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ram16x1s.cell_interface` The port interface for: ram16x1s d : sin (1) we : sin (1) a : sain (4) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`fdpe_1.cell_interface` The port interface for: fdpe_1 c : implicit (1) d : in (1) ce : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`obuf_ann.cell_interface` The port interface for: obuf_ann i : in (1) o : out (1)
`static CellInterface[]`	`ifdi_1.cell_interface` The port interface for: ifdi_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ifdi.cell_interface` The port interface for: ifdi c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`obuft_sstl2_i_dci.cell_interface` The port interface for: obuft_sstl2_i_dci i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`fdce_1.cell_interface` The port interface for: fdce_1 c : implicit (1) d : in (1) ce : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`m2_1_g.cell_interface`
`static CellInterface[]`	`ofdtxi.cell_interface` The port interface for: ofdtxi c : implicit (1) d : in (1) t : in (1) ce : in (1) o : out (1)
`static CellInterface[]`	`ram16x2s.cell_interface` The port interface for: ram16x2s d : sin (2) we : sin (1) a : sain (4) o : aout (2) wclk : implicit (1)
`static CellInterface[]`	`fdre_1.cell_interface` The port interface for: fdre_1 c : implicit (1) d : in (1) ce : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`fd.cell_interface` The port interface for: fd c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`rom128x1.implicit_interface`
`static CellInterface[]`	`rom128x1.cell_interface`
`static CellInterface[]`	`rom32x1.cell_interface` The port interface for: rom32x1 a : in (5) o : out (1)
`static CellInterface[]`	`ibufgds_lvds_25.cell_interface` The port interface for: ibufgds_lvds_25 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`fdre_1_g.cell_interface`
`static CellInterface[]`	`ifdx.cell_interface` The port interface for: ifdx c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdr_1.cell_interface` The port interface for: fdr_1 c : implicit (1) d : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`inv_g.cell_interface`
`static CellInterface[]`	`pullup.cell_interface` The port interface for: pullup o : out (1)
`static CellInterface[]`	`ofdi.cell_interface` The port interface for: ofdi d : in (1) c : implicit (1) q : out (1)
`static CellInterface[]`	`ibuf_ann.cell_interface` The port interface for: ibuf_ann i : in (1) o : out (1)
`static CellInterface[]`	`obufds_lvdsext_25.cell_interface` The port interface for: obufds_lvdsext_25 i : in (1) o : out (1) ob : out (1)
`static CellInterface[]`	`ofdtx.cell_interface` The port interface for: ofdtx c : implicit (1) d : in (1) t : in (1) ce : in (1) o : out (1)
`static CellInterface[]`	`fde_1.cell_interface` The port interface for: fde_1 c : implicit (1) ce : in (1) d : in (1) q : out (1)
`static CellInterface[]`	`buft_g.cell_interface`
`static CellInterface[]`	`opad_sim.cell_interface` Deprecated. The port interface for: opad_sim opad : in (1) o : out (1)
`static CellInterface[]`	`fdrs.cell_interface` The port interface for: fdrs c : implicit (1) d : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`fdre.cell_interface` The port interface for: fdre c : implicit (1) d : in (1) ce : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`fdrs_g.cell_interface`
`static CellInterface[]`	`obuf_g.cell_interface`
`static CellInterface[]`	`ofdx.cell_interface` The port interface for: ofdx c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdpe_g.cell_interface`
`static CellInterface[]`	`fdrse_g.cell_interface`
`static CellInterface[]`	`obufds_lvds_25.cell_interface` The port interface for: obufds_lvds_25 i : in (1) o : out (1) ob : out (1)
`static CellInterface[]`	`xnor9.cell_interface`
`static CellInterface[]`	`xnor8.cell_interface`
`static CellInterface[]`	`xnor7.cell_interface`
`static CellInterface[]`	`xnor6.cell_interface`
`static CellInterface[]`	`xnor5.cell_interface`
`static CellInterface[]`	`xnor4_g.cell_interface`
`static CellInterface[]`	`xnor3_g.cell_interface`
`static CellInterface[]`	`xnor2_g.cell_interface`
`static CellInterface[]`	`xnor4.cell_interface` The port interface for: xnor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`xnor3.cell_interface` The port interface for: xnor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`xnor2.cell_interface` The port interface for: xnor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`xor9.cell_interface`
`static CellInterface[]`	`xor8.cell_interface`
`static CellInterface[]`	`xor7.cell_interface`
`static CellInterface[]`	`xor6.cell_interface`
`static CellInterface[]`	`xor5.cell_interface`
`static CellInterface[]`	`xor4_g.cell_interface`
`static CellInterface[]`	`xor3_g.cell_interface`
`static CellInterface[]`	`xor2_g.cell_interface`
`static CellInterface[]`	`xor4.cell_interface` The port interface for: xor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`xor3.cell_interface` The port interface for: xor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`xor2.cell_interface` The port interface for: xor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor9.cell_interface`
`static CellInterface[]`	`nor8.cell_interface`
`static CellInterface[]`	`nor7.cell_interface`
`static CellInterface[]`	`nor6.cell_interface`
`static CellInterface[]`	`nor5.cell_interface`
`static CellInterface[]`	`nor4_g.cell_interface`
`static CellInterface[]`	`nor3_g.cell_interface`
`static CellInterface[]`	`nor2_g.cell_interface`
`static CellInterface[]`	`nor4b4.cell_interface` The port interface for: nor4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b3.cell_interface` The port interface for: nor4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b2.cell_interface` The port interface for: nor4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b1.cell_interface` The port interface for: nor4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4.cell_interface` The port interface for: nor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor3b3.cell_interface` The port interface for: nor3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3b2.cell_interface` The port interface for: nor3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3b1.cell_interface` The port interface for: nor3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3.cell_interface` The port interface for: nor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor2b2.cell_interface` The port interface for: nor2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor2b1.cell_interface` The port interface for: nor2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor2.cell_interface` The port interface for: nor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or9.cell_interface`
`static CellInterface[]`	`or8.cell_interface`
`static CellInterface[]`	`or7.cell_interface`
`static CellInterface[]`	`or6.cell_interface`
`static CellInterface[]`	`or5.cell_interface`
`static CellInterface[]`	`or4_g.cell_interface`
`static CellInterface[]`	`or3_g.cell_interface`
`static CellInterface[]`	`or2_g.cell_interface`
`static CellInterface[]`	`or4b4.cell_interface` The port interface for: or4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b3.cell_interface` The port interface for: or4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b2.cell_interface` The port interface for: or4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b1.cell_interface` The port interface for: or4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4.cell_interface` The port interface for: or4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or3b3.cell_interface` The port interface for: or3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3b2.cell_interface` The port interface for: or3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3b1.cell_interface` The port interface for: or3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3.cell_interface` The port interface for: or3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or2b2.cell_interface` The port interface for: or2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or2b1.cell_interface` The port interface for: or2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or2.cell_interface` The port interface for: or2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand9.cell_interface`
`static CellInterface[]`	`nand8.cell_interface`
`static CellInterface[]`	`nand7.cell_interface`
`static CellInterface[]`	`nand6.cell_interface`
`static CellInterface[]`	`nand5.cell_interface`
`static CellInterface[]`	`nand4_g.cell_interface`
`static CellInterface[]`	`nand3_g.cell_interface`
`static CellInterface[]`	`nand2_g.cell_interface`
`static CellInterface[]`	`nand4b4.cell_interface` The port interface for: nand4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b3.cell_interface` The port interface for: nand4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b2.cell_interface` The port interface for: nand4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b1.cell_interface` The port interface for: nand4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4.cell_interface` The port interface for: nand4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand3b3.cell_interface` The port interface for: nand3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3b2.cell_interface` The port interface for: nand3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3b1.cell_interface` The port interface for: nand3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3.cell_interface` The port interface for: nand3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand2b2.cell_interface` The port interface for: nand2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand2b1.cell_interface` The port interface for: nand2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand2.cell_interface` The port interface for: nand2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and9.cell_interface`
`static CellInterface[]`	`and8.cell_interface`
`static CellInterface[]`	`and7.cell_interface`
`static CellInterface[]`	`and6.cell_interface`
`static CellInterface[]`	`and5.cell_interface`
`static CellInterface[]`	`and4_g.cell_interface`
`static CellInterface[]`	`and3_g.cell_interface`
`static CellInterface[]`	`and2_g.cell_interface`
`static CellInterface[]`	`and4b4.cell_interface` The port interface for: and4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b3.cell_interface` The port interface for: and4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b2.cell_interface` The port interface for: and4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b1.cell_interface` The port interface for: and4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4.cell_interface` The port interface for: and4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and3b3.cell_interface` The port interface for: and3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3b2.cell_interface` The port interface for: and3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3b1.cell_interface` The port interface for: and3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3.cell_interface` The port interface for: and3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and2b2.cell_interface` The port interface for: and2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and2b1.cell_interface` The port interface for: and2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and2.cell_interface` The port interface for: and2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`startbuf_architecture.cell_interface` The port interface for: startbuf_architecture gsrin : in (1) gtsin : in (1) clkin : in (1) gsrout : out (1) gtsout : out (1)
`static CellInterface[]`	`bufgce_1.cell_interface` The port interface for: bufgce_1 i : clk (1) ce : in (1) o : out (1)
`static CellInterface[]`	`orcy.cell_interface` The port interface for: orcy i : in (1) ci : in (1) o : out (1)
`static CellInterface[]`	`obuf_agp.cell_interface` The port interface for: obuf_agp i : in (1) o : out (1)
`static CellInterface[]`	`obuf_ctt.cell_interface` The port interface for: obuf_ctt i : in (1) o : out (1)
`static CellInterface[]`	`obuf_sstl3_ii.cell_interface` The port interface for: obuf_sstl3_ii i : in (1) o : out (1)
`static CellInterface[]`	`obuf_sstl3_i.cell_interface` The port interface for: obuf_sstl3_i i : in (1) o : out (1)
`static CellInterface[]`	`obuf_sstl2_ii.cell_interface` The port interface for: obuf_sstl2_ii i : in (1) o : out (1)
`static CellInterface[]`	`obuf_sstl2_i.cell_interface` The port interface for: obuf_sstl2_i i : in (1) o : out (1)
`static CellInterface[]`	`obuf_hstl_iv.cell_interface` The port interface for: obuf_hstl_iv i : in (1) o : out (1)
`static CellInterface[]`	`obuf_hstl_iii.cell_interface` The port interface for: obuf_hstl_iii i : in (1) o : out (1)
`static CellInterface[]`	`obuf_hstl_i.cell_interface` The port interface for: obuf_hstl_i i : in (1) o : out (1)
`static CellInterface[]`	`obuf_gtlp.cell_interface` The port interface for: obuf_gtlp i : in (1) o : out (1)
`static CellInterface[]`	`obuf_gtl.cell_interface` The port interface for: obuf_gtl i : in (1) o : out (1)
`static CellInterface[]`	`obuf_pci66_3.cell_interface` The port interface for: obuf_pci66_3 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_pci33_5.cell_interface` The port interface for: obuf_pci33_5 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_pci33_3.cell_interface` The port interface for: obuf_pci33_3 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_lvcmos2.cell_interface` The port interface for: obuf_lvcmos2 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_24.cell_interface` The port interface for: obuf_f_24 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_16.cell_interface` The port interface for: obuf_f_16 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_12.cell_interface` The port interface for: obuf_f_12 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_8.cell_interface` The port interface for: obuf_f_8 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_6.cell_interface` The port interface for: obuf_f_6 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_4.cell_interface` The port interface for: obuf_f_4 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_f_2.cell_interface` The port interface for: obuf_f_2 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_24.cell_interface` The port interface for: obuf_s_24 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_16.cell_interface` The port interface for: obuf_s_16 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_12.cell_interface` The port interface for: obuf_s_12 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_8.cell_interface` The port interface for: obuf_s_8 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_6.cell_interface` The port interface for: obuf_s_6 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_4.cell_interface` The port interface for: obuf_s_4 i : in (1) o : out (1)
`static CellInterface[]`	`obuf_s_2.cell_interface` The port interface for: obuf_s_2 i : in (1) o : out (1)
`static CellInterface[]`	`fds.cell_interface` The port interface for: fds c : implicit (1) d : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ofddrtrse.cell_interface` The port interface for: ofddrtrse c0 : in (1) c1 : in (1) d0 : in (1) d1 : in (1) ce : in (1) r : in (1) s : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ofddrtrse.implicit_interface`
`static CellInterface[]`	`ldp.cell_interface` The port interface for: ldp pre : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ibufds.cell_interface` The port interface for: ibufds i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_ulvds_25.cell_interface` The port interface for: ibufds_ulvds_25 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvpecl_33.cell_interface` The port interface for: ibufds_lvpecl_33 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvpecl_25.cell_interface` The port interface for: ibufds_lvpecl_25 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvdsext_33_dci.cell_interface` The port interface for: ibufds_lvdsext_33_dci i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvdsext_33.cell_interface` The port interface for: ibufds_lvdsext_33 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvdsext_25_dci.cell_interface` The port interface for: ibufds_lvdsext_25_dci i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvdsext_25.cell_interface` The port interface for: ibufds_lvdsext_25 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvds_33_dci.cell_interface` The port interface for: ibufds_lvds_33_dci i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvds_33.cell_interface` The port interface for: ibufds_lvds_33 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvds_25_dci.cell_interface` The port interface for: ibufds_lvds_25_dci i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_lvds_25.cell_interface` The port interface for: ibufds_lvds_25 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_ldt_25.cell_interface` The port interface for: ibufds_ldt_25 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_diff_out.cell_interface` The port interface for: ibufds_diff_out i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ibufds_blvds_25.cell_interface` The port interface for: ibufds_blvds_25 i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`muxf5_l.cell_interface` The port interface for: muxf5_l i0 : in (1) i1 : in (1) s : in (1) lo : out (1)
`static CellInterface[]`	`ram64x2s.cell_interface` The port interface for: ram64x2s d : sin (2) we : sin (1) a : sain (6) o : aout (2) wclk : implicit (1)
`static CellInterface[]`	`fdc.cell_interface` The port interface for: fdc c : implicit (1) d : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`ibufg_agp.cell_interface` The port interface for: ibufg_agp i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_ctt.cell_interface` The port interface for: ibufg_ctt i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl3_ii.cell_interface` The port interface for: ibufg_sstl3_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl3_i.cell_interface` The port interface for: ibufg_sstl3_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl2_ii.cell_interface` The port interface for: ibufg_sstl2_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl2_i.cell_interface` The port interface for: ibufg_sstl2_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_iv.cell_interface` The port interface for: ibufg_hstl_iv i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_iii.cell_interface` The port interface for: ibufg_hstl_iii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_i.cell_interface` The port interface for: ibufg_hstl_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_gtlp.cell_interface` The port interface for: ibufg_gtlp i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_gtl.cell_interface` The port interface for: ibufg_gtl i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci66_3.cell_interface` The port interface for: ibufg_pci66_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci33_5.cell_interface` The port interface for: ibufg_pci33_5 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci33_3.cell_interface` The port interface for: ibufg_pci33_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_lvcmos2.cell_interface` The port interface for: ibufg_lvcmos2 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg.cell_interface` The port interface for: ibufg i : in (1) o : out (1)
`static CellInterface[]`	`norX.cell_interface`
`static CellInterface[]`	`ram64x1d_1.cell_interface` The port interface for: ram64x1d_1 d : sin (1) we : sin (1) a : sain (6) dpra : sain (6) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`ibufgds.cell_interface` The port interface for: ibufgds i : in (1) ib : in (1) o : out (1)
`static CellInterface[]`	`ld.cell_interface` The port interface for: ld g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ofddrcpe.cell_interface` The port interface for: ofddrcpe c0 : in (1) c1 : in (1) d0 : in (1) d1 : in (1) ce : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`muxf8_d.cell_interface` The port interface for: muxf8_d i0 : in (1) i1 : in (1) s : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`muxf6.cell_interface` The port interface for: muxf6 i0 : in (1) i1 : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`ram32x1s_1.cell_interface` The port interface for: ram32x1s_1 d : sin (1) we : sin (1) a : sain (5) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`rocbuf.cell_interface` The port interface for: rocbuf i : in (1) o : out (1)
`static CellInterface[]`	`lut3_d.cell_interface` The port interface for: lut3_d i : in (3) lo : out (1) o : out (1)
`static CellInterface[]`	`iobuf_agp.cell_interface` The port interface for: iobuf_agp i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_ctt.cell_interface` The port interface for: iobuf_ctt i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_sstl3_ii.cell_interface` The port interface for: iobuf_sstl3_ii i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_sstl3_i.cell_interface` The port interface for: iobuf_sstl3_i i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_sstl2_ii.cell_interface` The port interface for: iobuf_sstl2_ii i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_sstl2_i.cell_interface` The port interface for: iobuf_sstl2_i i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_hstl_iv.cell_interface` The port interface for: iobuf_hstl_iv i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_hstl_iii.cell_interface` The port interface for: iobuf_hstl_iii i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_hstl_i.cell_interface` The port interface for: iobuf_hstl_i i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_gtlp.cell_interface` The port interface for: iobuf_gtlp i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_gtl.cell_interface` The port interface for: iobuf_gtl i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_pci66_3.cell_interface` The port interface for: iobuf_pci66_3 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_pci33_5.cell_interface` The port interface for: iobuf_pci33_5 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_pci33_3.cell_interface` The port interface for: iobuf_pci33_3 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_lvcmos2.cell_interface` The port interface for: iobuf_lvcmos2 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_24.cell_interface` The port interface for: iobuf_f_24 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_16.cell_interface` The port interface for: iobuf_f_16 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_12.cell_interface` The port interface for: iobuf_f_12 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_8.cell_interface` The port interface for: iobuf_f_8 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_6.cell_interface` The port interface for: iobuf_f_6 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_4.cell_interface` The port interface for: iobuf_f_4 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_f_2.cell_interface` The port interface for: iobuf_f_2 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_24.cell_interface` The port interface for: iobuf_s_24 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_16.cell_interface` The port interface for: iobuf_s_16 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_12.cell_interface` The port interface for: iobuf_s_12 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_8.cell_interface` The port interface for: iobuf_s_8 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_6.cell_interface` The port interface for: iobuf_s_6 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_4.cell_interface` The port interface for: iobuf_s_4 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf_s_2.cell_interface` The port interface for: iobuf_s_2 i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`iobuf.cell_interface` The port interface for: iobuf i : in (1) t : in (1) o : out (1) io : inout (1)
`static CellInterface[]`	`fddrcpe.cell_interface` The port interface for: fddrcpe c0 : in (1) c1 : in (1) d0 : in (1) d1 : in (1) ce : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`ldc.cell_interface` The port interface for: ldc clr : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`srlc16_1.cell_interface` The port interface for: srlc16_1 CLK : implicit (1) d : sin (1) a : ain (4) q : aout (1) q15 : aout (1)
`static CellInterface[]`	`fdp_g.cell_interface`
`static CellInterface[]`	`icap_virtex2.cell_interface` The port interface for: icap_virtex2 i : in (8) write : in (1) ce : in (1) clk : in (1) o : out (8) busy : out (1)
`static CellInterface[]`	`srl16.cell_interface` The port interface for: srl16 CLK : implicit (1) d : sin (1) a : ain (4) q : aout (1)
`static CellInterface[]`	`ibuf_agp.cell_interface` The port interface for: ibuf_agp i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_ctt.cell_interface` The port interface for: ibuf_ctt i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_sstl3_ii.cell_interface` The port interface for: ibuf_sstl3_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_sstl3_i.cell_interface` The port interface for: ibuf_sstl3_i i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_sstl2_ii.cell_interface` The port interface for: ibuf_sstl2_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_sstl2_i.cell_interface` The port interface for: ibuf_sstl2_i i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_hstl_iv.cell_interface` The port interface for: ibuf_hstl_iv i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_hstl_iii.cell_interface` The port interface for: ibuf_hstl_iii i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_hstl_i.cell_interface` The port interface for: ibuf_hstl_i i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_gtlp.cell_interface` The port interface for: ibuf_gtlp i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_gtl.cell_interface` The port interface for: ibuf_gtl i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_pci66_3.cell_interface` The port interface for: ibuf_pci66_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_pci33_5.cell_interface` The port interface for: ibuf_pci33_5 i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_pci33_3.cell_interface` The port interface for: ibuf_pci33_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibuf_lvcmos2.cell_interface` The port interface for: ibuf_lvcmos2 i : in (1) o : out (1)
`static CellInterface[]`	`nandX.cell_interface`
`static CellInterface[]`	`obuft_agp.cell_interface` The port interface for: obuft_agp i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_ctt.cell_interface` The port interface for: obuft_ctt i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_sstl3_ii.cell_interface` The port interface for: obuft_sstl3_ii i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_sstl3_i.cell_interface` The port interface for: obuft_sstl3_i i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_sstl2_ii.cell_interface` The port interface for: obuft_sstl2_ii i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_sstl2_i.cell_interface` The port interface for: obuft_sstl2_i i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_hstl_iv.cell_interface` The port interface for: obuft_hstl_iv i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_hstl_iii.cell_interface` The port interface for: obuft_hstl_iii i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_hstl_i.cell_interface` The port interface for: obuft_hstl_i i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_gtlp.cell_interface` The port interface for: obuft_gtlp i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_gtl.cell_interface` The port interface for: obuft_gtl i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_pci66_3.cell_interface` The port interface for: obuft_pci66_3 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_pci33_5.cell_interface` The port interface for: obuft_pci33_5 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_pci33_3.cell_interface` The port interface for: obuft_pci33_3 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_lvcmos2.cell_interface` The port interface for: obuft_lvcmos2 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_24.cell_interface` The port interface for: obuft_f_24 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_16.cell_interface` The port interface for: obuft_f_16 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_12.cell_interface` The port interface for: obuft_f_12 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_8.cell_interface` The port interface for: obuft_f_8 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_6.cell_interface` The port interface for: obuft_f_6 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_4.cell_interface` The port interface for: obuft_f_4 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_f_2.cell_interface` The port interface for: obuft_f_2 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_24.cell_interface` The port interface for: obuft_s_24 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_16.cell_interface` The port interface for: obuft_s_16 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_12.cell_interface` The port interface for: obuft_s_12 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_8.cell_interface` The port interface for: obuft_s_8 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_6.cell_interface` The port interface for: obuft_s_6 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_4.cell_interface` The port interface for: obuft_s_4 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`obuft_s_2.cell_interface` The port interface for: obuft_s_2 i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ram128x1s_1.cell_interface` The port interface for: ram128x1s_1 d : sin (1) we : sin (1) a : sain (7) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`muxf8_l.cell_interface` The port interface for: muxf8_l i0 : in (1) i1 : in (1) s : in (1) lo : out (1)
`static CellInterface[]`	`roc.cell_interface` The port interface for: roc o : out (1)
`static CellInterface[]`	`ram64x1s_1.cell_interface` The port interface for: ram64x1s_1 d : sin (1) we : sin (1) a : sain (6) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`xorX.cell_interface`
`static CellInterface[]`	`muxf7.cell_interface` The port interface for: muxf7 i0 : in (1) i1 : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`startup_virtex2.cell_interface` The port interface for: startup_virtex2 gsr : in (1) gts : in (1) clk : clk () gwe : optionin (1) ghigh : optionin (1)
`static CellInterface[]`	`fdcp.cell_interface` The port interface for: fdcp c : implicit (1) d : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`xnorX.cell_interface`
`static CellInterface[]`	`muxf5.cell_interface` The port interface for: muxf5 i0 : in (1) i1 : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`fdcpe_1.cell_interface` The port interface for: fdcpe_1 c : implicit (1) d : in (1) ce : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fdse_g.cell_interface`
`static CellInterface[]`	`fdc_g.cell_interface`
`static CellInterface[]`	`lut3_l.cell_interface` The port interface for: lut3_l i : in (3) lo : out (1)
`static CellInterface[]`	`srl16e_1.cell_interface` The port interface for: srl16e_1 CLK : implicit (1) d : sin (1) ce : sin (1) a : ain (4) q : aout (1)
`static CellInterface[]`	`muxf7_l.cell_interface` The port interface for: muxf7_l i0 : in (1) i1 : in (1) s : in (1) lo : out (1)
`static CellInterface[]`	`lut1.cell_interface` The port interface for: lut1 i0 : in (1) o : out (1)
`static CellInterface[]`	`ram32x1s_ack.cell_interface` The port interface for: ram32x1s_ack d : in (1) we : in (1) ra : in (5) wa : in (5) o : out (1) wclk : implicit (1)
`static CellInterface[]`	`ifddrcpe.cell_interface` The port interface for: ifddrcpe c0 : in (1) c1 : in (1) d : in (1) ce : in (1) clr : in (1) pre : in (1) q0 : out (1) q1 : out (1)
`static CellInterface[]`	`ifddrcpe.implicit_interface`
`static CellInterface[]`	`iobufds.cell_interface` The port interface for: iobufds i : in (1) t : in (1) io : inout (1) iob : inout (1) o : out (1)
`static CellInterface[]`	`bufgce.cell_interface` The port interface for: bufgce i : clk (1) ce : in (1) o : out (1)
`static CellInterface[]`	`srlc16e.cell_interface` The port interface for: srlc16e CLK : implicit (1) d : sin (1) ce : sin (1) a : ain (4) q : aout (1) q15 : aout (1)
`static CellInterface[]`	`ram32x1d.cell_interface` The port interface for: ram32x1d d : sin (1) we : sin (1) a : sain (5) dpra : sain (5) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`andX.cell_interface`
`static CellInterface[]`	`lut2_l.cell_interface` The port interface for: lut2_l i : in (2) lo : out (1)
`static CellInterface[]`	`ldcpe.cell_interface` The port interface for: ldcpe clr : in (1) pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`srlc16.cell_interface` The port interface for: srlc16 CLK : implicit (1) d : sin (1) a : ain (4) q : aout (1) q15 : aout (1)
`static CellInterface[]`	`mult18x18s.cell_interface` The port interface for: mult18x18s c : implicit (1) a : in (18) b : in (18) ce : in (1) r : in (1) p : out (36)
`static CellInterface[]`	`mult18x18s.implicit_interface`
`static CellInterface[]`	`xorcy_d.cell_interface` The port interface for: xorcy_d li : in (1) ci : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`srl16_1.cell_interface` The port interface for: srl16_1 CLK : implicit (1) d : sin (1) a : ain (4) q : aout (1)
`static CellInterface[]`	`fds_g.cell_interface`
`static CellInterface[]`	`mult_and.cell_interface` The port interface for: mult_and i0 : in (1) i1 : in (1) lo : out (1)
`static CellInterface[]`	`muxf8.cell_interface` The port interface for: muxf8 i0 : in (1) i1 : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`muxcy_d.cell_interface` The port interface for: muxcy_d di : in (1) ci : in (1) s : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`ldcp.cell_interface` The port interface for: ldcp clr : in (1) pre : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`bufgs.cell_interface` The port interface for: bufgs i : in (1) o : out (1)
`static CellInterface[]`	`bufgdll.cell_interface` The port interface for: bufgdll i : in (1) o : out (1)
`static CellInterface[]`	`lut2.cell_interface` The port interface for: lut2 i : in (2) o : out (1)
`static CellInterface[]`	`lde.cell_interface` The port interface for: lde ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`bufge.cell_interface` The port interface for: bufge i : in (1) o : out (1)
`static CellInterface[]`	`muxf7_d.cell_interface` The port interface for: muxf7_d i0 : in (1) i1 : in (1) s : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`ld_1.cell_interface` The port interface for: ld_1 g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ofddrrse.cell_interface` The port interface for: ofddrrse c0 : in (1) c1 : in (1) d0 : in (1) d1 : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`xorcy.cell_interface` The port interface for: xorcy li : in (1) ci : in (1) o : out (1)
`static CellInterface[]`	`tocbuf.cell_interface` The port interface for: tocbuf i : in (1) o : out (1)
`static CellInterface[]`	`ldc_1.cell_interface` The port interface for: ldc_1 clr : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`lut2_d.cell_interface` The port interface for: lut2_d i : in (2) lo : out (1) o : out (1)
`static CellInterface[]`	`muxf6_d.cell_interface` The port interface for: muxf6_d i0 : in (1) i1 : in (1) s : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`ldcpe_1.cell_interface` The port interface for: ldcpe_1 clr : in (1) pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ldcp_1.cell_interface` The port interface for: ldcp_1 clr : in (1) pre : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`xorcy_l.cell_interface` The port interface for: xorcy_l li : in (1) ci : in (1) lo : out (1)
`static CellInterface[]`	`obuftds.cell_interface` The port interface for: obuftds i : in (1) t : in (1) o : out (1) ob : out (1)
`static CellInterface[]`	`fddrrse.cell_interface` The port interface for: fddrrse c0 : in (1) c1 : in (1) d0 : in (1) d1 : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ram16x8s.cell_interface` The port interface for: ram16x8s d : sin (8) we : sin (1) a : sain (4) o : aout (8) wclk : implicit (1)
`static CellInterface[]`	`keeper.cell_interface` The port interface for: keeper o : out (1)
`static CellInterface[]`	`muxcy_l.cell_interface` The port interface for: muxcy_l di : in (1) ci : in (1) s : in (1) lo : out (1)
`static CellInterface[]`	`lut1_d.cell_interface` The port interface for: lut1_d i0 : in (1) lo : out (1) o : out (1)
`static CellInterface[]`	`ram128x1s.cell_interface` The port interface for: ram128x1s d : sin (1) we : sin (1) a : sain (7) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`bufcf.cell_interface` The port interface for: bufcf i : in (1) o : out (1)
`static CellInterface[]`	`srl16e.cell_interface` The port interface for: srl16e CLK : implicit (1) d : sin (1) ce : sin (1) a : ain (4) q : aout (1)
`static CellInterface[]`	`lut3.cell_interface` The port interface for: lut3 i : in (3) o : out (1)
`static CellInterface[]`	`bufgmux.cell_interface` The port interface for: bufgmux i0 : in (1) i1 : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`srlc16e_1.cell_interface` The port interface for: srlc16e_1 CLK : implicit (1) d : sin (1) ce : sin (1) a : ain (4) q : aout (1) q15 : aout (1)
`static CellInterface[]`	`ldpe.cell_interface` The port interface for: ldpe pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ram32x1d_1.cell_interface` The port interface for: ram32x1d_1 d : sin (1) we : sin (1) a : sain (5) dpra : sain (5) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`muxf6_l.cell_interface` The port interface for: muxf6_l i0 : in (1) i1 : in (1) s : in (1) lo : out (1)
`static CellInterface[]`	`obufds.cell_interface` The port interface for: obufds i : in (1) o : out (1) ob : out (1)
`static CellInterface[]`	`orX.cell_interface`
`static CellInterface[]`	`ldp_1.cell_interface` The port interface for: ldp_1 pre : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdre_g.cell_interface`
`static CellInterface[]`	`lut1_l.cell_interface` The port interface for: lut1_l i0 : in (1) lo : out (1)
`static CellInterface[]`	`ifddrrse.cell_interface` The port interface for: ifddrrse c0 : in (1) c1 : in (1) d : in (1) ce : in (1) r : in (1) s : in (1) q0 : out (1) q1 : out (1)
`static CellInterface[]`	`ifddrrse.implicit_interface`
`static CellInterface[]`	`muxcy.cell_interface` The port interface for: muxcy di : in (1) ci : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`mult18x18.cell_interface` The port interface for: mult18x18 a : in (18) b : in (18) p : out (36)
`static CellInterface[]`	`lut4.cell_interface` The port interface for: lut4 i : in (4) o : out (1)
`static CellInterface[]`	`bufg_ann.cell_interface` The port interface for: bufg_ann i : in (1) o : out (1)
`static CellInterface[]`	`fdr_g.cell_interface`
`static CellInterface[]`	`bufgmux_1.cell_interface` The port interface for: bufgmux_1 i0 : in (1) i1 : in (1) s : in (1) o : out (1)
`static CellInterface[]`	`bufgls.cell_interface` The port interface for: bufgls i : in (1) o : out (1)
`static CellInterface[]`	`ram16x1d_1.cell_interface` The port interface for: ram16x1d_1 d : sin (1) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`fdcpe.cell_interface` The port interface for: fdcpe c : implicit (1) d : in (1) ce : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`dcm.cell_interface` The port interface for: dcm clkin : in (1) clkfb : in (1) rst : in (1) dssen : in (1) psincdec : in (1) psen : in (1) psclk : in (1) clk0 : out (1) clk90 : out (1) clk180 : out (1) clk270 : out (1) clk2x : out (1) clk2x180 : out (1) clkdv : out (1) clkfx : out (1) clkfx180 : out (1) locked : out (1) status : out (8) psdone : out (1)
`static CellInterface[]`	`lde_1.cell_interface` The port interface for: lde_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`lut4_d.cell_interface` The port interface for: lut4_d i : in (4) lo : out (1) o : out (1)
`static CellInterface[]`	`ram64x1d.cell_interface` The port interface for: ram64x1d d : sin (1) we : sin (1) a : sain (6) dpra : sain (6) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`toc.cell_interface` The port interface for: toc o : out (1)
`static CellInterface[]`	`ldpe_1.cell_interface` The port interface for: ldpe_1 pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`bscan_virtex2.cell_interface` The port interface for: bscan_virtex2 capture : optionout (1) tdo1 : in (1) tdo2 : in (1) update : out (1) shift : out (1) reset : out (1) tdi : out (1) sel1 : out (1) drck1 : out (1) sel2 : out (1) drck2 : out (1)
`static CellInterface[]`	`capture_virtex2.cell_interface` The port interface for: capture_virtex2 cap : in (1) clk : in (1)
`static CellInterface[]`	`fdr.cell_interface` The port interface for: fdr c : implicit (1) d : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`fdcp_1.cell_interface` The port interface for: fdcp_1 c : implicit (1) d : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`ldce.cell_interface` The port interface for: ldce clr : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`muxf5_d.cell_interface` The port interface for: muxf5_d i0 : in (1) i1 : in (1) s : in (1) o : out (1) lo : out (1)
`static CellInterface[]`	`fdp.cell_interface` The port interface for: fdp c : implicit (1) d : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`ldce_1.cell_interface` The port interface for: ldce_1 clr : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ram64x1s.cell_interface` The port interface for: ram64x1s d : sin (1) we : sin (1) a : sain (6) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`lut4_l.cell_interface` The port interface for: lut4_l i : in (4) lo : out (1)
`static CellInterface[]`	`ofddrtcpe.cell_interface` The port interface for: ofddrtcpe c0 : in (1) c1 : in (1) d0 : in (1) d1 : in (1) ce : in (1) clr : in (1) pre : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ofddrtcpe.implicit_interface`
`static CellInterface[]`	`ram16x1s_1.cell_interface` The port interface for: ram16x1s_1 d : sin (1) we : sin (1) a : sain (4) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`Rom128x1View.implicit_interface`
`static CellInterface[]`	`Rom128x1View.cell_interface`
`static CellInterface[]`	`RAMB16_S.implicit_interface`
`static CellInterface[]`	`RAMB16_S.cell_interface`
`static CellInterface[]`	`bufg.cell_interface` The port interface for bufg: i: in (1) o: out (1)
`static CellInterface[]`	`Rom256x1View.implicit_interface`
`static CellInterface[]`	`Rom256x1View.cell_interface`
`static CellInterface[]`	`RAMB16SingleParity.implicit_interface` Deprecated.
`static CellInterface[]`	`RAMB16SingleParity.cell_interface` Deprecated.
`static CellInterface[]`	`SimulationBuffer.cell_interface`
`static CellInterface[]`	`Rom64x1View.implicit_interface`
`static CellInterface[]`	`Rom64x1View.cell_interface`
`static CellInterface[]`	`RAMB16DualParityB.implicit_interface` Deprecated.
`static CellInterface[]`	`RAMB16DualParityB.cell_interface` Deprecated.
`static CellInterface[]`	`BlockRamViewParity.implicit_interface` Deprecated.
`static CellInterface[]`	`BlockRamViewParity.cell_interface` Deprecated.
`static CellInterface[]`	`andX_g.cell_interface`
`static CellInterface[]`	`RAMB16_S_S.implicit_interface`
`static CellInterface[]`	`RAMB16_S_S.cell_interface`
`static CellInterface[]`	`nandX_g.cell_interface`
`static CellInterface[]`	`RAMB16DualNoParity.implicit_interface` Deprecated.
`static CellInterface[]`	`RAMB16DualNoParity.cell_interface` Deprecated.
`static CellInterface[]`	`RAMB16SingleNoParity.implicit_interface` Deprecated.
`static CellInterface[]`	`RAMB16SingleNoParity.cell_interface` Deprecated.
`static CellInterface[]`	`vcc.cell_interface` The port interface for vcc: VCC: out (1)
`static CellInterface[]`	`norX_g.cell_interface`
`static CellInterface[]`	`RAMB16DualParity.implicit_interface` Deprecated.
`static CellInterface[]`	`RAMB16DualParity.cell_interface` Deprecated.
`static CellInterface[]`	`BlockRamView.implicit_interface` Deprecated.
`static CellInterface[]`	`BlockRamView.cell_interface` Deprecated.
`static CellInterface[]`	`orX_g.cell_interface`
`static CellInterface[]`	`gnd.cell_interface` The port interface for gnd: GND: out (1)

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex2.helpers

Fields in byucc.jhdl.Xilinx.Virtex2.helpers declared as CellInterface
`static CellInterface[]`	`Subtractor.cell_interface`
`static CellInterface[]`	`adderSubtractor.cell_interface`
`static CellInterface[]`	`adder.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex2.Modules

Fields in byucc.jhdl.Xilinx.Virtex2.Modules declared as CellInterface
`static CellInterface[]`	`downcnt.cell_interface`
`static CellInterface[]`	`downcnt.implicit_interface`
`static CellInterface[]`	`Mux.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`PriorityEncoder.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`mux81.cell_interface`
`static CellInterface[]`	`Priority.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`srl_array.cell_interface`
`static CellInterface[]`	`upcnt.cell_interface`
`static CellInterface[]`	`upcnt.implicit_interface`
`static CellInterface[]`	`ramrom.cell_interface`
`static CellInterface[]`	`Equals.cell_interface` The ports and parameters of this module.
`static CellInterface[]`	`delay.cell_interface`
`static CellInterface[]`	`mux41.cell_interface`
`static CellInterface[]`	`Shifter.cell_interface`
`static CellInterface[]`	`booth.cell_interface`
`static CellInterface[]`	`MultiplierBlockSigned.cell_interface`
`static CellInterface[]`	`SRLFifo.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`EmbeddedMultiplier.cell_interface`
`static CellInterface[]`	`SRLArray.cell_interface`
`static CellInterface[]`	`MultiplierBlock.cell_interface`
`static CellInterface[]`	`arrayMult.cell_interface` Standard JHDL CellInterface.

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint

Fields in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint declared as CellInterface
`static CellInterface[]`	`FPMult.cell_interface`
`static CellInterface[]`	`FPAddSub.cell_interface`
`static CellInterface[]`	`FPDivide.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack

Fields in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack declared as CellInterface
`static CellInterface[]`	`Round.cell_interface`
`static CellInterface[]`	`ShifterTable.cell_interface`
`static CellInterface[]`	`PriorityEncoder.cell_interface`
`static CellInterface[]`	`BarrelShiftR.cell_interface`
`static CellInterface[]`	`FPExponentMatch.cell_interface`
`static CellInterface[]`	`TestOverflow.cell_interface`
`static CellInterface[]`	`NormalizePE.cell_interface`
`static CellInterface[]`	`FP_ALU.cell_interface`
`static CellInterface[]`	`BarrelShiftL.cell_interface`
`static CellInterface[]`	`Maximum.cell_interface`
`static CellInterface[]`	`Normalize.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack

Fields in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack declared as CellInterface
`static CellInterface[]`	`FPMantissaDivide.cell_interface`
`static CellInterface[]`	`LookupTableBlockRAM.cell_interface` cell's interface to the outside world
`static CellInterface[]`	`DelayS.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack

Fields in byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack declared as CellInterface
`static CellInterface[]`	`MultSubVirtex2.cell_interface`
`static CellInterface[]`	`MultSub.cell_interface`
`static CellInterface[]`	`And_fmap_g.cell_interface`
`static CellInterface[]`	`MultAdd.cell_interface`
`static CellInterface[]`	`EXAMINE_CI_Virtex2.cell_interface`
`static CellInterface[]`	`multCol.cell_interface`
`static CellInterface[]`	`MultAddVirtex2.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.Virtex2.RamPack

Fields in byucc.jhdl.Xilinx.Virtex2.RamPack declared as CellInterface
`static CellInterface[]`	`BlockRamView.implicit_interface`
`static CellInterface[]`	`BlockRamView.cell_interface`
`static CellInterface[]`	`BlockRamViewL.implicit_interface`
`static CellInterface[]`	`BlockRamViewL.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.XC4000

Fields in byucc.jhdl.Xilinx.XC4000 declared as CellInterface
`static CellInterface[]`	`fdce.cell_interface` The port interface for: fdce c : implicit (1) d : in (1) ce : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`ofd.cell_interface` The port interface for: ofd c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ildx_1.cell_interface` The port interface for: ildx_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ipad.cell_interface` Deprecated. The port interface for: ipad ipad : out (1)
`static CellInterface[]`	`fdce_g.cell_interface`
`static CellInterface[]`	`ram32x4s.cell_interface` The port interface for: ram32x4s d : sin (4) we : sin (1) a : sain (5) o : aout (4) wclk : implicit (1)
`static CellInterface[]`	`ram32x8s.cell_interface` The port interface for: ram32x8s d : sin (8) we : sin (1) a : sain (5) o : aout (8) wclk : implicit (1)
`static CellInterface[]`	`fmap.cell_interface` The port interface for: fmap i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`d3_8e.cell_interface` The port interface for: d3_8e a0 : in (1) a1 : in (1) a2 : in (1) e : in (1) d0 : out (1) d1 : out (1) d2 : out (1) d3 : out (1) d4 : out (1) d5 : out (1) d6 : out (1) d7 : out (1)
`static CellInterface[]`	`ofdxi.cell_interface` The port interface for: ofdxi c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdse_1_g.cell_interface`
`static CellInterface[]`	`buf_g.cell_interface`
`static CellInterface[]`	`fdr_1_g.cell_interface`
`static CellInterface[]`	`ram32x1s.cell_interface` The port interface for: ram32x1s d : sin (1) we : sin (1) a : sain (5) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`ldce.cell_interface` The port interface for: ldce clr : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdrs_1_g.cell_interface`
`static CellInterface[]`	`ibuf.cell_interface` The port interface for: ibuf i : in (1) o : out (1)
`static CellInterface[]`	`opad.cell_interface` Deprecated. The port interface for: opad opad : in (1)
`static CellInterface[]`	`ifdxi.cell_interface` The port interface for: ifdxi c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`ram16x4s.cell_interface` The port interface for: ram16x4s d : sin (4) we : sin (1) a : sain (4) o : aout (4) wclk : implicit (1)
`static CellInterface[]`	`obuft.cell_interface` The port interface for: obuft i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ldpe_1.cell_interface` The port interface for: ldpe_1 pre : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdp_1_g.cell_interface`
`static CellInterface[]`	`ofde.cell_interface` The port interface for: ofde c : implicit (1) d : in (1) e : in (1) o : out (1)
`static CellInterface[]`	`fde.cell_interface` The port interface for: fde c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdrse_1_g.cell_interface`
`static CellInterface[]`	`fdrs_1.cell_interface` The port interface for: fdrs_1 c : implicit (1) d : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`pullup_g.cell_interface`
`static CellInterface[]`	`pulldown_g.cell_interface`
`static CellInterface[]`	`fdrse_1.cell_interface` The port interface for: fdrse_1 c : implicit (1) d : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ibuf_g.cell_interface`
`static CellInterface[]`	`bufe.cell_interface` The port interface for: bufe i : in (1) e : in (1) o : out (1)
`static CellInterface[]`	`fdc_1.cell_interface` The port interface for: fdc_1 c : implicit (1) d : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`ldce_1.cell_interface` The port interface for: ldce_1 clr : in (1) ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`obuf.cell_interface` The port interface for: obuf i : in (1) o : out (1)
`static CellInterface[]`	`fdc_1_g.cell_interface`
`static CellInterface[]`	`fdse_1.cell_interface` The port interface for: fdse_1 c : implicit (1) d : in (1) ce : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`iopad.cell_interface` Deprecated. The port interface for: iopad io : inout (1)
`static CellInterface[]`	`buf.cell_interface` The port interface for: buf i : in (1) o : out (1)
`static CellInterface[]`	`upad.cell_interface` The port interface for: upad io : inout (1)
`static CellInterface[]`	`ram16x4d.cell_interface` The port interface for: ram16x4d d : sin (4) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (4) dpo : aout (4) wclk : implicit (1)
`static CellInterface[]`	`ram16x8d.cell_interface` The port interface for: ram16x8d d : sin (8) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (8) dpo : aout (8) wclk : implicit (1)
`static CellInterface[]`	`ofdt.cell_interface` The port interface for: ofdt c : implicit (1) d : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`m2_1.cell_interface` The port interface for: m2_1 d0 : in (1) d1 : in (1) s0 : in (1) o : out (1)
`static CellInterface[]`	`ifd_1.cell_interface` The port interface for: ifd_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`pulldown.cell_interface` The port interface for: pulldown o : out (1)
`static CellInterface[]`	`fdpe.cell_interface` The port interface for: fdpe c : implicit (1) d : in (1) ce : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fds_1.cell_interface` The port interface for: fds_1 c : implicit (1) d : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`inv.cell_interface` The port interface for: inv i : in (1) o : out (1)
`static CellInterface[]`	`buft.cell_interface` The port interface for: buft i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ram16x1d.cell_interface` The port interface for: ram16x1d d : sin (1) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (1) dpo : aout (1) wclk : implicit (1)
`static CellInterface[]`	`ildxi_1.cell_interface` The port interface for: ildxi_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`rom16x1.cell_interface` The port interface for: rom16x1 a : in (4) o : out (1)
`static CellInterface[]`	`ipad_sim.cell_interface` Deprecated. The port interface for: ipad_sim i : in (1) ipad : out (1)
`static CellInterface[]`	`obuft_g.cell_interface`
`static CellInterface[]`	`ram16x8s.cell_interface` The port interface for: ram16x8s d : sin (8) we : sin (1) a : sain (4) o : aout (8) wclk : implicit (1)
`static CellInterface[]`	`fdp_1.cell_interface` The port interface for: fdp_1 c : implicit (1) d : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`ram32x2s.cell_interface` The port interface for: ram32x2s d : sin (2) we : sin (1) a : sain (5) o : aout (2) wclk : implicit (1)
`static CellInterface[]`	`ram16x2d.cell_interface` The port interface for: ram16x2d d : sin (2) we : sin (1) a : sain (4) dpra : sain (4) spo : aout (2) dpo : aout (2) wclk : implicit (1)
`static CellInterface[]`	`ifd.cell_interface` The port interface for: ifd c : implicit (1) d : in (1) q : out (1) gsr : optionin (1)
`static CellInterface[]`	`fds_1_g.cell_interface`
`static CellInterface[]`	`fd_1.cell_interface` The port interface for: fd_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdrse.cell_interface` The port interface for: fdrse c : implicit (1) d : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ram16x1s.cell_interface` The port interface for: ram16x1s d : sin (1) we : sin (1) a : sain (4) o : aout (1) wclk : implicit (1)
`static CellInterface[]`	`fdpe_1.cell_interface` The port interface for: fdpe_1 c : implicit (1) d : in (1) ce : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`obuf_ann.cell_interface` The port interface for: obuf_ann i : in (1) o : out (1)
`static CellInterface[]`	`ifdi_1.cell_interface` The port interface for: ifdi_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ifdi.cell_interface` The port interface for: ifdi c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdce_1.cell_interface` The port interface for: fdce_1 c : implicit (1) d : in (1) ce : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`m2_1_g.cell_interface`
`static CellInterface[]`	`ofdtxi.cell_interface` The port interface for: ofdtxi c : implicit (1) d : in (1) t : in (1) ce : in (1) o : out (1)
`static CellInterface[]`	`ram16x2s.cell_interface` The port interface for: ram16x2s d : sin (2) we : sin (1) a : sain (4) o : aout (2) wclk : implicit (1)
`static CellInterface[]`	`fdre_1.cell_interface` The port interface for: fdre_1 c : implicit (1) d : in (1) ce : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`fd.cell_interface` The port interface for: fd c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`rom32x1.cell_interface` The port interface for: rom32x1 a : in (5) o : out (1)
`static CellInterface[]`	`fdre_1_g.cell_interface`
`static CellInterface[]`	`ifdx.cell_interface` The port interface for: ifdx c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdr_1.cell_interface` The port interface for: fdr_1 c : implicit (1) d : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`inv_g.cell_interface`
`static CellInterface[]`	`pullup.cell_interface` The port interface for: pullup o : out (1)
`static CellInterface[]`	`ofdi.cell_interface` The port interface for: ofdi d : in (1) c : implicit (1) q : out (1)
`static CellInterface[]`	`ibuf_ann.cell_interface` The port interface for: ibuf_ann i : in (1) o : out (1)
`static CellInterface[]`	`ofdtx.cell_interface` The port interface for: ofdtx c : implicit (1) d : in (1) t : in (1) ce : in (1) o : out (1)
`static CellInterface[]`	`fde_1.cell_interface` The port interface for: fde_1 c : implicit (1) ce : in (1) d : in (1) q : out (1)
`static CellInterface[]`	`buft_g.cell_interface`
`static CellInterface[]`	`opad_sim.cell_interface` Deprecated. The port interface for: opad_sim opad : in (1) o : out (1)
`static CellInterface[]`	`fdrs.cell_interface` The port interface for: fdrs c : implicit (1) d : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`fdrs_g.cell_interface`
`static CellInterface[]`	`obuf_g.cell_interface`
`static CellInterface[]`	`ofdx.cell_interface` The port interface for: ofdx c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdpe_g.cell_interface`
`static CellInterface[]`	`fdrse_g.cell_interface`
`static CellInterface[]`	`xnor9.cell_interface`
`static CellInterface[]`	`xnor8.cell_interface`
`static CellInterface[]`	`xnor7.cell_interface`
`static CellInterface[]`	`xnor6.cell_interface`
`static CellInterface[]`	`xnor5.cell_interface`
`static CellInterface[]`	`xnor4_g.cell_interface`
`static CellInterface[]`	`xnor3_g.cell_interface`
`static CellInterface[]`	`xnor2_g.cell_interface`
`static CellInterface[]`	`xnor4.cell_interface` The port interface for: xnor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`xnor3.cell_interface` The port interface for: xnor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`xnor2.cell_interface` The port interface for: xnor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`xor9.cell_interface`
`static CellInterface[]`	`xor8.cell_interface`
`static CellInterface[]`	`xor7.cell_interface`
`static CellInterface[]`	`xor6.cell_interface`
`static CellInterface[]`	`xor5.cell_interface`
`static CellInterface[]`	`xor4_g.cell_interface`
`static CellInterface[]`	`xor3_g.cell_interface`
`static CellInterface[]`	`xor2_g.cell_interface`
`static CellInterface[]`	`xor4.cell_interface` The port interface for: xor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`xor3.cell_interface` The port interface for: xor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`xor2.cell_interface` The port interface for: xor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor9.cell_interface`
`static CellInterface[]`	`nor8.cell_interface`
`static CellInterface[]`	`nor7.cell_interface`
`static CellInterface[]`	`nor6.cell_interface`
`static CellInterface[]`	`nor5.cell_interface`
`static CellInterface[]`	`nor4_g.cell_interface`
`static CellInterface[]`	`nor3_g.cell_interface`
`static CellInterface[]`	`nor2_g.cell_interface`
`static CellInterface[]`	`nor4b4.cell_interface` The port interface for: nor4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b3.cell_interface` The port interface for: nor4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b2.cell_interface` The port interface for: nor4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b1.cell_interface` The port interface for: nor4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4.cell_interface` The port interface for: nor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor3b3.cell_interface` The port interface for: nor3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3b2.cell_interface` The port interface for: nor3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3b1.cell_interface` The port interface for: nor3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3.cell_interface` The port interface for: nor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor2b2.cell_interface` The port interface for: nor2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor2b1.cell_interface` The port interface for: nor2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor2.cell_interface` The port interface for: nor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or9.cell_interface`
`static CellInterface[]`	`or8.cell_interface`
`static CellInterface[]`	`or7.cell_interface`
`static CellInterface[]`	`or6.cell_interface`
`static CellInterface[]`	`or5.cell_interface`
`static CellInterface[]`	`or4_g.cell_interface`
`static CellInterface[]`	`or3_g.cell_interface`
`static CellInterface[]`	`or2_g.cell_interface`
`static CellInterface[]`	`or4b4.cell_interface` The port interface for: or4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b3.cell_interface` The port interface for: or4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b2.cell_interface` The port interface for: or4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b1.cell_interface` The port interface for: or4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4.cell_interface` The port interface for: or4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or3b3.cell_interface` The port interface for: or3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3b2.cell_interface` The port interface for: or3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3b1.cell_interface` The port interface for: or3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3.cell_interface` The port interface for: or3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or2b2.cell_interface` The port interface for: or2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or2b1.cell_interface` The port interface for: or2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or2.cell_interface` The port interface for: or2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand9.cell_interface`
`static CellInterface[]`	`nand8.cell_interface`
`static CellInterface[]`	`nand7.cell_interface`
`static CellInterface[]`	`nand6.cell_interface`
`static CellInterface[]`	`nand5.cell_interface`
`static CellInterface[]`	`nand4_g.cell_interface`
`static CellInterface[]`	`nand3_g.cell_interface`
`static CellInterface[]`	`nand2_g.cell_interface`
`static CellInterface[]`	`nand4b4.cell_interface` The port interface for: nand4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b3.cell_interface` The port interface for: nand4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b2.cell_interface` The port interface for: nand4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b1.cell_interface` The port interface for: nand4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4.cell_interface` The port interface for: nand4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand3b3.cell_interface` The port interface for: nand3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3b2.cell_interface` The port interface for: nand3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3b1.cell_interface` The port interface for: nand3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3.cell_interface` The port interface for: nand3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand2b2.cell_interface` The port interface for: nand2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand2b1.cell_interface` The port interface for: nand2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand2.cell_interface` The port interface for: nand2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and9.cell_interface`
`static CellInterface[]`	`and8.cell_interface`
`static CellInterface[]`	`and7.cell_interface`
`static CellInterface[]`	`and6.cell_interface`
`static CellInterface[]`	`and5.cell_interface`
`static CellInterface[]`	`and4_g.cell_interface`
`static CellInterface[]`	`and3_g.cell_interface`
`static CellInterface[]`	`and2_g.cell_interface`
`static CellInterface[]`	`and4b4.cell_interface` The port interface for: and4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b3.cell_interface` The port interface for: and4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b2.cell_interface` The port interface for: and4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b1.cell_interface` The port interface for: and4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4.cell_interface` The port interface for: and4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and3b3.cell_interface` The port interface for: and3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3b2.cell_interface` The port interface for: and3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3b1.cell_interface` The port interface for: and3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3.cell_interface` The port interface for: and3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and2b2.cell_interface` The port interface for: and2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and2b1.cell_interface` The port interface for: and2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and2.cell_interface` The port interface for: and2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`buffclk.cell_interface` The port interface for: buffclk i : in (1) o : out (1)
`static CellInterface[]`	`tdi.cell_interface` The port interface for: tdi i : out (1) o : in (1)
`static CellInterface[]`	`hmap.cell_interface` The port interface for: hmap i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`oxor2.cell_interface` The port interface for: oxor2 f : in (1) io : in (1) o : out (1)
`static CellInterface[]`	`fdre.cell_interface`
`static CellInterface[]`	`ilffx.cell_interface` The port interface for: ilffx ce : in (1) d : in (1) gf : implicit (1) q : out (1)
`static CellInterface[]`	`ilffx.implicit_interface`
`static CellInterface[]`	`nandX.cell_interface`
`static CellInterface[]`	`oxnor2.cell_interface` The port interface for: oxnor2 f : in (1) io : in (1) o : out (1)
`static CellInterface[]`	`norX.cell_interface`
`static CellInterface[]`	`xnorX.cell_interface`
`static CellInterface[]`	`tck.cell_interface` The port interface for: tck i : out (1)
`static CellInterface[]`	`omux2.cell_interface` The port interface for: omux2 s0 : in (1) d1 : in (1) d0 : in (1) o : out (1)
`static CellInterface[]`	`orX.cell_interface`
`static CellInterface[]`	`bufgs.cell_interface` The port interface for: bufgs i : in (1) o : out (1)
`static CellInterface[]`	`oor2.cell_interface` The port interface for: oor2 f : in (1) io : in (1) o : out (1)
`static CellInterface[]`	`bufge.cell_interface` The port interface for: bufge i : in (1) o : out (1)
`static CellInterface[]`	`bufge_ann.cell_interface` The port interface for: bufge_ann i : in (1) o : out (1)
`static CellInterface[]`	`bufgls_ann.cell_interface` The port interface for: bufgls_ann i : in (1) o : out (1)
`static CellInterface[]`	`oand2.cell_interface` The port interface for: oand2 f : in (1) io : in (1) o : out (1)
`static CellInterface[]`	`fdse.cell_interface`
`static CellInterface[]`	`md0.cell_interface` The port interface for: md0 i : out (1) o : in (1)
`static CellInterface[]`	`fdp.cell_interface`
`static CellInterface[]`	`bufgp_ann.cell_interface` The port interface for: bufgp_ann i : in (1) o : out (1)
`static CellInterface[]`	`startup.cell_interface` The port interface for: startup gsr : in (1) gts : in (1) clk : in (1) q2 : out (1) q3 : out (1) q1q4 : out (1) donein : out (1)
`static CellInterface[]`	`wor2and.cell_interface` The port interface for: wor2and i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`bufgls.cell_interface` The port interface for: bufgls i : in (1) o : out (1)
`static CellInterface[]`	`ilflx_1.cell_interface` The port interface for: ilflx_1 ge : in (1) d : in (1) gf : in (1) g : implicit (1) q : out (1)
`static CellInterface[]`	`md1.cell_interface` The port interface for: md1 o : in (1) i : out (1)
`static CellInterface[]`	`xorX.cell_interface`
`static CellInterface[]`	`fdc.cell_interface`
`static CellInterface[]`	`ilffxi.cell_interface` The port interface for: ilffxi ce : in (1) d : in (1) gf : implicit (1) q : out (1)
`static CellInterface[]`	`ilffxi.implicit_interface`
`static CellInterface[]`	`bscan.cell_interface` The port interface for: bscan tdi : in (1) tms : in (1) tck : in (1) tdo1 : in (1) tdo2 : in (1) tdo : out (1) drck : out (1) idle : out (1) sel1 : out (1) sel2 : out (1)
`static CellInterface[]`	`andX.cell_interface`
`static CellInterface[]`	`md2.cell_interface` The port interface for: md2 i : out (1) o : in (1)
`static CellInterface[]`	`fdr.cell_interface`
`static CellInterface[]`	`onand2.cell_interface` The port interface for: onand2 f : in (1) io : in (1) o : out (1)
`static CellInterface[]`	`bufgs_ann.cell_interface` The port interface for: bufgs_ann i : in (1) o : out (1)
`static CellInterface[]`	`onor2.cell_interface` The port interface for: onor2 f : in (1) io : in (1) o : out (1)
`static CellInterface[]`	`tdo.cell_interface` The port interface for: tdo o : in (1) i : out (1)
`static CellInterface[]`	`tms.cell_interface` The port interface for: tms i : out (1)
`static CellInterface[]`	`ilflxi_1.cell_interface` The port interface for: ilflxi_1 ge : in (1) d : in (1) gf : in (1) g : implicit (1) q : out (1)
`static CellInterface[]`	`fds.cell_interface`
`static CellInterface[]`	`wand.cell_interface` The port interface for: wand i : in (1) o : out (1)
`static CellInterface[]`	`bufg_ann.cell_interface` The port interface for: bufg_ann i : in (1) o : out (1)
`static CellInterface[]`	`ram16x1.cell_interface` The port interface for: ram16x1 d : in (1) we : in (1) a : in (4) o : out (1)
`static CellInterface[]`	`ram32x1.cell_interface` The port interface for: ram32x1 d : in (1) we : in (1) a : in (5) o : out (1)
`static CellInterface[]`	`fmap_g.cell_interface`
`static CellInterface[]`	`gnd.cell_interface` The port interface for gnd: GND: out (1)
`static CellInterface[]`	`cy4.cell_interface` The port interface for cy4: a0: in (1) a1: in (1) b0: in (1) b1: in (1) add: in (1) cin: in (1) c0: in (1) c1: in (1) c2: in (1) c3: in (1) c4: in (1) c5: in (1) c6: in (1) c7: in (1) cout0: out (1) cout: out (1)
`static CellInterface[]`	`bufg.cell_interface` The port interface for bufg: i: in (1) o: out (1)
`static CellInterface[]`	`SimulationBuffer.cell_interface` The port interface for SimulationBuffer: in: in (gw) out: out (gw) parameter: "gw" (INTEGER).
`static CellInterface[]`	`Shifter.cell_interface`
`static CellInterface[]`	`cy4_mode.cell_interface` The portnames for cy4_mode: `{ "c" }`
`static CellInterface[]`	`vcc.cell_interface` The port interface for vcc: VCC: out (1)

Uses of CellInterface in byucc.jhdl.Xilinx.XC4000.carryLogic

Fields in byucc.jhdl.Xilinx.XC4000.carryLogic declared as CellInterface
`static CellInterface[]`	`cy4_DEC_G_F1.cell_interface`
`static CellInterface[]`	`cy4_INC_G_CI.cell_interface`
`static CellInterface[]`	`cy4_SUB_F_CI.cell_interface`
`static CellInterface[]`	`cy4_SUB_FG_CI.cell_interface`
`static CellInterface[]`	`cy4_DEC_G_CI.cell_interface`
`static CellInterface[]`	`cy4_SUB_G_F3_.cell_interface`
`static CellInterface[]`	`cy4_INCDEC_G_F1.cell_interface`
`static CellInterface[]`	`cy4_ADD_FG_CI.cell_interface`
`static CellInterface[]`	`cy4_SUB_G_F1.cell_interface`
`static CellInterface[]`	`cy4_ADD_G_F3_.cell_interface`
`static CellInterface[]`	`cy4_INC_G_1.cell_interface`
`static CellInterface[]`	`cy4_INCDEC_G_CI.cell_interface`
`static CellInterface[]`	`cy4_DEC_FG_CI.cell_interface`
`static CellInterface[]`	`cy4_FORCE_0.cell_interface`
`static CellInterface[]`	`cy4_SUB_G_CI.cell_interface`
`static CellInterface[]`	`cy4_DEC_G_F3_.cell_interface`
`static CellInterface[]`	`cy4_ADD_F_CI.cell_interface`
`static CellInterface[]`	`cy4_ADDSUB_G_F3_.cell_interface`
`static CellInterface[]`	`cy4_INC_FG_1.cell_interface`
`static CellInterface[]`	`cy4_ADD_G_CI.cell_interface`
`static CellInterface[]`	`cy4_INCDEC_G_0.cell_interface`
`static CellInterface[]`	`cy4_ADDSUB_F_CI.cell_interface`
`static CellInterface[]`	`cy4_ADDSUB_FG_CI.cell_interface`
`static CellInterface[]`	`cy4_DEC_G_0.cell_interface`
`static CellInterface[]`	`cy4_FORCE_F3_.cell_interface`
`static CellInterface[]`	`cy4_INC_FG_CI.cell_interface`
`static CellInterface[]`	`cy4_ADD_G_F1.cell_interface`
`static CellInterface[]`	`cy4_INCDEC_FG_CI.cell_interface`
`static CellInterface[]`	`cy4_INCDEC_FG_1.cell_interface`
`static CellInterface[]`	`cy4_INC_G_F3_.cell_interface`
`static CellInterface[]`	`cy4_ADDSUB_G_F1.cell_interface`
`static CellInterface[]`	`cy4_EXAMINE_CI.cell_interface`
`static CellInterface[]`	`cy4_INC_F_CI.cell_interface`
`static CellInterface[]`	`cy4_FORCE_1.cell_interface`
`static CellInterface[]`	`cy4_DEC_F_CI.cell_interface`
`static CellInterface[]`	`cy4_DEC_FG_0.cell_interface`
`static CellInterface[]`	`cy4_ADDSUB_G_CI.cell_interface`
`static CellInterface[]`	`cy4_FORCE_F1.cell_interface`
`static CellInterface[]`	`cy4_SUB_G_1.cell_interface`
`static CellInterface[]`	`cy4_INC_G_F1.cell_interface`
`static CellInterface[]`	`cy4_FORCE_CI.cell_interface`
`static CellInterface[]`	`cy4_INCDEC_F_CI.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.XC4000.Modules

Fields in byucc.jhdl.Xilinx.XC4000.Modules declared as CellInterface
`static CellInterface[]`	`upcnt.cell_interface`
`static CellInterface[]`	`upcnt.implicit_interface`
`static CellInterface[]`	`delay.cell_interface`
`static CellInterface[]`	`booth.cell_interface`
`static CellInterface[]`	`downcnt.cell_interface`
`static CellInterface[]`	`downcnt.implicit_interface`
`static CellInterface[]`	`arrayMult.cell_interface` Standard JHDL CellInterface.
`static CellInterface[]`	`ramrom.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack

Fields in byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack declared as CellInterface
`static CellInterface[]`	`MultSubXC4000.cell_interface`
`static CellInterface[]`	`MultAdd.cell_interface`
`static CellInterface[]`	`multCol.cell_interface`
`static CellInterface[]`	`MultAddXC4000.cell_interface`
`static CellInterface[]`	`MultSub.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.XC4000.techmap.helpers

Fields in byucc.jhdl.Xilinx.XC4000.techmap.helpers declared as CellInterface
`static CellInterface[]`	`Subtractor.cell_interface`
`static CellInterface[]`	`adder.cell_interface`
`static CellInterface[]`	`adderSubtractor.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.XC9000

Fields in byucc.jhdl.Xilinx.XC9000 declared as CellInterface
`static CellInterface[]`	`fdce.cell_interface` The port interface for: fdce c : implicit (1) d : in (1) ce : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`ofd.cell_interface` The port interface for: ofd c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ildx_1.cell_interface` The port interface for: ildx_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ipad.cell_interface` Deprecated. The port interface for: ipad ipad : out (1)
`static CellInterface[]`	`fdce_g.cell_interface`
`static CellInterface[]`	`fmap.cell_interface` The port interface for: fmap i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`d3_8e.cell_interface` The port interface for: d3_8e a0 : in (1) a1 : in (1) a2 : in (1) e : in (1) d0 : out (1) d1 : out (1) d2 : out (1) d3 : out (1) d4 : out (1) d5 : out (1) d6 : out (1) d7 : out (1)
`static CellInterface[]`	`ofdxi.cell_interface` The port interface for: ofdxi c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdse_1_g.cell_interface`
`static CellInterface[]`	`buf_g.cell_interface`
`static CellInterface[]`	`fdr_1_g.cell_interface`
`static CellInterface[]`	`fdrs_1_g.cell_interface`
`static CellInterface[]`	`ibuf.cell_interface` The port interface for: ibuf i : in (1) o : out (1)
`static CellInterface[]`	`opad.cell_interface` Deprecated. The port interface for: opad opad : in (1)
`static CellInterface[]`	`ifdxi.cell_interface` The port interface for: ifdxi c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`obuft.cell_interface` The port interface for: obuft i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`fdp_1_g.cell_interface`
`static CellInterface[]`	`ofde.cell_interface` The port interface for: ofde c : implicit (1) d : in (1) e : in (1) o : out (1)
`static CellInterface[]`	`fde.cell_interface` The port interface for: fde c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdrse_1_g.cell_interface`
`static CellInterface[]`	`fdrs_1.cell_interface` The port interface for: fdrs_1 c : implicit (1) d : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`pullup_g.cell_interface`
`static CellInterface[]`	`pulldown_g.cell_interface`
`static CellInterface[]`	`fdrse_1.cell_interface` The port interface for: fdrse_1 c : implicit (1) d : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`ibuf_g.cell_interface`
`static CellInterface[]`	`bufe.cell_interface` The port interface for: bufe i : in (1) e : in (1) o : out (1)
`static CellInterface[]`	`fdc_1.cell_interface` The port interface for: fdc_1 c : implicit (1) d : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`obuf.cell_interface` The port interface for: obuf i : in (1) o : out (1)
`static CellInterface[]`	`fdc_1_g.cell_interface`
`static CellInterface[]`	`fdse_1.cell_interface` The port interface for: fdse_1 c : implicit (1) d : in (1) ce : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`iopad.cell_interface` Deprecated. The port interface for: iopad io : inout (1)
`static CellInterface[]`	`buf.cell_interface` The port interface for: buf i : in (1) o : out (1)
`static CellInterface[]`	`fdse.cell_interface` The port interface for: fdse c : implicit (1) d : in (1) ce : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`upad.cell_interface` The port interface for: upad io : inout (1)
`static CellInterface[]`	`ofdt.cell_interface` The port interface for: ofdt c : implicit (1) d : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`m2_1.cell_interface` The port interface for: m2_1 d0 : in (1) d1 : in (1) s0 : in (1) o : out (1)
`static CellInterface[]`	`ifd_1.cell_interface` The port interface for: ifd_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`pulldown.cell_interface` The port interface for: pulldown o : out (1)
`static CellInterface[]`	`fdpe.cell_interface` The port interface for: fdpe c : implicit (1) d : in (1) ce : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fds_1.cell_interface` The port interface for: fds_1 c : implicit (1) d : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`inv.cell_interface` The port interface for: inv i : in (1) o : out (1)
`static CellInterface[]`	`buft.cell_interface` The port interface for: buft i : in (1) t : in (1) o : out (1)
`static CellInterface[]`	`ildxi_1.cell_interface` The port interface for: ildxi_1 ge : in (1) g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ipad_sim.cell_interface` Deprecated. The port interface for: ipad_sim i : in (1) ipad : out (1)
`static CellInterface[]`	`obuft_g.cell_interface`
`static CellInterface[]`	`fdp_1.cell_interface` The port interface for: fdp_1 c : implicit (1) d : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`ifd.cell_interface` The port interface for: ifd c : implicit (1) d : in (1) q : out (1) gsr : optionin (1)
`static CellInterface[]`	`fds_1_g.cell_interface`
`static CellInterface[]`	`fd_1.cell_interface` The port interface for: fd_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdrse.cell_interface` The port interface for: fdrse c : implicit (1) d : in (1) ce : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`fdpe_1.cell_interface` The port interface for: fdpe_1 c : implicit (1) d : in (1) ce : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`obuf_ann.cell_interface` The port interface for: obuf_ann i : in (1) o : out (1)
`static CellInterface[]`	`ifdi_1.cell_interface` The port interface for: ifdi_1 c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`ifdi.cell_interface` The port interface for: ifdi c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdce_1.cell_interface` The port interface for: fdce_1 c : implicit (1) d : in (1) ce : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`m2_1_g.cell_interface`
`static CellInterface[]`	`ofdtxi.cell_interface` The port interface for: ofdtxi c : implicit (1) d : in (1) t : in (1) ce : in (1) o : out (1)
`static CellInterface[]`	`fdre_1.cell_interface` The port interface for: fdre_1 c : implicit (1) d : in (1) ce : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`fdre_1_g.cell_interface`
`static CellInterface[]`	`ifdx.cell_interface` The port interface for: ifdx c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fdr_1.cell_interface` The port interface for: fdr_1 c : implicit (1) d : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`inv_g.cell_interface`
`static CellInterface[]`	`pullup.cell_interface` The port interface for: pullup o : out (1)
`static CellInterface[]`	`ofdi.cell_interface` The port interface for: ofdi d : in (1) c : implicit (1) q : out (1)
`static CellInterface[]`	`ibuf_ann.cell_interface` The port interface for: ibuf_ann i : in (1) o : out (1)
`static CellInterface[]`	`ofdtx.cell_interface` The port interface for: ofdtx c : implicit (1) d : in (1) t : in (1) ce : in (1) o : out (1)
`static CellInterface[]`	`fde_1.cell_interface` The port interface for: fde_1 c : implicit (1) ce : in (1) d : in (1) q : out (1)
`static CellInterface[]`	`buft_g.cell_interface`
`static CellInterface[]`	`opad_sim.cell_interface` Deprecated. The port interface for: opad_sim opad : in (1) o : out (1)
`static CellInterface[]`	`fdrs.cell_interface` The port interface for: fdrs c : implicit (1) d : in (1) r : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`fdre.cell_interface` The port interface for: fdre c : implicit (1) d : in (1) ce : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`fdrs_g.cell_interface`
`static CellInterface[]`	`obuf_g.cell_interface`
`static CellInterface[]`	`ofdx.cell_interface` The port interface for: ofdx c : implicit (1) d : in (1) ce : in (1) q : out (1)
`static CellInterface[]`	`fd.cell_interface` The port interface for: fd c : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`fdpe_g.cell_interface`
`static CellInterface[]`	`fdrse_g.cell_interface`
`static CellInterface[]`	`norX.cell_interface`
`static CellInterface[]`	`fdre_g.cell_interface`
`static CellInterface[]`	`ibufg_agp.cell_interface` The port interface for: ibufg_agp i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_ctt.cell_interface` The port interface for: ibufg_ctt i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl3_ii.cell_interface` The port interface for: ibufg_sstl3_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl3_i.cell_interface` The port interface for: ibufg_sstl3_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl2_ii.cell_interface` The port interface for: ibufg_sstl2_ii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_sstl2_i.cell_interface` The port interface for: ibufg_sstl2_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_iv.cell_interface` The port interface for: ibufg_hstl_iv i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_iii.cell_interface` The port interface for: ibufg_hstl_iii i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_hstl_i.cell_interface` The port interface for: ibufg_hstl_i i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_gtlp.cell_interface` The port interface for: ibufg_gtlp i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_gtl.cell_interface` The port interface for: ibufg_gtl i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci66_3.cell_interface` The port interface for: ibufg_pci66_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci33_5.cell_interface` The port interface for: ibufg_pci33_5 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_pci33_3.cell_interface` The port interface for: ibufg_pci33_3 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg_lvcmos2.cell_interface` The port interface for: ibufg_lvcmos2 i : in (1) o : out (1)
`static CellInterface[]`	`ibufg.cell_interface` The port interface for: ibufg i : in (1) o : out (1)
`static CellInterface[]`	`add1.cell_interface` The port interface for: add1 a : in (1) b : in (1) ci : in (1) s : out (1) co : out (1)
`static CellInterface[]`	`orX.cell_interface`
`static CellInterface[]`	`fdp_g.cell_interface`
`static CellInterface[]`	`xorX.cell_interface`
`static CellInterface[]`	`fdcp.cell_interface` The port interface for: fdcp c : implicit (1) d : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`nandX.cell_interface`
`static CellInterface[]`	`xnorX.cell_interface`
`static CellInterface[]`	`fdc_g.cell_interface`
`static CellInterface[]`	`fdse_g.cell_interface`
`static CellInterface[]`	`ftcp.cell_interface` The port interface for: ftcp c : implicit (1) t : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fdp.cell_interface` The port interface for: fdp c : implicit (1) d : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`fds_g.cell_interface`
`static CellInterface[]`	`fdr_g.cell_interface`
`static CellInterface[]`	`fdc.cell_interface` The port interface for: fdc c : implicit (1) d : in (1) clr : in (1) q : out (1)
`static CellInterface[]`	`fdcp_g.cell_interface`
`static CellInterface[]`	`andX.cell_interface`
`static CellInterface[]`	`fdr.cell_interface` The port interface for: fdr c : implicit (1) d : in (1) r : in (1) q : out (1)
`static CellInterface[]`	`ld.cell_interface` The port interface for: ld g : implicit (1) d : in (1) q : out (1)
`static CellInterface[]`	`adsu1.cell_interface` The port interface for: adsu1 a : in (1) b : in (1) ci : in (1) add : in (1) s : out (1) co : out (1)
`static CellInterface[]`	`fds.cell_interface` The port interface for: fds c : implicit (1) d : in (1) s : in (1) q : out (1)
`static CellInterface[]`	`fdcpe.cell_interface` The port interface for: fdcpe c : implicit (1) d : in (1) ce : in (1) clr : in (1) pre : in (1) q : out (1)
`static CellInterface[]`	`bufgsr.cell_interface` The port interface for: bufgsr i : in (1) o : out (1)
`static CellInterface[]`	`xnor9_g.cell_interface`
`static CellInterface[]`	`xnor8_g.cell_interface`
`static CellInterface[]`	`xnor7_g.cell_interface`
`static CellInterface[]`	`xnor6_g.cell_interface`
`static CellInterface[]`	`xnor5_g.cell_interface`
`static CellInterface[]`	`xnor4_g.cell_interface`
`static CellInterface[]`	`xnor3_g.cell_interface`
`static CellInterface[]`	`xnor2_g.cell_interface`
`static CellInterface[]`	`xnor9.cell_interface` The port interface for: xnor9 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) i8 : in (1) o : out (1)
`static CellInterface[]`	`xnor8.cell_interface` The port interface for: xnor8 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) o : out (1)
`static CellInterface[]`	`xnor7.cell_interface` The port interface for: xnor7 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) o : out (1)
`static CellInterface[]`	`xnor6.cell_interface` The port interface for: xnor6 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) o : out (1)
`static CellInterface[]`	`xnor5.cell_interface` The port interface for: xnor5 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`xnor4.cell_interface` The port interface for: xnor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`xnor3.cell_interface` The port interface for: xnor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`xnor2.cell_interface` The port interface for: xnor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`xor9_g.cell_interface`
`static CellInterface[]`	`xor8_g.cell_interface`
`static CellInterface[]`	`xor7_g.cell_interface`
`static CellInterface[]`	`xor6_g.cell_interface`
`static CellInterface[]`	`xor5_g.cell_interface`
`static CellInterface[]`	`xor4_g.cell_interface`
`static CellInterface[]`	`xor3_g.cell_interface`
`static CellInterface[]`	`xor2_g.cell_interface`
`static CellInterface[]`	`xor9.cell_interface` The port interface for: xor9 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) i8 : in (1) o : out (1)
`static CellInterface[]`	`xor8.cell_interface` The port interface for: xor8 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) o : out (1)
`static CellInterface[]`	`xor7.cell_interface` The port interface for: xor7 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) o : out (1)
`static CellInterface[]`	`xor6.cell_interface` The port interface for: xor6 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) o : out (1)
`static CellInterface[]`	`xor5.cell_interface` The port interface for: xor5 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`xor4.cell_interface` The port interface for: xor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`xor3.cell_interface` The port interface for: xor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`xor2.cell_interface` The port interface for: xor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor9_g.cell_interface`
`static CellInterface[]`	`nor8_g.cell_interface`
`static CellInterface[]`	`nor7_g.cell_interface`
`static CellInterface[]`	`nor6_g.cell_interface`
`static CellInterface[]`	`nor5_g.cell_interface`
`static CellInterface[]`	`nor4_g.cell_interface`
`static CellInterface[]`	`nor3_g.cell_interface`
`static CellInterface[]`	`nor2_g.cell_interface`
`static CellInterface[]`	`nor9.cell_interface` The port interface for: nor9 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) i8 : in (1) o : out (1)
`static CellInterface[]`	`nor8.cell_interface` The port interface for: nor8 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) o : out (1)
`static CellInterface[]`	`nor7.cell_interface` The port interface for: nor7 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) o : out (1)
`static CellInterface[]`	`nor6.cell_interface` The port interface for: nor6 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) o : out (1)
`static CellInterface[]`	`nor5.cell_interface` The port interface for: nor5 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`nor4b4.cell_interface` The port interface for: nor4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b3.cell_interface` The port interface for: nor4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b2.cell_interface` The port interface for: nor4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4b1.cell_interface` The port interface for: nor4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor4.cell_interface` The port interface for: nor4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nor3b3.cell_interface` The port interface for: nor3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3b2.cell_interface` The port interface for: nor3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3b1.cell_interface` The port interface for: nor3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor3.cell_interface` The port interface for: nor3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nor2b2.cell_interface` The port interface for: nor2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor2b1.cell_interface` The port interface for: nor2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nor2.cell_interface` The port interface for: nor2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or9_g.cell_interface`
`static CellInterface[]`	`or8_g.cell_interface`
`static CellInterface[]`	`or7_g.cell_interface`
`static CellInterface[]`	`or6_g.cell_interface`
`static CellInterface[]`	`or5_g.cell_interface`
`static CellInterface[]`	`or4_g.cell_interface`
`static CellInterface[]`	`or3_g.cell_interface`
`static CellInterface[]`	`or2_g.cell_interface`
`static CellInterface[]`	`or9.cell_interface` The port interface for: or9 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) i8 : in (1) o : out (1)
`static CellInterface[]`	`or8.cell_interface` The port interface for: or8 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) o : out (1)
`static CellInterface[]`	`or7.cell_interface` The port interface for: or7 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) o : out (1)
`static CellInterface[]`	`or6.cell_interface` The port interface for: or6 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) o : out (1)
`static CellInterface[]`	`or5.cell_interface` The port interface for: or5 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`or4b4.cell_interface` The port interface for: or4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b3.cell_interface` The port interface for: or4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b2.cell_interface` The port interface for: or4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4b1.cell_interface` The port interface for: or4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or4.cell_interface` The port interface for: or4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`or3b3.cell_interface` The port interface for: or3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3b2.cell_interface` The port interface for: or3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3b1.cell_interface` The port interface for: or3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or3.cell_interface` The port interface for: or3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`or2b2.cell_interface` The port interface for: or2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or2b1.cell_interface` The port interface for: or2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`or2.cell_interface` The port interface for: or2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand9_g.cell_interface`
`static CellInterface[]`	`nand8_g.cell_interface`
`static CellInterface[]`	`nand7_g.cell_interface`
`static CellInterface[]`	`nand6_g.cell_interface`
`static CellInterface[]`	`nand5_g.cell_interface`
`static CellInterface[]`	`nand4_g.cell_interface`
`static CellInterface[]`	`nand3_g.cell_interface`
`static CellInterface[]`	`nand2_g.cell_interface`
`static CellInterface[]`	`nand9.cell_interface` The port interface for: nand9 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) i8 : in (1) o : out (1)
`static CellInterface[]`	`nand8.cell_interface` The port interface for: nand8 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) o : out (1)
`static CellInterface[]`	`nand7.cell_interface` The port interface for: nand7 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) o : out (1)
`static CellInterface[]`	`nand6.cell_interface` The port interface for: nand6 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) o : out (1)
`static CellInterface[]`	`nand5.cell_interface` The port interface for: nand5 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`nand4b4.cell_interface` The port interface for: nand4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b3.cell_interface` The port interface for: nand4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b2.cell_interface` The port interface for: nand4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4b1.cell_interface` The port interface for: nand4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand4.cell_interface` The port interface for: nand4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`nand3b3.cell_interface` The port interface for: nand3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3b2.cell_interface` The port interface for: nand3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3b1.cell_interface` The port interface for: nand3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand3.cell_interface` The port interface for: nand3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`nand2b2.cell_interface` The port interface for: nand2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand2b1.cell_interface` The port interface for: nand2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`nand2.cell_interface` The port interface for: nand2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and9_g.cell_interface`
`static CellInterface[]`	`and8_g.cell_interface`
`static CellInterface[]`	`and7_g.cell_interface`
`static CellInterface[]`	`and6_g.cell_interface`
`static CellInterface[]`	`and5_g.cell_interface`
`static CellInterface[]`	`and4_g.cell_interface`
`static CellInterface[]`	`and3_g.cell_interface`
`static CellInterface[]`	`and2_g.cell_interface`
`static CellInterface[]`	`and9.cell_interface` The port interface for: and9 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) i8 : in (1) o : out (1)
`static CellInterface[]`	`and8.cell_interface` The port interface for: and8 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) i7 : in (1) o : out (1)
`static CellInterface[]`	`and7.cell_interface` The port interface for: and7 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) i6 : in (1) o : out (1)
`static CellInterface[]`	`and6.cell_interface` The port interface for: and6 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) i5 : in (1) o : out (1)
`static CellInterface[]`	`and5.cell_interface` The port interface for: and5 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) i4 : in (1) o : out (1)
`static CellInterface[]`	`and4b4.cell_interface` The port interface for: and4b4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b3.cell_interface` The port interface for: and4b3 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b2.cell_interface` The port interface for: and4b2 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4b1.cell_interface` The port interface for: and4b1 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and4.cell_interface` The port interface for: and4 i0 : in (1) i1 : in (1) i2 : in (1) i3 : in (1) o : out (1)
`static CellInterface[]`	`and3b3.cell_interface` The port interface for: and3b3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3b2.cell_interface` The port interface for: and3b2 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3b1.cell_interface` The port interface for: and3b1 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and3.cell_interface` The port interface for: and3 i0 : in (1) i1 : in (1) i2 : in (1) o : out (1)
`static CellInterface[]`	`and2b2.cell_interface` The port interface for: and2b2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and2b1.cell_interface` The port interface for: and2b1 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`and2.cell_interface` The port interface for: and2 i0 : in (1) i1 : in (1) o : out (1)
`static CellInterface[]`	`bufg.cell_interface` The port interface for bufg: i: in (1) o: out (1)
`static CellInterface[]`	`vcc.cell_interface` The port interface for vcc: VCC: out (1)
`static CellInterface[]`	`andX_g.cell_interface`
`static CellInterface[]`	`orX_g.cell_interface`
`static CellInterface[]`	`nandX_g.cell_interface`
`static CellInterface[]`	`norX_g.cell_interface`
`static CellInterface[]`	`gnd.cell_interface` The port interface for gnd: GND: out (1)
`static CellInterface[]`	`SimulationBuffer.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.XC9000.helpers

Fields in byucc.jhdl.Xilinx.XC9000.helpers declared as CellInterface
`static CellInterface[]`	`adder.cell_interface`
`static CellInterface[]`	`adderSubtractor.cell_interface`
`static CellInterface[]`	`Subtractor.cell_interface`

Uses of CellInterface in byucc.jhdl.Xilinx.XC9000.Modules

Fields in byucc.jhdl.Xilinx.XC9000.Modules declared as CellInterface
`static CellInterface[]`	`mux81.cell_interface`
`static CellInterface[]`	`mux41.cell_interface`
`static CellInterface[]`	`Shifter.cell_interface`

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Uses of Interfacebyucc.jhdl.base.CellInterface

Uses of Interface
byucc.jhdl.base.CellInterface