byucc.jhdl.contrib.modgen
Class IntDivide

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.contrib.modgen.IntDivide

All Implemented Interfaces:

BooleanFlags, Clockable, byucc.jhdl.base.Propagateable, TreeListable, UserDefinedSchematic

public class IntDivide

extends Logic

implements UserDefinedSchematic

Variable width integer divider with the option of signed or unsigned multiply and generic pipeline depth.

Copyright (c) 1999-2000 Brigham Young University. All rights reserved. Reproduction in whole or in part in any form or medium without express permission of Brigham Young University is prohibited.

This is a variable width integer divider based on a non-restoring division algorithm that can be pipelined. The divider can produce both a quotient and remainder or a rounded quotient as well as perform both unsigned and signed division.

As seen in the diagram, the divider will calculate the integer quotient and remainder by dividing the dividend value by the divisor value. The clock enable input allows one to stall the pipeline. The divideByZero output will detect invalid results caused by the divisor value being zero.

The dividend, divisor, quotient and remainder wires are all generic widths with restrictions. Generic width implies that the module will query the width of these input wires and construct itself accordingly. In the case of the IntDivide module genterator although the dividend, divisor, quotient and remainder widths are generic, there are certain restrictions with regard to the relationship of their widths. These restrictions on the relation of their widths are indicated in the table below for both the non-rounded quotient and rounded quotient configurations of the divider. To obtain all possible bits of a quotient its width must be the same as the dividend's width (if the quotient width is less than the dividend's the most significant bits are truncated off with no overflow check being done). In the table below, when a wire is indicated as not required this means that a null can be passed into wires's parameter if the functionality of this signal is not desired (note that if a null is passed in for a wire, optimization is performed, see the Logic Optimization section below for more explanation).

Non-rounding IntDivider Wire Width Restrictions

Wire	Width	Width Restrictions	Required Wire?
dividend	dvdWidth	2<= dvdWidth*	Required
divisor	dvrWidth	2<= dvrWidth<= dvdWidth	Required
clk_en	clk_enWidth	clk_enWidth=1	Not Required**
quotient	qWidth	2<= qWidth<= dvdWidth	Not Required***
remainder	remWidth	remWidth= dvrWidth	Not Required***
divideByZero	divBy0Width	divBy0Width=1	Not Required

Rounded IntDivider Wire Width Restrictions

Wire	Width	Width Restrictions	Required Wire?
dividend	dvdWidth	2<= dvdWidth*	Required
divisor	dvrWidth	2<= dvrWidth<= dvdWidth	Required
clk_en	clk_enWidth	clk_enWidth=1	Not Required**
quotient	qWidth	2<= qWidth<= dvdWidth	Required
remainder	N/A	N/A	Must be null
divideByZero	divBy0Width	divBy0Width=1	Not Required

* Although these widths should be valid structurally for widths greater than 64 bits, the maximum bit width that the behavioral model is valid for is 63 bits.

** Note that if your divider is purely combinational (the pipedepth parameter into your constructor is zero), the clk_en wire must be null.

*** For the non-rounding quotient case, although the quotient and remainder wire can be individually null they cannot both be null at the same time (in other words, you must have a useful output).

Implementation

All Technologies

This divider is based on a non-restoring divide algorithm. The advantage of this algorithm is that it can be pipelined fairly easily in a manner similar to the way one would pipeline an array multiplier. The core of the divider logic consists of addsub units. The number of addsub units and the widths of the addsub units in the core divider logic is determined by the width of the dividend input wire. If n is the width of the dividend input wire, there will be n (n+1)-bit addsub units in the core divider logic.

Correction and Rounding Hardware

After the divider logic core there is a need for remainder correcting hardware in both unsigned and signed cases and quotient correcting hardware for the signed case. For non-rounding dividers, this correcting hardware is only one stage for unsigned dividers but is 3 stages for signed dividers. For rounding dividers the correcting and rounding hardware require two stages for both unsigned and signed dividers. The total number of logic stages for a particular divider configuration can be queried by using the static numOfStages method or using the method getNumOfStages once a divider is instantiated.

Pipelining and Latency

The pipelining of this module is implemented based on the assumption that every pipeline stage should be balanced. Thus the pipedepth parameter of this divider does NOT represent the latency of the divider but the frequency of a pipeline register.
pipedepth=0 means fully-combinational divider
pipedepth=1 means fully-pipelined divider (one pipeline register per logic stage).
pipedepth=2 means place a pipeline register every other stage
pipedepth=3 means place a pipeline register every third stage
etc...
If there is a shorter stage it will be the first stage in the divider in order to allow more time for inputs to arrive. Also note that no input registering is done and therefore must be done by the user if desired (i.e. the inputs go directly into the first addsub unit and no matter the configuration will not go through a register beforehand). The latency corresponding to a particular divider configuration can be queried using the static latency method or by using the getLatency method once a divider has been constructed.

Rounding Convention

A rounding divider rounds the fraction of the remainder over the divisor in a conventional manner (i.e. if |fraction|<1/2 it will round down and if |fraction|>1/2 it will round up). The border case is when the magnitude of the fraction is exactly equal to 1/2. The table below describes what occurs in this case.

Unsigned/Signed Divider	Sign of Dividend	Round Up or Down (Magnitude)	Examples
Unsigned	N/A	Round Up	3/6= 1
Signed	Positive	Round Up	3/6= 1, 3/-6= -1
Signed	Negative	Round Down	-3/6= 0, -3/-6= 0

Logic Optimization

For the divisor input, using widths less than the width of the dividend will result in less logic. For example for a fully-pipelined divider, a smaller divisor width will require less pipelining registers and therefore require less logic resources.

If any of the wire parameters that can be null are null, logic will not be built for any wires or structure corresponding to these inputs or outputs. Therefore if the functionality of a signal is not desired it is always best to pass a null in for that wire's parameter. For example, passing a null in for the remainder output wire will tell the module not to construct the remainder correcting hardware. On the other hand, leaving the output hanging by using the Logic method call nc(divisorWidth) will cause the remainder logic to be built although it is left unconnected (because nc() returns a wire and the module doesn't know the difference between that wire and a connected output wire). Likewise if one passes a null in for the clk_en input wire no clk_en net will be not be connected. In constrast, tying the clk_en input high with the Logic class method call vcc() will cause the clock enable net to be hooked up to every flip-flop although it's obvious that one isn't going to use the clk_en signal in this case.

Overflow

The user should take note of the following two cases when overflow can occur using this divider:

1. When the width of the quotient wire is less that the width of the width of dividend wire. In this case no overflow detection hardware is made and the answer may be incorrect (if you are concerned about this you should make the quotient wire width the same as the width of the dividend wire and do your own overflow checking).
2. When the highest magnitude negative number (MSB is 1 and all other bits are 0) is divided by -1 (all ones). In this case the result will be the highest magnitude negative number since the correct answer, which should have a positive sign but the same magnitude, cannot be expressed in twos-complement form with the given number of bits.

Divide By Zero

The divide by zero signal will only be high when the outputs of the divider correspond to a calculation when the divisor was zero. In this case the quotient and the remainder output values are INVALID and are not guaranteed to be consistant from one divider configuration to another (also note that the JHDL behavioral model may not be 100% consistant with the structural model when a divisor is 0).

Xilinx XC4000

Area

This design is not placed so no area information has been gathered.

Xilinx Virtex

Area

This design is not placed so no area information has been gathered.

Other Technologies

If the JHDL Techmapper is not Xilinx nor Virtex a functionally correct divider will be instantiated (using all Logic class API calls).

Copyright (c) 1999-2000 Brigham Young University. All rights reserved. Reproduction in whole or in part in any form or medium without express permission of Brigham Young University is prohibited.

Version:

$Revision: 1.3 $

Author:

Russell Fredrickson

Field Summary

static CellInterface[]	cell_interface Standard JHDL CellInterface.
protected static boolean	disableBehavioralModel
static int	DIVIDE_BY_ZERO_INDEX For indexing divide_by_zero value in the 3 element array compute returns
static int	QUOTIENT_INDEX For indexing the quotient in the 3 element array compute returns
static int	REMAINDER_INDEX For indexing the remainder in the 3 element array compute returns

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, implicit_interface, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

IntDivide(Node parent, Wire dividend, Wire divisor, Wire clk_en, Wire quotient, Wire remainder, Wire divideByZero, boolean signed, boolean roundQuotient, int pipedepth)
Integer divider constructor without a user-defined instance name.

IntDivide(Node parent, Wire dividend, Wire divisor, Wire clk_en, Wire quotient, Wire remainder, Wire divideByZero, boolean signed, boolean roundQuotient, int pipedepth, java.lang.String instanceName)
Integer divider constructor whose last parameter is a user-defined instance name.

Method Summary

boolean	cellInterfaceDeterminesUniqueNetlistStructure() Method to indicate that the netlister can assume that the wires and the bound parameters in the cell interface uniquely determine a cell structure.
void	clock() Clock method is used for behavioral pipelined similuation.
static void	compute(BV dividend, BV divisor, BV quotient, BV remainder, BV divideByZero, boolean signed, boolean roundQuotient) compute method using BVs
static long[]	compute(long dividend, int dvdWidth, long divisor, int dvrWidth, int quotientWidth, boolean remainderFlag, boolean divideByZeroFlag, boolean signed, boolean roundQuotient) Compute method that calculates a mathematically accurate calculation of all the outputs of the divider and returns them as a long array of 3 elements.
static void	computeQuotient(BV dividend, BV divisor, BV quotient, boolean signed, boolean roundQuotient) computeQuotient using BVs
static long	computeQuotient(long dividend, int dvdWidth, long divisor, int dvrWidth, int quotientWidth, boolean signed, boolean roundQuotient) ComputeQuotient method that calculates a mathematically accurate calculation of the quotient the divider would produce out for the given parameters.
static void	computeRemainder(BV dividend, BV divisor, BV remainder, boolean signed) ComputeRemainder using BVs
static long	computeRemainder(long dividend, int dvdWidth, long divisor, int dvrWidth, boolean signed) ComputeRemainder method provides the correct remainder value that the structural model would generate given the input parameters.
protected boolean	defaultSimulationModelIsBehavioral() The default simulation model is behavioral.
int	getLatency() Method to get the latency of a divider that is already constructed.
int	getNumOfStages() Method to get the number of logic stages of a divider that is already constructed.
void	initUserDefinedNode(UserDefinedNode udn) init method needed for UserDefinedSchematic interface.
static int	latency(int dividendWidth, int quotientWidth, boolean remainderFlag, boolean signed, boolean roundQuotient, int pipedepth) The latency method gives the latency in clock cycles of the module with the given input parameters.
static int	numOfStages(int dividendWidth, int quotientWidth, boolean remainderFlag, boolean signed, boolean roundQuotient) Method that calculates the number of pipelinable logic stages (most stages consist of addsub units).
void	paint(UserDefinedNode udn) paint method for UserDefinedSchematic interface.
void	propagate() Propagate method for combinational behavioral simulation (no registers).
void	reset() Reset method puts zeros on quotient, remainder and divideByZero outputs and clears behavioral delay arrays.

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, connectImplicitPorts, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

cell_interface

public static CellInterface[] cell_interface

Standard JHDL CellInterface.

disableBehavioralModel

protected static boolean disableBehavioralModel

QUOTIENT_INDEX

public static final int QUOTIENT_INDEX

For indexing the quotient in the 3 element array compute returns

See Also:

Constant Field Values

REMAINDER_INDEX

public static final int REMAINDER_INDEX

For indexing the remainder in the 3 element array compute returns

See Also:

Constant Field Values

DIVIDE_BY_ZERO_INDEX

public static final int DIVIDE_BY_ZERO_INDEX

For indexing divide_by_zero value in the 3 element array compute returns

See Also:

Constant Field Values

Constructor Detail

IntDivide

public IntDivide(Node parent,
                 Wire dividend,
                 Wire divisor,
                 Wire clk_en,
                 Wire quotient,
                 Wire remainder,
                 Wire divideByZero,
                 boolean signed,
                 boolean roundQuotient,
                 int pipedepth)

Integer divider constructor without a user-defined instance name.

Throws:

IntDivideException - Thrown when any of the parameters are invalid (as described above in the parameter description).

IntDivide

public IntDivide(Node parent,
                 Wire dividend,
                 Wire divisor,
                 Wire clk_en,
                 Wire quotient,
                 Wire remainder,
                 Wire divideByZero,
                 boolean signed,
                 boolean roundQuotient,
                 int pipedepth,
                 java.lang.String instanceName)

Integer divider constructor whose last parameter is a user-defined instance name.

Throws:

IntDivideException - Thrown when any of the parameters are invalid (as described above in the parameter description).

Method Detail

cellInterfaceDeterminesUniqueNetlistStructure

public boolean cellInterfaceDeterminesUniqueNetlistStructure()

Method to indicate that the netlister can assume that the wires and the bound parameters in the cell interface uniquely determine a cell structure.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

true

initUserDefinedNode

public void initUserDefinedNode(UserDefinedNode udn)

init method needed for UserDefinedSchematic interface.

Specified by:

initUserDefinedNode in interface UserDefinedSchematic

paint

public void paint(UserDefinedNode udn)

paint method for UserDefinedSchematic interface.

Specified by:

paint in interface UserDefinedSchematic

latency

public static int latency(int dividendWidth,
                          int quotientWidth,
                          boolean remainderFlag,
                          boolean signed,
                          boolean roundQuotient,
                          int pipedepth)

The latency method gives the latency in clock cycles of the module with the given input parameters. When a IntDivider module is constructed the class variable latency is set using this method.

Returns:

Integer representing the latency of the divider. 0 means that there is no delay (fully-combinational), 1 means that the outputs will appear one cycle after corresponding inputs, etc.

getLatency

public int getLatency()

Method to get the latency of a divider that is already constructed.

Returns:

latency (in clock cycles) of the divider (latency of 0 denotes fully-combinational)

numOfStages

public static int numOfStages(int dividendWidth,
                              int quotientWidth,
                              boolean remainderFlag,
                              boolean signed,
                              boolean roundQuotient)

Method that calculates the number of pipelinable logic stages (most stages consist of addsub units).

Returns:

Integer value that represents the number of pipelinable logic stages.

getNumOfStages

public int getNumOfStages()

Method to get the number of logic stages of a divider that is already constructed.

Returns:

number of logic stages in the divider

defaultSimulationModelIsBehavioral

protected boolean defaultSimulationModelIsBehavioral()

The default simulation model is behavioral.

Overrides:

defaultSimulationModelIsBehavioral in class Structural

Returns:

true;

reset

public void reset()

Reset method puts zeros on quotient, remainder and divideByZero outputs and clears behavioral delay arrays.

Specified by:

reset in interface Clockable

Overrides:

reset in class Structural

clock

public void clock()

Clock method is used for behavioral pipelined similuation. This uses a delay array and a global pointer count to simulate pipelining.

Specified by:

clock in interface Clockable

Overrides:

clock in class Structural

propagate

public void propagate()

Propagate method for combinational behavioral simulation (no registers).

Specified by:

propagate in interface byucc.jhdl.base.Propagateable

Overrides:

propagate in class Structural

compute

public static long[] compute(long dividend,
                             int dvdWidth,
                             long divisor,
                             int dvrWidth,
                             int quotientWidth,
                             boolean remainderFlag,
                             boolean divideByZeroFlag,
                             boolean signed,
                             boolean roundQuotient)

Compute method that calculates a mathematically accurate calculation of all the outputs of the divider and returns them as a long array of 3 elements. The first element of the array is the quotient, the second is the remainder and the third is the divideByZero signal value.

Returns:

a long array of 3 elements with the first element being the quotient, the second element being the remainder and the third element being the divideByZero signal. If any of these outputs are not used then that particular value is always 0.

compute

public static void compute(BV dividend,
                           BV divisor,
                           BV quotient,
                           BV remainder,
                           BV divideByZero,
                           boolean signed,
                           boolean roundQuotient)

compute method using BVs

computeQuotient

public static long computeQuotient(long dividend,
                                   int dvdWidth,
                                   long divisor,
                                   int dvrWidth,
                                   int quotientWidth,
                                   boolean signed,
                                   boolean roundQuotient)

ComputeQuotient method that calculates a mathematically accurate calculation of the quotient the divider would produce out for the given parameters.

Returns:

Long integer quotient value of the division of the dividend and divisor input values.

computeQuotient

public static void computeQuotient(BV dividend,
                                   BV divisor,
                                   BV quotient,
                                   boolean signed,
                                   boolean roundQuotient)

computeQuotient using BVs

computeRemainder

public static long computeRemainder(long dividend,
                                    int dvdWidth,
                                    long divisor,
                                    int dvrWidth,
                                    boolean signed)

ComputeRemainder method provides the correct remainder value that the structural model would generate given the input parameters.

Returns:

Long integer value of the remainder for the divide of the dividend and divisor input values.

computeRemainder

public static void computeRemainder(BV dividend,
                                    BV divisor,
                                    BV remainder,
                                    boolean signed)

ComputeRemainder using BVs