byucc.jhdl.base
Interface BooleanFlags

All Known Implementing Classes:

Net, Node, byucc.jhdl.base.PortInfo, PortRecord

public interface BooleanFlags

This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. Some optimizing can be done if needed; using the same bit position to mean more than one flag according to the class that owns the flag

Author:

Eric Blake

Field Summary

static int	ANTECEDANT_IS_BEHAVIORALLY_MODELED Records whether some ancestor of the cell is behaviorally modeled.
static int	ASYNC_PORT
static int	ASYNCHRONOUS_RESOLVED
static int	ATOMICALLY_PLACEABLE Whether a cell is placeable
static int	ATOMICALLY_UNMAPPABLE Whether a cell is mappable
static int	BEHAVIORALLY_MODELED_BRANCH Records whether a cell or one of its ancestors is behaviorally modeled.
static int	CLK_PORT Represents an clk port
static int	CLOCK_METHOD_IMPLEMENTED_BY_USER Records whether the Structural.clock() method of a Structural cell is implemented by the use.
static int	CLOCK_METHOD_IS_DISABLED Records whether the Structural.clock() method of a Structural cell should be called.
static int	CLOCKABLE_IS_SCHEDULED
static int	DANGLING_IS_OK Whether it is permissable for a wire to dangle (have no sinks)
static int	DELETE_MARK Marks an element as ready for deletion, to save list overhead traversal
static int	FATAL_BUILD_ERROR_OCCURED Whether a fatal error has occured in the system, preventing simulation
static int	HAS_BEEN_TRACED Whether a circuit element has been visited during a full circuit trace
static int	HAS_USER_SPECIFIED_NAME Whether the wire that this Net represents has a user-specified name
static int	HWUPDATE Whether a Clockable cell should be updated by hardware or simulation
static int	IMPLICIT_PORT Whether a port is implicit
static int	IN_CLK_PORT Represents an input clk port
static int	IN_PORT Represents an input port
static int	INOUT_PORT Represents an inout port
static int	IO_TYPE_FLAGS Group of possible port types
static int	IS_BEHAVIORALLY_MODELED Records whether a cell's methods will be used for behavior during simulation
static int	IS_ON_BUILD_STACK Records whether a cell is in the process of being built
static int	IS_ON_PROP_LIST Whether a simulation object is on a list to be simulated
static int	IS_PLACED Whether a cell has been placed
static int	METHODS_IMPLEMENTED_BY_USER Group of methods that can be implemented by the user in Structural
static int	NETLISTABLE Whether a circuit element is netlistable
static int	ORIG_WIRE_IS_ATOMIC Whether the wire that this Net represents is atomic
static int	OUT_PORT Represents an output port
static int	PLACEMENT_IS_LOCKED Whether a cell's placement has been locked
static int	PROPAGATE_METHOD_IMPLEMENTED_BY_USER Records whether the Structural.propagate() method of a Structural cell is implemented by the use.
static int	PROPAGATE_METHOD_IS_DISABLED Records whether the Structural.propagate() method of a Structural cell should be called.
static int	RECURSION_FLAG Whether a wire has been visited during a recursive trace
static int	RESET_METHOD_IMPLEMENTED_BY_USER Records whether the Structural.reset() method of a Structural cell is implemented by the use.
static int	SIMULATEABLE Whether a circuit element is simulateable
static int	SOURCELESS_IS_OK Whether it is permissable for a wire to be sourceless
static int	SYNC_PORT
static int	VISIBLE Whether a circuit element is visible in a browser

Field Detail

IS_ON_BUILD_STACK

public static final int IS_ON_BUILD_STACK

Records whether a cell is in the process of being built

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IS_BEHAVIORALLY_MODELED

public static final int IS_BEHAVIORALLY_MODELED

Records whether a cell's methods will be used for behavior during simulation

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ANTECEDANT_IS_BEHAVIORALLY_MODELED

public static final int ANTECEDANT_IS_BEHAVIORALLY_MODELED

Records whether some ancestor of the cell is behaviorally modeled.

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BEHAVIORALLY_MODELED_BRANCH

public static final int BEHAVIORALLY_MODELED_BRANCH

Records whether a cell or one of its ancestors is behaviorally modeled.

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PROPAGATE_METHOD_IS_DISABLED

public static final int PROPAGATE_METHOD_IS_DISABLED

Records whether the Structural.propagate() method of a Structural cell should be called.

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CLOCK_METHOD_IS_DISABLED

public static final int CLOCK_METHOD_IS_DISABLED

Records whether the Structural.clock() method of a Structural cell should be called.

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CLOCK_METHOD_IMPLEMENTED_BY_USER

public static final int CLOCK_METHOD_IMPLEMENTED_BY_USER

Records whether the Structural.clock() method of a Structural cell is implemented by the use.

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RESET_METHOD_IMPLEMENTED_BY_USER

public static final int RESET_METHOD_IMPLEMENTED_BY_USER

Records whether the Structural.reset() method of a Structural cell is implemented by the use.

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PROPAGATE_METHOD_IMPLEMENTED_BY_USER

public static final int PROPAGATE_METHOD_IMPLEMENTED_BY_USER

Records whether the Structural.propagate() method of a Structural cell is implemented by the use.

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METHODS_IMPLEMENTED_BY_USER

public static final int METHODS_IMPLEMENTED_BY_USER

Group of methods that can be implemented by the user in Structural

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HWUPDATE

public static final int HWUPDATE

Whether a Clockable cell should be updated by hardware or simulation

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IS_ON_PROP_LIST

public static final int IS_ON_PROP_LIST

Whether a simulation object is on a list to be simulated

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HAS_BEEN_TRACED

public static final int HAS_BEEN_TRACED

Whether a circuit element has been visited during a full circuit trace

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DANGLING_IS_OK

public static final int DANGLING_IS_OK

Whether it is permissable for a wire to dangle (have no sinks)

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SOURCELESS_IS_OK

public static final int SOURCELESS_IS_OK

Whether it is permissable for a wire to be sourceless

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CLOCKABLE_IS_SCHEDULED

public static final int CLOCKABLE_IS_SCHEDULED

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ASYNC_PORT

public static final int ASYNC_PORT

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SYNC_PORT

public static final int SYNC_PORT

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ASYNCHRONOUS_RESOLVED

public static final int ASYNCHRONOUS_RESOLVED

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RECURSION_FLAG

public static final int RECURSION_FLAG

Whether a wire has been visited during a recursive trace

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FATAL_BUILD_ERROR_OCCURED

public static final int FATAL_BUILD_ERROR_OCCURED

Whether a fatal error has occured in the system, preventing simulation

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IS_PLACED

public static final int IS_PLACED

Whether a cell has been placed

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PLACEMENT_IS_LOCKED

public static final int PLACEMENT_IS_LOCKED

Whether a cell's placement has been locked

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ORIG_WIRE_IS_ATOMIC

public static final int ORIG_WIRE_IS_ATOMIC

Whether the wire that this Net represents is atomic

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HAS_USER_SPECIFIED_NAME

public static final int HAS_USER_SPECIFIED_NAME

Whether the wire that this Net represents has a user-specified name

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ATOMICALLY_PLACEABLE

public static final int ATOMICALLY_PLACEABLE

Whether a cell is placeable

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ATOMICALLY_UNMAPPABLE

public static final int ATOMICALLY_UNMAPPABLE

Whether a cell is mappable

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IN_PORT

public static final int IN_PORT

Represents an input port

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OUT_PORT

public static final int OUT_PORT

Represents an output port

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INOUT_PORT

public static final int INOUT_PORT

Represents an inout port

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CLK_PORT

public static final int CLK_PORT

Represents an clk port

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IN_CLK_PORT

public static final int IN_CLK_PORT

Represents an input clk port

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IO_TYPE_FLAGS

public static final int IO_TYPE_FLAGS

Group of possible port types

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IMPLICIT_PORT

public static final int IMPLICIT_PORT

Whether a port is implicit

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NETLISTABLE

public static final int NETLISTABLE

Whether a circuit element is netlistable

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VISIBLE

public static final int VISIBLE

Whether a circuit element is visible in a browser

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SIMULATEABLE

public static final int SIMULATEABLE

Whether a circuit element is simulateable

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DELETE_MARK

public static final int DELETE_MARK

Marks an element as ready for deletion, to save list overhead traversal

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