Package byucc.jhdl.base

Interface Summary

BooleanFlags	This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits.
Browser	This is a tagging interface that allows additional access to JHDL classes, such as looking at arbitrary Wires, for example.
Buf	This interface allows ClockDrivers to identify buffers, so that flipflops that are separated by their ClockDriver by only a buf will be able to take advantage of static scheduling and not be gated.
CellInterface
Checkpointable	This interface flags JHDL objects (*other* than those primitives who are ExternallyUpdatable) that can be Checkpointed when a circuit checkpoint is performed.
Clockable	This interface must be implemented by any clockable cell.
ConstantSource	This interface defines a cell that drives an unchanging value onto a wire.
ExternallyUpdateable	This interface is used to put the information from a readback back into the cell.
HardwareInterface	This interface marks a circuit that can be executed in hardware.
Initializeable	This interface is used for cells that must do some pre-simulation initialization
LargeExternallyUpdateable
LargeMemoryInterface	This defines an interface for larger memory; allowing faster access than the regular MemoryInterface interface.
LargeWritableMemory
MemoryInterface	This defines an interface for memory.
Observable	Deprecated. The Observable interface has been replaced by the byucc.jhdl.base.SimulatorCallback interface.
ProgrammaticTestBench	Just a tagging interface to indicate that something is a programatic testbench.
SimulatorCallback	This interface is used by any object that wants to receive callbacks from the simulator.
SubCell	This is a marker of an instantiable version of a Cell that works with Cell#pushHierarchy() and Cell.popHierarchy().
TestBench	Describes a testbench - a top level cell for generating test data to drive a circuit.
TriStateDriver	This interface allows a class to implement tri-state behavior.
UndrivenInputsAllowable	This interface marks a primitive Cell which ignores certain input ports based on decisions made at construction (for example, the cy4 block of the Xilinx XC4000 library operates in a number of modes, and not all inputs are used in each mode).
WriteableHardwareInterface	This interface describes hardware that can be set from stored state

Class Summary

Annotation	This class provides a Cell class that cannot be simulated.
ArgBlock
ArgBlockList
AtomicConnection	This class represents an atomic port of a cell that a net connects to in an atomic Netlist.
AtomicNet	Stores a net of an atomic netlist with all its connections
AtomicNetlist	This class defines a netlist whose nets are all atomic width.
Bindings
BusConnection	Used to store connection information that can be used by netlisting code.
BusNet	Used by BusNetlist to represent a bus, from which various subsets are used as connections to ports.
BusNetlist	Represents the netlist of a cell using busses.
BV	Copyright (c) 1999-2000 Brigham Young University.
Cell	The Cell class extends the Node class to provide named-port and generic-width capability.
CellList	This holds a list of cells.
CL	This can be used as a super-class for a cell that is purely combinational.
ClockDriver	Class used to create clock drivers.
CompiledCodeGenerator	This class is a generic interface for compiled code simulators.
Connection	Used to store connection information that can be used by netlisting code.
ConnectionList	Holds a list of Connections, and can be iterated.
ConstBV	This class extends BV to provide a constant value.
Debug	This class holds some old debugging utilities.
DefaultSubCell
DynamicClockDriver	Class used to create clock drivers.
ExternalUpdateManager	Object to manage the external update of a jhdl design Right now we are considering two different types of updates 1) updates from checkpointing.
Flags	This class defines a set of flag manipulation utilities designed for optimal use of memory.
FlatConnection	This class represents a connection of a flat netlisting net to a port of a leaf cell or top level cell.
FlatNet	Stores a flat netlist net of atomic width with all connections to the top-level ports and all leaf cells.
FlatNetlist	This class defines a flat netlist whose nets are all atomic width.
HelperLibrary
HWProcess	This file contains the code that comprises most of the javaHDL simulation kernel.
HWSystem	This class defines a the top-level node for a circuit.
InitializeableList	This holds a list of Initializeables.
Nameable	Class for providing name capability for Wires and Nodes in the JHDL circuit graph.
Net	Used by Netlist to associate wires with a list of connection records.
Netlist	Used to collect connection information between Cells and atomic wires.
Node	Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires.
NodeList	This keeps a list of nodes.
ObservableList	Stores a list of Observables
Parameter	This class allows the creation of arbitrarily typed parameters as part of a CellInterface.
PlacementInfo	This class is the superclass for libraries that implement placement
Port	This class represents a port within a cell's interface.
PortRecord	This class serves as an interface to extract port information from a Cell.
PortRecordList	Stores a list of PortRecords
Property	The Property class allows a user to attach an arbitrary number of name-value properties, where the value can be of any type, to a Cell or Wire.
PropertyBoolean	Convenience wrapper class for Property, that is always of type Boolean.
PropertyInt	Convenience wrapper class for Property, that is always of type Integer.
PropertyList	This class stores a list of properties that correspond to a Cell or Wire.
PropertyString	Convenience wrapper class for Property, that is always of type String.
PullUpDown
SimulatorCallbackList	Stores a list of SimultatorCallback objects.
StateObject	This is used to represent the state of a circuit at a given clock cycle.
Structural	If the node only contains instantiations of other kinds of nodes, this is the container class to use.
Synchronous	Base class for defining a synchronous circuit element.
temp_cell	Used by BV for testing
Util	A set of utility routines.
VisibleAnnotation	This class provides a Cell class that cannot be simulated It can only be used to annotate the circuit and was provided primarily for use by the techmapper.
Wire	A base class for wires that communicate actual values in the system.
WireList	Stores a list of wires

Exception Summary

BuildException	This exception is the basic exception for all JHDL errors related to circuit building.
BVException	Designed to allow exception trapping related directly to the BV class.
CellInterfaceException	Thrown when there is a problem interpreting a cell interface.
CompiledCodeException	This is thrown when a user cell does not have a behavioral model, but an attempt is made to use the cell behaviorally
FloatException	This checked exception notifies that a wire was floating during an attempt to do a Wire.get(source) or related call on the wire.
NoBehavioralModelException	This is thrown when a user cell does not have a behavioral model, but an attempt is made to use the cell behaviorally
PutGetException	This is thrown when an attempt is made to access a wire when it is not allowed.
SimulationException	This is thrown when an error occurs during simulation.
TypeException	This is thrown in relation to binding parameters, when types clash.
UnboundException	This is thrown when evaluating a parameter that has not yet been bound.
UnimplementedException	This is thrown when a user calls a simulation method on a cell that does not define that method.
WireValueException	This checked exception notifies when a wire did not have a valid value (in other words, it was either floating or had multiple sources) during an attempt to do a Wire.get(source) or related call on the wire.