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| Classes in byucc.jhdl.base used by byucc.jhdl.CSRC | |
| ArgBlockList
|
|
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| CL
This can be used as a super-class for a cell that is purely combinational. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ClockDriver
Class used to create clock drivers. |
|
| ConstantSource
This interface defines a cell that drives an unchanging value onto a wire. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| PlacementInfo
This class is the superclass for libraries that implement placement |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| UndrivenInputsAllowable
This interface marks a primitive Cell which ignores certain input ports based on decisions made at construction (for example, the cy4 block of the Xilinx XC4000 library operates in a number of modes, and not all inputs are used in each mode). |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| WireList
Stores a list of wires |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.DRC | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| CellList
This holds a list of cells. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.DRC.Rules | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellList
This holds a list of cells. |
|
| WireList
Stores a list of wires |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.DRC.Rules.Virtex | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.DRC.Rules.XC4000 | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.DRC.Tester | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Fsm | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| HWSystem
This class defines a the top-level node for a circuit. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| PlacementInfo
This class is the superclass for libraries that implement placement |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| SubCell
This is a marker of an instantiable version of a Cell that works with Cell#pushHierarchy() and Cell.popHierarchy(). |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| WireList
Stores a list of wires |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.CordicPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.DigitSerial | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2 | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8 | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4 | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint.SqPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint.examples | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.FloatingPoint.helpers | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.ShiftRegPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Logic.Modules.helpers | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| ProgrammaticTestBench
Just a tagging interface to indicate that something is a programatic testbench. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.TERA | |
| ArgBlockList
|
|
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| CL
This can be used as a super-class for a cell that is purely combinational. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ClockDriver
Class used to create clock drivers. |
|
| ConstantSource
This interface defines a cell that drives an unchanging value onto a wire. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| WireList
Stores a list of wires |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx | |
| Annotation
This class provides a Cell class that cannot be simulated. |
|
| ArgBlockList
|
|
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Buf
This interface allows ClockDrivers to identify buffers, so that flipflops that are separated by their ClockDriver by only a buf will be able to take advantage of static scheduling and not be gated. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| CL
This can be used as a super-class for a cell that is purely combinational. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ClockDriver
Class used to create clock drivers. |
|
| ConstantSource
This interface defines a cell that drives an unchanging value onto a wire. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| Initializeable
This interface is used for cells that must do some pre-simulation initialization |
|
| MemoryInterface
This defines an interface for memory. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| UndrivenInputsAllowable
This interface marks a primitive Cell which ignores certain input ports based on decisions made at construction (for example, the cy4 block of the Xilinx XC4000 library operates in a number of modes, and not all inputs are used in each mode). |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| WireList
Stores a list of wires |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex | |
| Annotation
This class provides a Cell class that cannot be simulated. |
|
| ArgBlockList
|
|
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Buf
This interface allows ClockDrivers to identify buffers, so that flipflops that are separated by their ClockDriver by only a buf will be able to take advantage of static scheduling and not be gated. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Checkpointable
This interface flags JHDL objects (*other* than those primitives who are ExternallyUpdatable) that can be Checkpointed when a
circuit checkpoint is performed. |
|
| CL
This can be used as a super-class for a cell that is purely combinational. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| Initializeable
This interface is used for cells that must do some pre-simulation initialization |
|
| LargeExternallyUpdateable
|
|
| MemoryInterface
This defines an interface for memory. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| PlacementInfo
This class is the superclass for libraries that implement placement |
|
| Property
The Property class allows a user to attach an arbitrary number of name-value properties, where the value can be of any type, to a Cell or Wire. |
|
| PullUpDown
|
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Synchronous
Base class for defining a synchronous circuit element. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| TriStateDriver
This interface allows a class to implement tri-state behavior. |
|
| UndrivenInputsAllowable
This interface marks a primitive Cell which ignores certain input ports based on decisions made at construction (for example, the cy4 block of the Xilinx XC4000 library operates in a number of modes, and not all inputs are used in each mode). |
|
| VisibleAnnotation
This class provides a Cell class that cannot be simulated It can only be used to annotate the circuit and was provided primarily for use by the techmapper. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| WireList
Stores a list of wires |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex.Modules | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| LargeMemoryInterface
This defines an interface for larger memory; allowing faster access than the regular MemoryInterface interface. |
|
| LargeWritableMemory
|
|
| MemoryInterface
This defines an interface for memory. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| HWSystem
This class defines a the top-level node for a circuit. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex.helpers | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Synchronous
Base class for defining a synchronous circuit element. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex.ramb4_wrapper | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex2 | |
| ArgBlockList
|
|
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Buf
This interface allows ClockDrivers to identify buffers, so that flipflops that are separated by their ClockDriver by only a buf will be able to take advantage of static scheduling and not be gated. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Checkpointable
This interface flags JHDL objects (*other* than those primitives who are ExternallyUpdatable) that can be Checkpointed when a
circuit checkpoint is performed. |
|
| CL
This can be used as a super-class for a cell that is purely combinational. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| Initializeable
This interface is used for cells that must do some pre-simulation initialization |
|
| LargeExternallyUpdateable
|
|
| MemoryInterface
This defines an interface for memory. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| PlacementInfo
This class is the superclass for libraries that implement placement |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| TriStateDriver
This interface allows a class to implement tri-state behavior. |
|
| VisibleAnnotation
This class provides a Cell class that cannot be simulated It can only be used to annotate the circuit and was provided primarily for use by the techmapper. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| WireList
Stores a list of wires |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex2.Modules | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.Virtex2.RamPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| MemoryInterface
This defines an interface for memory. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.XC4000 | |
| Annotation
This class provides a Cell class that cannot be simulated. |
|
| ArgBlockList
|
|
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Buf
This interface allows ClockDrivers to identify buffers, so that flipflops that are separated by their ClockDriver by only a buf will be able to take advantage of static scheduling and not be gated. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| CL
This can be used as a super-class for a cell that is purely combinational. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ConstantSource
This interface defines a cell that drives an unchanging value onto a wire. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| Initializeable
This interface is used for cells that must do some pre-simulation initialization |
|
| MemoryInterface
This defines an interface for memory. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| PlacementInfo
This class is the superclass for libraries that implement placement |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Synchronous
Base class for defining a synchronous circuit element. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| UndrivenInputsAllowable
This interface marks a primitive Cell which ignores certain input ports based on decisions made at construction (for example, the cy4 block of the Xilinx XC4000 library operates in a number of modes, and not all inputs are used in each mode). |
|
| VisibleAnnotation
This class provides a Cell class that cannot be simulated It can only be used to annotate the circuit and was provided primarily for use by the techmapper. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.XC4000.Modules | |
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| MemoryInterface
This defines an interface for memory. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.XC4000.carryLogic | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ConstantSource
This interface defines a cell that drives an unchanging value onto a wire. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.XC4000.techmap | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| PlacementInfo
This class is the superclass for libraries that implement placement |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.XC4000.techmap.lists | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.XC4000.techmap.tree | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.XC9000 | |
| ArgBlockList
|
|
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Buf
This interface allows ClockDrivers to identify buffers, so that flipflops that are separated by their ClockDriver by only a buf will be able to take advantage of static scheduling and not be gated. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| PlacementInfo
This class is the superclass for libraries that implement placement |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| WireList
Stores a list of wires |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.Xilinx.demo | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| CL
This can be used as a super-class for a cell that is purely combinational. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Broker | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| HWSystem
This class defines a the top-level node for a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Jab | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Browser
This is a tagging interface that allows additional access to JHDL classes, such as looking at arbitrary Wires, for example. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| HWSystem
This class defines a the top-level node for a circuit. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| PortRecord
This class serves as an interface to extract port information from a Cell. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Stimulator | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Browser
This is a tagging interface that allows additional access to JHDL classes, such as looking at arbitrary Wires, for example. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TriStateDriver
This interface allows a class to implement tri-state behavior. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Stimulator.functions | |
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Tbone | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Checkpointable
This interface flags JHDL objects (*other* than those primitives who are ExternallyUpdatable) that can be Checkpointed when a
circuit checkpoint is performed. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| HardwareInterface
This interface marks a circuit that can be executed in hardware. |
|
| HWSystem
This class defines a the top-level node for a circuit. |
|
| LargeExternallyUpdateable
|
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| SimulatorCallback
This interface is used by any object that wants to receive callbacks from the simulator. |
|
| StateObject
This is used to represent the state of a circuit at a given clock cycle. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| HWSystem
This class defines a the top-level node for a circuit. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.BrowserMainFrame | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.ClassInfo | |
| SimulatorCallback
This interface is used by any object that wants to receive callbacks from the simulator. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.Event | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.FloorPlan | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.JL | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.MemoryView | |
| SimulatorCallback
This interface is used by any object that wants to receive callbacks from the simulator. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.NewTreeBrowser | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.Schematic | |
| Browser
This is a tagging interface that allows additional access to JHDL classes, such as looking at arbitrary Wires, for example. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Net
Used by Netlist to associate wires with a list of connection records. |
|
| Netlist
Used to collect connection information between Cells and atomic wires. |
|
| PortRecord
This class serves as an interface to extract port information from a Cell. |
|
| SimulatorCallback
This interface is used by any object that wants to receive callbacks from the simulator. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.SimControl | |
| HWSystem
This class defines a the top-level node for a circuit. |
|
| SimulatorCallback
This interface is used by any object that wants to receive callbacks from the simulator. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.TreeBrowser | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.Waves | |
| Browser
This is a tagging interface that allows additional access to JHDL classes, such as looking at arbitrary Wires, for example. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| SimulatorCallback
This interface is used by any object that wants to receive callbacks from the simulator. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.WiresTable | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.Viewers.cvt | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.dtb | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.dtb.cli | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.dtb.listener | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.apps.util | |
| HWSystem
This class defines a the top-level node for a circuit. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.base | |
| ArgBlock
|
|
| ArgBlockList
|
|
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Browser
This is a tagging interface that allows additional access to JHDL classes, such as looking at arbitrary Wires, for example. |
|
| BusNet
Used by BusNetlist to represent a bus, from which various subsets are used as connections to ports. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| CellList
This holds a list of cells. |
|
| Checkpointable
This interface flags JHDL objects (*other* than those primitives who are ExternallyUpdatable) that can be Checkpointed when a
circuit checkpoint is performed. |
|
| CL
This can be used as a super-class for a cell that is purely combinational. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ClockDriver
Class used to create clock drivers. |
|
| Connection
Used to store connection information that can be used by netlisting code. |
|
| ConnectionList
Holds a list of Connections, and can be iterated. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| FlatNetlist
This class defines a flat netlist whose nets are all atomic width. |
|
| HardwareInterface
This interface marks a circuit that can be executed in hardware. |
|
| HWSystem
This class defines a the top-level node for a circuit. |
|
| Initializeable
This interface is used for cells that must do some pre-simulation initialization |
|
| LargeExternallyUpdateable
|
|
| LargeMemoryInterface
This defines an interface for larger memory; allowing faster access than the regular MemoryInterface interface. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Net
Used by Netlist to associate wires with a list of connection records. |
|
| Netlist
Used to collect connection information between Cells and atomic wires. |
|
| NoBehavioralModelException
This is thrown when a user cell does not have a behavioral model, but an attempt is made to use the cell behaviorally |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| NodeList
This keeps a list of nodes. |
|
| Observable
Deprecated. The Observable interface has been replaced by the byucc.jhdl.base.SimulatorCallback interface. This interface will be removed soon in 2002. |
|
| PlacementInfo
This class is the superclass for libraries that implement placement |
|
| PortRecord
This class serves as an interface to extract port information from a Cell. |
|
| PortRecordList
Stores a list of PortRecords |
|
| Property
The Property class allows a user to attach an arbitrary number of name-value properties, where the value can be of any type, to a Cell or Wire. |
|
| PropertyList
This class stores a list of properties that correspond to a Cell or Wire. |
|
| SimulatorCallback
This interface is used by any object that wants to receive callbacks from the simulator. |
|
| StateObject
This is used to represent the state of a circuit at a given clock cycle. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| SubCell
This is a marker of an instantiable version of a Cell that works with Cell#pushHierarchy() and Cell.popHierarchy(). |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| UndrivenInputsAllowable
This interface marks a primitive Cell which ignores certain input ports based on decisions made at construction (for example, the cy4 block of the Xilinx XC4000 library operates in a number of modes, and not all inputs are used in each mode). |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| WireList
Stores a list of wires |
|
| WireValueException
This checked exception notifies when a wire did not have a valid value (in other words, it was either floating or had multiple sources) during an attempt to do a Wire.get(source) or related call on the wire. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.base.genericparser | |
| Bindings
|
|
| Classes in byucc.jhdl.base used by byucc.jhdl.contrib.modgen | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.contrib.modgen.AddSubPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.contrib.modgen.CordicPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.contrib.modgen.IntDividePack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.contrib.modgen.MultArrayPack | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.examples | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| ProgrammaticTestBench
Just a tagging interface to indicate that something is a programatic testbench. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.examples.des | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.examples.editDistance | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.examples.fsm | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.examples.shifter | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.examples.xr16cpu | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.netlisters | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.netlisters.jhdl | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.parsers.edif | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.parsers.edif.NewJHDLGenerator | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.parsers.edif.sablecc | |
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.parsers.edif.sablecc.translation | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.parsers.xnf | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Property
The Property class allows a user to attach an arbitrary number of name-value properties, where the value can be of any type, to a Cell or Wire. |
|
| PropertyList
This class stores a list of properties that correspond to a Cell or Wire. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.platforms.util | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| CellInterface
|
|
| Checkpointable
This interface flags JHDL objects (*other* than those primitives who are ExternallyUpdatable) that can be Checkpointed when a
circuit checkpoint is performed. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| HardwareInterface
This interface marks a circuit that can be executed in hardware. |
|
| LargeExternallyUpdateable
|
|
| LargeMemoryInterface
This defines an interface for larger memory; allowing faster access than the regular MemoryInterface interface. |
|
| LargeWritableMemory
|
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| StateObject
This is used to represent the state of a circuit at a given clock cycle. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.platforms.util.multicontext | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.platforms.util.readback | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| ExternallyUpdateable
This interface is used to put the information from a readback back into the cell. |
|
| LargeExternallyUpdateable
|
|
| Classes in byucc.jhdl.base used by byucc.jhdl.platforms.util.readback.Xilinx | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| HWSystem
This class defines a the top-level node for a circuit. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.synth | |
| BooleanFlags
This class globally defines a set of constants of masks to reach various bits of a packed set holding up to 32 bits. |
|
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
| Clockable
This interface must be implemented by any clockable cell. |
|
| Nameable
Class for providing name capability for Wires and Nodes in the JHDL circuit graph. |
|
| Node
Abstract class that implements a Node in a circuit graph that consists of Nodes and Wires. |
|
| Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
|
| TestBench
Describes a testbench - a top level cell for generating test data to drive a circuit. |
|
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.synth.operators | |
| Wire
A base class for wires that communicate actual values in the system. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.util.BVFormat | |
| BV
Copyright (c) 1999-2000 Brigham Young University. |
|
| Classes in byucc.jhdl.base used by byucc.jhdl.util.gui | |
| Cell
The Cell class extends the Node class to provide
named-port and generic-width capability. |
|
|
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