|
Class Summary |
| addsubX |
Generic width adder-subtractor. |
| addX |
Generic width adder. |
| and2_dp |
This class implements and asynchronous 2-input and gate. |
| and2_dp_g |
This class implements and asynchronous 2-input and gate. |
| and3_dp |
This class implements and asynchronous 3-input and gate. |
| and3_dp_g |
This class implements and asynchronous 3-input and gate. |
| and4_dp |
This class implements and asynchronous 4-input and gate. |
| and5_dp |
This class implements and asynchronous 5-input and gate. |
| and6_dp |
This class implements and asynchronous 6-input and gate. |
| and7_dp |
This class implements and asynchronous 7-input and gate. |
| and8_dp |
This class implements and asynchronous 8-input and gate. |
| and9_dp |
This class implements and asynchronous 9-input and gate. |
| andX |
This class implements an AND gate with arbitrary number of inputs. |
| buf |
Buffer. |
| bufX |
This cell buffers each input wire. |
| Constant |
This class is a structural cell which drives a constant value
on to its output wire. |
| CSRCCL |
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| CSRCClockDriver |
|
| CSRCFD |
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| CSRCTechMapper |
|
| CSRCWire |
|
| dff_dp |
The dff_dp is a simple D-flipflop. |
| dff_dpX |
This instantiates a generic width dff_dp. |
| dffe_dp |
The dffe_dp is a D-flipflop with a clock enable. |
| dffe_dpX |
This instantiates a generic width dffe_dp. |
| dffr_dp |
The dffr_dp is a D-flipflop with a synchronous reset. |
| dffr_dpX |
This instantiates a generic width dffs_dp. |
| dffre_dp |
The dffre_dp is a D-flipflop with a synchronous reset
and a clock enable. |
| dffre_dpX |
This instantiates a generic width dffre_dp. |
| dffs_dp |
The dffs_dp is a D-flipflop with a synchronous set. |
| dffs_dpX |
This instantiates a generic width dffr_dp. |
| dffse_dp |
The dffse_dp is a D-flipflop with a synchronous set
and a clock enable. |
| dffse_dpX |
This instantiates a generic width dffse_dp. |
| DL_ONE |
Returns a logic one. |
| DL_ZERO |
Returns a logic zero. |
| gndX |
This instantiates a generic width vcc. |
| IB |
This is an input buffer. |
| IBX |
Generic width output buffer. |
| maj3 |
3-input majority gate. |
| mux_dpX |
Generic width 2-1 Mux. |
| mux3_dp |
2-1 Mux. |
| nand2_dp |
This class implements and asynchronous 2-input nand gate. |
| nand2_dp_g |
This class implements and asynchronous 2-input nand gate. |
| nand3_dp |
This class implements and asynchronous 3-input nand gate. |
| nand3_dp_g |
This class implements and asynchronous 3-input nand gate. |
| nand4_dp |
This class implements and asynchronous 4-input nand gate. |
| nand5_dp |
This class implements and asynchronous 5-input nand gate. |
| nand6_dp |
This class implements and asynchronous 6-input nand gate. |
| nand7_dp |
This class implements and asynchronous 7-input nand gate. |
| nand8_dp |
This class implements and asynchronous 8-input nand gate. |
| nand9_dp |
This class implements and asynchronous 9-input nand gate. |
| nandX |
This class implements an NAND gate with arbitrary number of inputs. |
| nor2_dp |
This class implements and asynchronous 2-input nor gate. |
| nor2_dp_g |
This class implements and asynchronous 2-input nor gate. |
| nor3_dp |
This class implements and asynchronous 3-input nor gate. |
| nor3_dp_g |
This class implements and asynchronous 3-input nor gate. |
| nor4_dp |
This class implements and asynchronous 4-input nor gate. |
| nor5_dp |
This class implements and asynchronous 5-input nor gate. |
| nor6_dp |
This class implements and asynchronous 6-input nor gate. |
| nor7_dp |
This class implements and asynchronous 7-input nor gate. |
| nor8_dp |
This class implements and asynchronous 8-input nor gate. |
| nor9_dp |
This class implements and asynchronous 9-input nor gate. |
| norX |
This class implements an NOR gate with arbitrary number of inputs. |
| not_dp |
Inverter. |
| notX |
This cell inverts each input wire. |
| OB |
This is an output buffer. |
| OBT |
This is an output buffer with a (high?) asserted output enable. |
| OBTX |
Generic width output buffer. |
| OBX |
Generic width output buffer. |
| or2_dp |
This class implements and asynchronous 2-input or gate. |
| or2_dp_g |
This class implements and asynchronous 2-input or gate. |
| or3_dp |
This class implements and asynchronous 3-input or gate. |
| or3_dp_g |
This class implements and asynchronous 3-input or gate. |
| or4_dp |
This class implements and asynchronous 4-input or gate. |
| or5_dp |
This class implements and asynchronous 5-input or gate. |
| or6_dp |
This class implements and asynchronous 6-input or gate. |
| or7_dp |
This class implements and asynchronous 7-input or gate. |
| or8_dp |
This class implements and asynchronous 8-input or gate. |
| or9_dp |
This class implements and asynchronous 9-input or gate. |
| orX |
This class implements an OR gate with arbitrary number of inputs. |
| Shifter |
This shifter was taken straight from the Xilinx directory. |
| subX |
Generic width subtractor. |
| TESTCSRCLibrary |
This class is the self-test controller for the CSRC library. |
| vccX |
This instantiates a generic width vcc. |
| xnor2_dp |
This class implements and asynchronous 2-input xnor gate. |
| xnor2_dp_g |
This class implements and asynchronous 2-input xnor gate. |
| xnor3_dp |
This class implements and asynchronous 3-input xnor gate. |
| xnor3_dp_g |
This class implements and asynchronous 3-input xnor gate. |
| xnor4_dp |
This class implements and asynchronous 4-input xnor gate. |
| xnor5_dp |
This class implements and asynchronous 5-input xnor gate. |
| xnor6_dp |
This class implements and asynchronous 6-input xnor gate. |
| xnor7_dp |
This class implements and asynchronous 7-input xnor gate. |
| xnor8_dp |
This class implements and asynchronous 8-input xnor gate. |
| xnor9_dp |
This class implements and asynchronous 9-input xnor gate. |
| xnorX |
This class implements an XNOR gate with arbitrary number of inputs. |
| xor2_dp |
This class implements and asynchronous 2-input xor gate. |
| xor2_dp_g |
This class implements and asynchronous 2-input xor gate. |
| xor3_dp |
This class implements and asynchronous 3-input xor gate. |
| xor3_dp_g |
This class implements and asynchronous 3-input xor gate. |
| xor4_dp |
This class implements and asynchronous 4-input xor gate. |
| xor5_dp |
This class implements and asynchronous 5-input xor gate. |
| xor6_dp |
This class implements and asynchronous 6-input xor gate. |
| xor7_dp |
This class implements and asynchronous 7-input xor gate. |
| xor8_dp |
This class implements and asynchronous 8-input xor gate. |
| xor9_dp |
This class implements and asynchronous 9-input xor gate. |
| xorX |
This class implements an XOR gate with arbitrary number of inputs. |