Uses of Interface
byucc.jhdl.base.ExternallyUpdateable

Packages that use ExternallyUpdateable

byucc.jhdl.apps.Tbone
byucc.jhdl.base
byucc.jhdl.CSRC
byucc.jhdl.platforms.util
byucc.jhdl.platforms.util.readback
byucc.jhdl.TERA
byucc.jhdl.Xilinx
byucc.jhdl.Xilinx.Virtex
byucc.jhdl.Xilinx.Virtex2
byucc.jhdl.Xilinx.XC4000
byucc.jhdl.Xilinx.XC9000

Uses of ExternallyUpdateable in byucc.jhdl.apps.Tbone

Methods in byucc.jhdl.apps.Tbone with parameters of type ExternallyUpdateable

StateObject

Tbone.getHardwareState(ExternallyUpdateable[] eCells, LargeExternallyUpdateable[] leCells, Checkpointable[] cCells)

Uses of ExternallyUpdateable in byucc.jhdl.base

Methods in byucc.jhdl.base that return ExternallyUpdateable

ExternallyUpdateable[]

HWSystem.getExternallyUpdateableCells() Method to get the list of ExternallyUpdateableCells

Methods in byucc.jhdl.base with parameters of type ExternallyUpdateable

StateObject	HardwareInterface.getHardwareState(ExternallyUpdateable[] eCells, LargeExternallyUpdateable[] leCells, Checkpointable[] cCells) Returns the hardware state
int	ExternalUpdateManager.findOutputValue(ExternallyUpdateable cCell) Deprecated. No longer used, ExternallyUpdatable#fetchState() used instead
void	WriteableHardwareInterface.setHardwareState(StateObject state, ExternallyUpdateable[] eCells, LargeExternallyUpdateable[] leCells, Checkpointable[] cCells) The method that sets the state

Uses of ExternallyUpdateable in byucc.jhdl.CSRC

Classes in byucc.jhdl.CSRC that implement ExternallyUpdateable

class	dff_dp The dff_dp is a simple D-flipflop.
class	dffe_dp The dffe_dp is a D-flipflop with a clock enable.
class	dffr_dp The dffr_dp is a D-flipflop with a synchronous reset.
class	dffre_dp The dffre_dp is a D-flipflop with a synchronous reset and a clock enable.
class	dffs_dp The dffs_dp is a D-flipflop with a synchronous set.
class	dffse_dp The dffse_dp is a D-flipflop with a synchronous set and a clock enable.

Uses of ExternallyUpdateable in byucc.jhdl.platforms.util

Methods in byucc.jhdl.platforms.util with parameters of type ExternallyUpdateable

StateObject

GenericBoard.getHardwareState(ExternallyUpdateable[] eCells, LargeExternallyUpdateable[] leCells, Checkpointable[] cCells)

Uses of ExternallyUpdateable in byucc.jhdl.platforms.util.readback

Methods in byucc.jhdl.platforms.util.readback with parameters of type ExternallyUpdateable

void	ReadWriteBackManager.setEUValues(ExternallyUpdateable[] eCells, int[] values) The method sets an array of writeback values corresponding to the given array of ExternallyUpdatable Cells.
int[]	ReadBackManager.getEUValues(ExternallyUpdateable[] eCells) Provides an array of readback values corresponding to the given array of ExternallyUpdatable Cells.

Uses of ExternallyUpdateable in byucc.jhdl.TERA

Classes in byucc.jhdl.TERA that implement ExternallyUpdateable

class

tera_dff The tera_dff is a simple D-flipflop.

Uses of ExternallyUpdateable in byucc.jhdl.Xilinx

Classes in byucc.jhdl.Xilinx that implement ExternallyUpdateable

class	Memory This layer of Memory abstraction extends BasicMemory and simply adds the ExternallyUpdateable interface
class	Memory_1 This layer of Memory abstraction extends BasicMemory and simply adds the ExternallyUpdateable interface
class	XilinxMemoryCL
class	XilinxMemorySynch
class	XilinxMemorySynch_1

Uses of ExternallyUpdateable in byucc.jhdl.Xilinx.Virtex

Classes in byucc.jhdl.Xilinx.Virtex that implement ExternallyUpdateable

class	fd D is a single D-type flip-flop with data input (D) and data output (Q).
class	fd_1 FD_1 is a single D-type flip-flop with data input (D) and data output (Q).
class	fdc FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q).
class	fdc_1 FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q).
class	fdce The FDCE is an asynchronously cleared, enabled D-type flip-flop.
class	fdce_1 FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs, and data output (Q).
class	fdcp FDCP is a single D-type flip-flop with data (D), asynchronous set (PRE), and asynchronous reset (CLR) inputs and data output (Q).
class	fdcp_1 FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q).
class	fdcpe FDRSE is a single D-type flip-flop with synchronous reset (CLR), synchronous set (PRE), and clock enable (CE) inputs and data output (Q).
class	fdcpe_1 FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q).
class	fde FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
class	fde_1 FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
class	fdp FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
class	fdp_1 FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
class	fdpe The FDPE is an asynchronously preset, enabled D-type flip-flop.
class	fdpe_1 FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q).
class	fdr FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdr_1 FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdre FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdre_1 FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdrs FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrs_1 FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrse FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fdrse_1 FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fds FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fds_1 FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fdse FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fdse_1 FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	ifdx The IFDX D-type flip-flop is contained in an input/output block (IOB).
class	ifdxi The IFDXI D-type flip-flop is contained in an input/output block (IOB).
class	ofdx OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops.
class	ram16x1d RAM16X1D is a 16-word by 1-bit static dual-ported RAM.
class	ram16x1d_1 RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.
class	ram16x1s RAM16X1S is a synchronous 16-word by 1-bit static RAM.
class	ram16x1s_1 RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.
class	ram16x2d RAM16X2D is a 16-word by 2-bit static dual-ported RAM.
class	ram16x2s RAM16X2S is a synchronous 16-word by 2-bit static RAM.
class	ram16x4d RAM16X4D is a 16-word by 4-bit static dual-ported RAM.
class	ram16x4s RAM16X4S is a synchronous 16-word by 4-bit static RAM.
class	ram16x8d RAM16X8D is a 16-word by 8-bit static dual-ported RAM.
class	ram16x8s RAM16X8S is a synchronous 16-word by 8-bit static RAM.
class	ram32x1s RAM32X1S is a synchronous 32-word by 1-bit static RAM.
class	ram32x1s_1 RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability.
class	ram32x1s_ack
class	ram32x2s RAM32X2S is a synchronous 32-word by 2-bit static RAM.
class	ram32x4s RAM32X4S is a synchronous 32-word by 4-bit static RAM.
class	ram32x8s RAM32X8S is a synchronous 32-word by 8-bit static RAM.
class	srl16 SRL16 is a shift register look up table (LUT).
class	srl16_1 SRL16_1 is a shift register look up table (LUT).
class	srl16e SRL16E is a shift register look up table (LUT).
class	srl16e_1 SRL16E_1 is a shift register look up table (LUT).

Uses of ExternallyUpdateable in byucc.jhdl.Xilinx.Virtex2

Classes in byucc.jhdl.Xilinx.Virtex2 that implement ExternallyUpdateable

class	ifddrcpe IFDDRCPE is a dual data rate (DDR) input D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR).
class	ifddrrse FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1).
class	ofddrtcpe OFDDRTCPE is a dual data rate (DDR) D flip-flop with clock enable (CE) and asynchronous preset and clear whose output is enabled by a 3-state buffer.
class	ofddrtrse OFDDRTRSE is a dual data rate (DDR) D flip-flop with clock enable (CE) and synchronous reset and set whose output is enabled by a 3-state buffer.
class	ram128x1s RAM128X1S is a 128-word by 1-bit static random access memory with synchronous write capability.
class	ram128x1s_1 RAM128X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability.
class	ram32x1d RAM32X1D is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.
class	ram32x1d_1 RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
class	ram64x1d RAM64X1D is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.
class	ram64x1d_1 RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
class	ram64x1s RAM64X1S is a 64-word by 1-bit static random access memory with synchronous write capability.
class	ram64x1s_1 RAM64X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability and a negative-edge clock.
class	ram64x2s RAM64X2S is a 64-word by 2-bit static random access memory with synchronous write capability.
class	srlc16 SRLC16 is a shift register look up table (LUT).
class	srlc16_1 SRLC16_1 is a shift register look up table (LUT).
class	srlc16e SRLC16E is a shift register look up table (LUT) with carry, clock enable, and asynchro-nous clear.
class	srlc16e_1 SRLC16E_1 is a shift register look up table (LUT).

Uses of ExternallyUpdateable in byucc.jhdl.Xilinx.XC4000

Classes in byucc.jhdl.Xilinx.XC4000 that implement ExternallyUpdateable

class	ram16x1 RAM16X1 is a 16-word by 1-bit static RAM.
class	ram32x1 RAM32X1 is a 32-word by 1-bit static RAM.

Uses of ExternallyUpdateable in byucc.jhdl.Xilinx.XC9000

Classes in byucc.jhdl.Xilinx.XC9000 that implement ExternallyUpdateable

class

ftcp Asynchronously presettable/clearable toggle flip-flop.