|
Class Summary |
| and2 |
This class implements and asynchronous 2-input and gate. |
| and2_g |
This class implements and asynchronous 2-input and gate. |
| and2b1 |
This class implements and asynchronous 2-input and gate. |
| and2b2 |
This class implements and asynchronous 2-input and gate. |
| and3 |
This class implements and asynchronous 3-input and gate. |
| and3_g |
This class implements and asynchronous 3-input and gate. |
| and3b1 |
This class implements and asynchronous 3-input and gate. |
| and3b2 |
This class implements and asynchronous 3-input and gate. |
| and3b3 |
This class implements and asynchronous 3-input and gate. |
| and4 |
This class implements and asynchronous 4-input and gate. |
| and4_g |
This class implements and asynchronous 4-input and gate. |
| and4b1 |
This class implements and asynchronous 4-input and gate. |
| and4b2 |
This class implements and asynchronous 4-input and gate. |
| and4b3 |
This class implements and asynchronous 4-input and gate. |
| and4b4 |
This class implements and asynchronous 4-input and gate. |
| and5 |
This class implements and asynchronous 5-input and gate. |
| and6 |
This class implements and asynchronous 6-input and gate. |
| and7 |
This class implements and asynchronous 7-input and gate. |
| and8 |
This class implements and asynchronous 8-input and gate. |
| and9 |
This class implements and asynchronous 9-input and gate. |
| andX |
This class implements an AND gate with arbitrary number of inputs. |
| andX_g |
|
| BlockRamView |
Deprecated. Use BlockRamView in RamPack instead. |
| BlockRamViewParity |
Deprecated. Use BlockRamView in RamPack instead. |
| bscan_virtex2 |
The BSCAN_VIRTEX2 symbol is used to create internal boundary scan
chains in a Virtex2 or Virtex2- E device. |
| buf |
BUF is a general purpose, non-inverting buffer. |
| buf_g |
The BUF_G is a generic-width non-inverting buffer cell. |
| bufcf |
BUFCF is a single fast connect buffer used to connect the outputs
of the LUTs and some dedicated logic directly to the input of
another LUT. |
| bufe |
BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple tristate
buffers with inputs I, I3 - I0, I7 - I0, and I15 - I0,
respectively; outputs O, O3 - O0, O7 - O0, and O15 - O0,
respectively; and active-High output enable (E). |
| bufg |
The BUFG cell is a global buffer which distributes high-fanout
clock signals throughout the device. |
| bufg_ann |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| bufgce |
BUFGCE is a multiplexed global clock buffer with a single gated
input. |
| bufgce_1 |
BUFGCE_1 is a multiplexed global clock buffer with a single gated
input. |
| bufgdll |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| bufge |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| bufgls |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| bufgmux |
BUFGMUX is a multiplexed global clock buffer that can select between
two input clocks I0 and I1. |
| bufgmux_1 |
BUFGMUX_1 is a multiplexed global clock buffer that can select between
two input clocks I0 and I1. |
| bufgp |
The BUFG cell is a global buffer which distributes high-fanout
clock signals throughout the device. |
| bufgs |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| buft |
BUFT is a 3-state buffer with input I, output O, and active-Low
output enable (T). |
| buft_g |
The BUFT_G is a generic-width tristate buffer cell. |
| capture_virtex2 |
CAPTURE_VIRTEX2 provides user control over when to capture register
(flip-flop and latch) information for readback. |
| CountingLinkedList |
|
| d3_8e |
The d3_8e class implements an enabled 3:8 decoder. |
| dcm |
DCM is a digital clock manager that provides multiple functions. |
| fd |
D is a single D-type flip-flop with data input (D) and data output
(Q). |
| fd_1 |
FD_1 is a single D-type flip-flop with data input (D) and data
output (Q). |
| fdc |
FDC is a single D-type flip-flop with data (D) and asynchronous
clear (CLR) inputs and data output (Q). |
| fdc_1 |
FDC_1 is a single D-type flip-flop with data input (D),
asynchronous clear input (CLR), and data output (Q). |
| fdc_1_g |
Implements an asynchronously clearable register in the XC4000
library. |
| fdc_g |
Implements an asynchronously clearable register in the XC4000
library. |
| fdce |
The FDCE is an asynchronously cleared, enabled D-type flip-flop. |
| fdce_1 |
FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE),
asynchronous clear (CLR) inputs, and data output (Q). |
| fdce_g |
The FDCE_G is a generic-width, asynchronously cleared, enabled
D-type flip-flop. |
| fdcp |
FDCP is a single D-type flip-flop with data (D), asynchronous set
(PRE), and asynchronous reset (CLR) inputs and data output (Q). |
| fdcp_1 |
FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset
(PRE) and clear (CLR) inputs, and data output (Q). |
| fdcpe |
FDRSE is a single D-type flip-flop with synchronous reset (CLR),
synchronous set (PRE), and clock enable (CE) inputs and data output
(Q). |
| fdcpe_1 |
FDCPE_1 is a single D-type flip-flop with data (D), clock enable
(CE), asynchronous preset (PRE), and asynchronous clear (CLR)
inputs and data output (Q). |
| fddrcpe |
FDDRCPE is a Dual Data Rate (DDR) D flip-flop with two separate
clocks (C0 and C1) phase shifted 180 degrees that allow selection
of two separate data inputs (D0 and D1). |
| fddrrse |
FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate
clocks (C0 and C1) phase shifted 180 degrees that allow selection
of two separate data inputs (D0 and D1). |
| fde |
FDE is a single D-type flip-flop with data input (D), clock enable
(CE), and data output (Q). |
| fde_1 |
FDE_1 is a single D-type flip-flop with data input (D), clock
enable (CE), and data output (Q). |
| fdp |
FDP is a single D-type flip-flop with data (D) and asynchronous
preset (PRE) inputs and data output (Q). |
| fdp_1 |
FDP_1 is a single D-type flip-flop with data (D) and asynchronous
preset (PRE) inputs and data output (Q). |
| fdp_1_g |
Implements an asynchronously settable register in the XC4000
library. |
| fdp_g |
Implements an asynchronously settable register in the XC4000
library. |
| fdpe |
The FDPE is an asynchronously preset, enabled D-type flip-flop. |
| fdpe_1 |
FDPE_1 is a single D-type flip-flop with data (D), clock enable
(CE), and asynchronous preset (PRE) inputs and data output (Q). |
| fdpe_g |
The FDCE_P is a generic-width, asynchronously preset, enabled
D-type flip-flop. |
| fdr |
FDR is a D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdr_1 |
FDR_1 is a single D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdr_1_g |
FDR is a D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdr_g |
FDR is a D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdre |
FDRE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). |
| fdre_1 |
FDRE_1 is a single D-type flip-flop with data (D), clock enable
(CE), and synchronous reset (R) inputs and data output (Q). |
| fdre_1_g |
FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). |
| fdre_g |
FDRE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). |
| fdrs |
FDRS is a single D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_1 |
FDRS_1 is a single D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_1_g |
FDRS_1 is a D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_g |
FDRS is a D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrse |
FDRSE is a single D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_1 |
FDRSE_1 is a single D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_1_g |
FDRSE is a D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_g |
FDRSE is a D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fds |
FDS is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fds_1 |
FDS_1 is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fds_1_g |
FDS_1 is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fds_g |
FDS is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fdse |
FDSE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fdse_1 |
FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fdse_1_g |
FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fdse_g |
FDSE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fmap |
The FMAP symbol is used to control logic partitioning into XC4000
family 4-input function generators. |
| fmap_g |
The fmap_g is a generic_width and generic port count wrapper for all
XC4000 techmapper specific cells. |
| gnd |
This class is the GND cell for the Xilinx tools as well as
for JHDL simulation. |
| ibuf |
IBUF is a single input buffer. |
| ibuf_agp |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_ann |
IBUF is a single input buffer. |
| ibuf_ctt |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_g |
IBUF is a single input buffer. |
| ibuf_gtl |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_gtlp |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_hstl_i |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_hstl_iii |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_hstl_iv |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_lvcmos2 |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_lvttl |
IBUF is a single input buffer. |
| ibuf_pci33_3 |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_pci33_5 |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_pci66_3 |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_sstl2_i |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_sstl2_ii |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_sstl3_i |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibuf_sstl3_ii |
For Virtex2 and Spartan2, IBUF and its variants (listed below) are
single input buffers whose I/O interface corresponds to a specific
I/O standard. |
| ibufds |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_blvds_25 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_diff_out |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_ldt_25 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvds_25 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvds_25_dci |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvds_33 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvds_33_dci |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvdsext_25 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvdsext_25_dci |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvdsext_33 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvdsext_33_dci |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvpecl_25 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_lvpecl_33 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufds_ulvds_25 |
IBUFDS is an input buffer that supports low-voltage, differential
signaling. |
| ibufg |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_agp |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_ctt |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_gtl |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_gtlp |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_hstl_i |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_hstl_iii |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_hstl_iv |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_lvcmos2 |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_lvttl |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_pci33_3 |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_pci33_5 |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_pci66_3 |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_sstl2_i |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_sstl2_ii |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_sstl3_i |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_sstl3_ii |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufgds |
IBUFGDS is a dedicated differential signaling input buffer for
connection to the clock buffer (BUFG) or DCM. |
| ibufgds_lvds_25 |
IBUFGDS is a dedicated differential signaling input buffer for
connection to the clock buffer (BUFG) or DCM. |
| ibufgds_lvdsext_25 |
IBUFGDS is a dedicated differential signaling input buffer for
connection to the clock buffer (BUFG) or DCM. |
| icap_virtex2 |
|
| ifd |
The IFD D-type flip-flop is contained in an input/output block
(IOB). |
| ifd_1 |
The IFD_1 D-type flip-flop is contained in an input/output block
(IOB) except for XC5200. |
| ifddrcpe |
IFDDRCPE is a dual data rate (DDR) input D flip-flop with clock
enable (CE) and asynchronous preset (PRE) and clear (CLR). |
| ifddrrse |
FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate
clocks (C0 and C1) phase shifted 180 degrees that allow selection
of two separate data inputs (D0 and D1). |
| ifdi |
The IFDI D-type flip-flop is contained in an input/output block
(IOB). |
| ifdi_1 |
The IFDI_1 D-type flip-flop is contained in an input/output block
(IOB). |
| ifdx |
The IFDX D-type flip-flop is contained in an input/output block
(IOB). |
| ifdxi |
The IFDXI D-type flip-flop is contained in an input/output block
(IOB). |
| ildx_1 |
ILDX_1 is a transparent data latch, which can be used to hold
transient data entering a chip. |
| ildxi_1 |
ILDXI_1 is a transparent data latch, which can hold transient data
entering a chip. |
| inv |
The INV cell is an asynchronous inverter. |
| inv_g |
The INV_G is a generic-width inverter cell. |
| iobuf |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_agp |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_ctt |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_f_12 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_f_16 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_f_2 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_f_24 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_f_4 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_f_6 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_f_8 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_gtl |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_gtlp |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_hstl_i |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_hstl_iii |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_hstl_iv |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_lvcmos2 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_pci33_3 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_pci33_5 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_pci66_3 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_s_12 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_s_16 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_s_2 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_s_24 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_s_4 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_s_6 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_s_8 |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_sstl2_i |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_sstl2_ii |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_sstl2_ii_dci |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_sstl3_i |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobuf_sstl3_ii |
IOBUF and its variants (listed below) are bi-directional buffers
whose I/O interface corresponds to a specific I/O standard.The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the
standard. |
| iobufds |
|
| iopad |
Deprecated. iopads are not necessary. |
| ipad |
Deprecated. ipads are not necessary. |
| ipad_sim |
Deprecated. ipads are not necessary. |
| keeper |
|
| ld |
LD is a transparent data latch. |
| ld_1 |
LD_1 is a transparent data latch with an inverted gate. |
| ldc |
LDC is a transparent data latch with asynchronous clear. |
| ldc_1 |
LDC_1 is a transparent data latch with asynchronous clear and
inverted gate. |
| ldce |
LDCE is a transparent data latch with asynchronous clear and gate
enable. |
| ldce_1 |
LDCE_1 is a transparent data latch with asynchronous clear, gate
enable, and inverted gate. |
| ldcp |
LDCP is a transparent data latch with data (D), asynchronous clear
(CLR) and preset (PRE) inputs. |
| ldcp_1 |
LDCP_1 is a transparent data latch with data (D), asynchronous
clear (CLR) and preset (PRE) inputs. |
| ldcpe |
LDCPE is a transparent data latch with data (D), asynchronous
clear (CLR), asynchronous preset (PRE), and gate enable (GE). |
| ldcpe_1 |
LDCPE is a transparent data latch with data (D), asynchronous
clear (CLR), asynchronous preset (PRE), and gate enable (GE). |
| lde |
LDE is a transparent data latch with data (D) and gate enable (GE)
inputs. |
| lde_1 |
LDE_1 is a transparent data latch with data (D) and gate enable
(GE) inputs. |
| ldp |
LDP is a transparent data latch with asynchronous preset
(PRE). |
| ldp_1 |
LDP_1 is a transparent data latch with asynchronous preset
(PRE). |
| ldpe |
LDPE is a transparent data latch with asynchronous preset and gate
enable. |
| ldpe_1 |
LDPE_1 is a transparent data latch with asynchronous preset, gate
enable, and inverted gated. |
| lut1 |
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and
4-bit look-up-tables (LUTs) with general output (O). |
| lut1_d |
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-,
and 4-bit look-up-tables (LUTs) with two functionally identical
outputs, O and LO. |
| lut1_l |
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-,
and 4- bit look-up-tables (LUTs) with a local output (LO) that is
used to connect to another output within the same CLB slice and to
the fast connect buffer. |
| lut2 |
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and
4-bit look-up-tables (LUTs) with general output (O). |
| lut2_d |
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-,
and 4-bit look-up-tables (LUTs) with two functionally identical
outputs, O and LO. |
| lut2_l |
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-,
and 4- bit look-up-tables (LUTs) with a local output (LO) that is
used to connect to another output within the same CLB slice and to
the fast connect buffer. |
| lut3 |
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and
4-bit look-up-tables (LUTs) with general output (O). |
| lut3_d |
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-,
and 4-bit look-up-tables (LUTs) with two functionally identical
outputs, O and LO. |
| lut3_l |
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-,
and 4- bit look-up-tables (LUTs) with a local output (LO) that is
used to connect to another output within the same CLB slice and to
the fast connect buffer. |
| lut4 |
LUT4 is a 4-bit look-up-table (LUT) with general output (O). |
| lut4_d |
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-,
and 4-bit look-up-tables (LUTs) with two functionally identical
outputs, O and LO. |
| lut4_l |
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-,
and 4- bit look-up-tables (LUTs) with a local output (LO) that is
used to connect to another output within the same CLB slice and to
the fast connect buffer. |
| m2_1 |
The M2_1 multiplexer chooses one data bit from two sources (D1 or
D0) under the control of the select input (S0). |
| m2_1_g |
The M2_1 multiplexer is a generic-width 2:1 multiplexer. |
| mult_and |
MULT_AND is an AND component used exclusively for building fast
and smaller multipliers. |
| mult18x18 |
MULT18X18 is a combinational signed 18-bit by 18-bit multiplier. |
| mult18x18s |
MULT18X18S is a signed 18-bit by 18-bit multiplier
with output registered. |
| muxcy |
MUXCY is used to implement a 1-bit high-speed carry propagate
function. |
| muxcy_d |
MUXCY_D is used to implement a 1-bit high-speed carry propagate
function. |
| muxcy_l |
MUXCY_L is used to implement a 1-bit high-speed carry propagate
function. |
| muxf5 |
MUXF5 provides a multiplexer function in one half of a Virtex2 CLB
for creating a function-of-5 lookup table or a 4-to-1 multiplexer
in combination with the associated lookup tables. |
| muxf5_d |
MUXF5_D provides a multiplexer function in one half of a Virtex2 or
Spartan2 CLB for creating a function-of-5 lookup table or a 4-to-1
multiplexer in combination with the associated lookup tables. |
| muxf5_l |
MUXF5_L provides a multiplexer function in one half of a Virtex2 or
Spartan2 CLB for creating a function-of-5 lookup table or a 4-to-1
multiplexer in combination with the associated lookup tables. |
| muxf6 |
MUXF6 provides a multiplexer function in a full Virtex2 CLB for
creating a function-of-6 lookup table or an 8-to-1 multiplexer in
combination with the associated four lookup tables and two
MUXF5s. |
| muxf6_d |
MUXF6_D provides a multiplexer function in a full Virtex2 or
Spartan2 CLB for creating a function-of-6 lookup table or an
8-to-1 multiplexer in combination with the associated four lookup
tables and two MUXF5s. |
| muxf6_l |
MUXF6_L provides a multiplexer function in a full Virtex or
Spartan-II CLB or one half of a Virtex-II CLB (two slices) for
creating a function-of-6 lookup table or an 8-to-1 multiplexer
in combination with the associated four lookup tables and two MUXF5s. |
| muxf7 |
MUXF7 provides a multiplexer function in a full Virtex-II CLB for
creating a function-of-7 lookup table or a 16-to-1 multiplexer in
combination with the associated lookup tables. |
| muxf7_d |
MUXF7_D provides a multiplexer function in one full Virtex-II CLB
for creating a function-of-7 lookup table or a 16-to-1 multiplexer
in combination with the associated lookup tables. |
| muxf7_l |
MUXF7_L provides a multiplexer function in a full Virtex-II CLB
for creating a func-tion- of-7 lookup table or a 16-to-1 multiplexer
in combination with the associated lookup tables. |
| muxf8 |
MUXF8 provides a multiplexer function in two full Virtex-II CLBs
for creating a func-tion- of-7 lookup table or a 32-to-1 multiplexer
in combination with the associated lookup tables and two MUXF8s. |
| muxf8_d |
MUXF8_D provides a multiplexer function in two full Virtex-II CLBs
for creating a function-of-8 lookup table or a 32-to-1 multiplexer
in combination with the associated four lookup tables and two MUXF8s. |
| muxf8_l |
MUXF8_L provides a multiplexer function in two full Virtex-II CLBs
for creating a function-of-8 lookup table or a 32-to-1 multiplexer
in combination with the associated four lookup tables and two MUXF8s. |
| nand2 |
This class implements and asynchronous 2-input nand gate. |
| nand2_g |
This class implements and asynchronous 2-input nand gate. |
| nand2b1 |
This class implements and asynchronous 2-input nand gate. |
| nand2b2 |
This class implements and asynchronous 2-input nand gate. |
| nand3 |
This class implements and asynchronous 3-input nand gate. |
| nand3_g |
This class implements and asynchronous 3-input nand gate. |
| nand3b1 |
This class implements and asynchronous 3-input nand gate. |
| nand3b2 |
This class implements and asynchronous 3-input nand gate. |
| nand3b3 |
This class implements and asynchronous 3-input nand gate. |
| nand4 |
This class implements and asynchronous 4-input nand gate. |
| nand4_g |
This class implements and asynchronous 4-input nand gate. |
| nand4b1 |
This class implements and asynchronous 4-input nand gate. |
| nand4b2 |
This class implements and asynchronous 4-input nand gate. |
| nand4b3 |
This class implements and asynchronous 4-input nand gate. |
| nand4b4 |
This class implements and asynchronous 4-input nand gate. |
| nand5 |
This class implements and asynchronous 5-input nand gate. |
| nand6 |
This class implements and asynchronous 6-input nand gate. |
| nand7 |
This class implements and asynchronous 7-input nand gate. |
| nand8 |
This class implements and asynchronous 8-input nand gate. |
| nand9 |
This class implements and asynchronous 9-input nand gate. |
| nandX |
This class implements an NAND gate with arbitrary number of inputs. |
| nandX_g |
|
| NetworkWireList |
|
| nor2 |
This class implements and asynchronous 2-input nor gate. |
| nor2_g |
This class implements and asynchronous 2-input nor gate. |
| nor2b1 |
This class implements and asynchronous 2-input nor gate. |
| nor2b2 |
This class implements and asynchronous 2-input nor gate. |
| nor3 |
This class implements and asynchronous 3-input nor gate. |
| nor3_g |
This class implements and asynchronous 3-input nor gate. |
| nor3b1 |
This class implements and asynchronous 3-input nor gate. |
| nor3b2 |
This class implements and asynchronous 3-input nor gate. |
| nor3b3 |
This class implements and asynchronous 3-input nor gate. |
| nor4 |
This class implements and asynchronous 4-input nor gate. |
| nor4_g |
This class implements and asynchronous 4-input nor gate. |
| nor4b1 |
This class implements and asynchronous 4-input nor gate. |
| nor4b2 |
This class implements and asynchronous 4-input nor gate. |
| nor4b3 |
This class implements and asynchronous 4-input nor gate. |
| nor4b4 |
This class implements and asynchronous 4-input nor gate. |
| nor5 |
This class implements and asynchronous 5-input nor gate. |
| nor6 |
This class implements and asynchronous 6-input nor gate. |
| nor7 |
This class implements and asynchronous 7-input nor gate. |
| nor8 |
This class implements and asynchronous 8-input nor gate. |
| nor9 |
This class implements and asynchronous 9-input nor gate. |
| norX |
This class implements an NOR gate with arbitrary number of inputs. |
| norX_g |
|
| obuf |
OBUF is a single output buffer. |
| obuf_agp |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_ann |
OBUF is a single output buffer. |
| obuf_ctt |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_f_12 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_f_16 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_f_2 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_f_24 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_f_4 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_f_6 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_f_8 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_g |
OBUF is a single output buffer. |
| obuf_gtl |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_gtlp |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_hstl_i |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_hstl_iii |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_hstl_iv |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_lvcmos2 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_lvttl_f_12 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_pci33_3 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_pci33_5 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_pci66_3 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_s_12 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_s_16 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_s_2 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_s_24 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_s_4 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_s_6 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_s_8 |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_sstl2_i |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_sstl2_i_dci |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_sstl2_ii |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_sstl3_i |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obuf_sstl3_ii |
OBUF and its variants (listed below) are single output buffers
whose I/O interface corresponds to a specific I/O standard. |
| obufds |
OBUFDS is a single output buffer that supports low-voltage,
differential signaling (1.8v CMOS). |
| obufds_lvds_25 |
OBUFDS is a single output buffer that supports low-voltage,
differential signaling (1.8v CMOS). |
| obufds_lvdsext_25 |
OBUFDS is a single output buffer that supports low-voltage,
differential signaling (1.8v CMOS). |
| obuft |
OBUFT is a single 3-state output buffer with active-low enable. |
| obuft_agp |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_ctt |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_f_12 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_f_16 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_f_2 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_f_24 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_f_4 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_f_6 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_f_8 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_g |
OBUFT is a single 3-state output buffer with active-low enable. |
| obuft_gtl |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_gtlp |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_hstl_i |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_hstl_iii |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_hstl_iv |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_lvcmos2 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_pci33_3 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_pci33_5 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_pci66_3 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_s_12 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_s_16 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_s_2 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_s_24 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_s_4 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_s_6 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_s_8 |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_sstl2_i |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_sstl2_i_dci |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_sstl2_ii |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_sstl3_i |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuft_sstl3_ii |
OBUFT and its variants (listed below) are single 3-state output
buffers with active-Low output Enable whose I/O interface
corresponds to a specific I/O standard. |
| obuftds |
OBUFTDS is a single 3-state, differential signaling output buffer with
active Low enable and a selectIO interface. |
| ofd |
OFD, OFD4, OFD8, and OFD16 are single and multiple output D
flip-flops except for XC5200 and XC9000. |
| ofddrcpe |
OFDDRCPE is a dual data rate (DDR) output D flip-flop with clock
enable (CE) and asynchronous preset (PRE) and clear (CLR). |
| ofddrrse |
OFDDRRSE is a dual data rate (DDR) output D flip-flop with synchronous
reset (R) and set (S) and clock enable (CE). |
| ofddrtcpe |
OFDDRTCPE is a dual data rate (DDR) D flip-flop with clock enable
(CE) and asynchronous preset and clear whose output is enabled by
a 3-state buffer. |
| ofddrtrse |
OFDDRTRSE is a dual data rate (DDR) D flip-flop with clock enable
(CE) and synchronous reset and set whose output is enabled by a
3-state buffer. |
| ofde |
OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops
whose outputs are enabled by tristate buffers. |
| ofdi |
OFDI is contained in an input/output block (IOB). |
| ofdt |
OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops
whose outputs are enabled by a tristate buffers. |
| ofdtx |
OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D
flip-flops whose outputs are enabled by a tristate buffers. |
| ofdtxi |
OFDTXI and its output buffer are contained in an input/output
block (IOB). |
| ofdx |
OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D
flip-flops. |
| ofdxi |
OFDXI is contained in an input/output block (IOB). |
| opad |
Deprecated. ipads are not necessary. |
| opad_sim |
Deprecated. ipads are not necessary. |
| or2 |
This class implements and asynchronous 2-input or gate. |
| or2_g |
This class implements and asynchronous 2-input or gate. |
| or2b1 |
This class implements and asynchronous 2-input or gate. |
| or2b2 |
This class implements and asynchronous 2-input or gate. |
| or3 |
This class implements and asynchronous 3-input or gate. |
| or3_g |
This class implements and asynchronous 3-input or gate. |
| or3b1 |
This class implements and asynchronous 3-input or gate. |
| or3b2 |
This class implements and asynchronous 3-input or gate. |
| or3b3 |
This class implements and asynchronous 3-input or gate. |
| or4 |
This class implements and asynchronous 4-input or gate. |
| or4_g |
This class implements and asynchronous 4-input or gate. |
| or4b1 |
This class implements and asynchronous 4-input or gate. |
| or4b2 |
This class implements and asynchronous 4-input or gate. |
| or4b3 |
This class implements and asynchronous 4-input or gate. |
| or4b4 |
This class implements and asynchronous 4-input or gate. |
| or5 |
This class implements and asynchronous 5-input or gate. |
| or6 |
This class implements and asynchronous 6-input or gate. |
| or7 |
This class implements and asynchronous 7-input or gate. |
| or8 |
This class implements and asynchronous 8-input or gate. |
| or9 |
This class implements and asynchronous 9-input or gate. |
| orcy |
ORCY is a special OR with general O output used for generating
faster and smaller arithmetic functions. |
| orX |
This class implements an OR gate with arbitrary number of inputs. |
| orX_g |
|
| pulldown |
PULLDOWN resistor elements are available in each XC4000
Input/Output Block (IOB). |
| pulldown_g |
The PULLDOWN_G is a generic-width pulldown resistor cell. |
| pullup |
The pull-up element establishes a High logic level for open-drain
elements and macros (DECODE, WAND, WORAND) or 3-state nodes (TBUF)
when all the drivers are off. |
| pullup_g |
The PULLUP_G is a generic-width pullup resistor cell. |
| ram128x1s |
RAM128X1S is a 128-word by 1-bit static random access memory with
synchronous write capability. |
| ram128x1s_1 |
RAM128X1S_1 is a 64-word by 1-bit static random access memory
with synchronous write capability. |
| ram16x1d |
RAM16X1D is a 16-word by 1-bit static dual-ported RAM. |
| ram16x1d_1 |
RAM16X1D_1 is a 16-word by 1-bit static dual port random access
memory with synchronous write capability and negative-edge clock. |
| ram16x1s |
RAM16X1S is a synchronous 16-word by 1-bit static RAM. |
| ram16x1s_1 |
RAM16X1S_1 is a 16-word by 1-bit static random access memory
with synchronous write capability and negative-edge clock. |
| ram16x2d |
RAM16X2D is a 16-word by 2-bit static dual-ported RAM. |
| ram16x2s |
RAM16X2S is a synchronous 16-word by 2-bit static RAM. |
| ram16x4d |
RAM16X4D is a 16-word by 4-bit static dual-ported RAM. |
| ram16x4s |
RAM16X4S is a synchronous 16-word by 4-bit static RAM. |
| ram16x8d |
RAM16X8D is a 16-word by 8-bit static dual-ported RAM. |
| ram16x8s |
RAM16X8S is a 16-word by 8-bit static random access memory with
synchronous write capability. |
| ram32x1d |
RAM32X1D is a 32-word by 1-bit static dual port random access
memory with synchronous write capability and a positive-edge clock. |
| ram32x1d_1 |
RAM32X1D_1 is a 32-word by 1-bit static dual port random access
memory with synchronous write capability and a negative-edge clock. |
| ram32x1s |
RAM32X1S is a synchronous 32-word by 1-bit static RAM. |
| ram32x1s_1 |
RAM32X1S_1 is a 32-word by 1-bit static random access memory with
synchronous write capability. |
| ram32x1s_ack |
|
| ram32x2s |
RAM32X2S is a synchronous 32-word by 2-bit static RAM. |
| ram32x4s |
RAM32X4S is a synchronous 32-word by 4-bit static RAM. |
| ram32x8s |
RAM32X8S is a synchronous 32-word by 8-bit static RAM. |
| ram64x1d |
RAM64X1D is a 64-word by 1-bit static dual port random access
memory with synchronous write capability and a positive-edge clock. |
| ram64x1d_1 |
RAM64X1D_1 is a 64-word by 1-bit static dual port random access
memory with synchronous write capability and a negative-edge clock. |
| ram64x1s |
RAM64X1S is a 64-word by 1-bit static random access memory with
synchronous write capability. |
| ram64x1s_1 |
RAM64X1S_1 is a 64-word by 1-bit static random access memory with
synchronous write capability and a negative-edge clock. |
| ram64x2s |
RAM64X2S is a 64-word by 2-bit static random access memory with
synchronous write capability. |
| RAMB16_S |
This class provides the functionality of the RAMB16_Sn Virtex2
library elements - The Single-ported BlockRams. |
| RAMB16_S_S |
This class provides the functionality of the RAMB16_Sn_Sn Virtex2
library elements - The Dual-ported BlockRams. |
| RAMB16Dual |
Deprecated. Use RAMB16_S_S instead. |
| RAMB16DualNoParity |
Deprecated. Use RAMB16_S_S instead. |
| RAMB16DualParity |
Deprecated. Use RAMB16_S_S instead. |
| RAMB16DualParityB |
Deprecated. Use RAMB16_S_S instead. |
| RAMB16Single |
Deprecated. Use RAMB16_S instead. |
| RAMB16SingleNoParity |
Deprecated. Use RAMB16_S instead. |
| RAMB16SingleParity |
Deprecated. Use RAMB16_S instead. |
| roc |
|
| rocbuf |
|
| rom128x1 |
ROM128X1 is a 128-word by 1-bit ROM. |
| Rom128x1View |
This class is for the simulation of block ram's to work correctly. |
| rom16x1 |
ROM16X1 is a 16-word by 1-bit ROM. |
| rom256x1 |
ROM256X1 is a 256-word by 1-bit ROM. |
| Rom256x1View |
This class is for the simulation of block ram's to work correctly. |
| rom32x1 |
ROM32X1 is a 32-word by 1-bit ROM. |
| rom64x1 |
ROM64X1 is a 64-word by 1-bit ROM. |
| Rom64x1View |
This class is for the simulation of block ram's to work correctly. |
| SimulationBuffer |
|
| srl16 |
SRL16 is a shift register look up table (LUT). |
| srl16_1 |
SRL16_1 is a shift register look up table (LUT). |
| srl16e |
SRL16E is a shift register look up table (LUT). |
| srl16e_1 |
SRL16E_1 is a shift register look up table (LUT). |
| srlc16 |
SRLC16 is a shift register look up table (LUT). |
| srlc16_1 |
SRLC16_1 is a shift register look up table (LUT). |
| srlc16e |
SRLC16E is a shift register look up table (LUT) with carry, clock
enable, and asynchro-nous clear. |
| srlc16e_1 |
SRLC16E_1 is a shift register look up table (LUT). |
| startbuf_architecture |
|
| startup_virtex2 |
The STARTUP_VIRTEX2 primitive is used for Global Set/Reset, global
3-state control, and the user configuration clock. |
| TESTVirtex2Library |
This class is the self-test controller for the Virtex2 library. |
| TMCellList |
|
| toc |
|
| tocbuf |
|
| upad |
A UPAD allows the use of any unbonded IOBs in a device. |
| vcc |
This class is the VCC cell for the Xilinx tools as well as
for JHDL simulation. |
| Virtex2LibrarySelfTester |
This class is the self-test controller for the Virtex2 library. |
| Virtex2PlacementInfo |
|
| Virtex2TechMapper |
This is the tech-mapper for the Virtex2 library. |
| xnor2 |
This class implements and asynchronous 2-input xnor gate. |
| xnor2_g |
This class implements and asynchronous 2-input xnor gate. |
| xnor3 |
This class implements and asynchronous 3-input xnor gate. |
| xnor3_g |
This class implements and asynchronous 3-input xnor gate. |
| xnor4 |
This class implements and asynchronous 4-input xnor gate. |
| xnor4_g |
This class implements and asynchronous 4-input xnor gate. |
| xnor5 |
This class implements and asynchronous 5-input xnor gate. |
| xnor6 |
This class implements and asynchronous 6-input xnor gate. |
| xnor7 |
This class implements and asynchronous 7-input xnor gate. |
| xnor8 |
This class implements and asynchronous 8-input xnor gate. |
| xnor9 |
This class implements and asynchronous 9-input xnor gate. |
| xnorX |
This class implements an XNOR gate with arbitrary number of inputs. |
| xor2 |
This class implements and asynchronous 2-input xor gate. |
| xor2_g |
This class implements and asynchronous 2-input xor gate. |
| xor3 |
This class implements and asynchronous 3-input xor gate. |
| xor3_g |
This class implements and asynchronous 3-input xor gate. |
| xor4 |
This class implements and asynchronous 4-input xor gate. |
| xor4_g |
This class implements and asynchronous 4-input xor gate. |
| xor5 |
This class implements and asynchronous 5-input xor gate. |
| xor6 |
This class implements and asynchronous 6-input xor gate. |
| xor7 |
This class implements and asynchronous 7-input xor gate. |
| xor8 |
This class implements and asynchronous 8-input xor gate. |
| xor9 |
This class implements and asynchronous 9-input xor gate. |
| xorcy |
XORCY is a special XOR with general O output used for generating
faster and smaller arithmetic functions. |
| xorcy_d |
XORCY_D is a special XOR used for generating faster and smaller
arithmetic functions. |
| xorcy_l |
XORCY_L is a special XOR with general O output used for generating
faster and smaller arithmetic functions. |
| xorX |
This class implements an XOR gate with arbitrary number of inputs. |
| Xwire |
This class subclasses the class byucc.jhdl.Xilinx.Xwire. |