byucc.jhdl.Xilinx.Virtex2
Class RAMB16DualParityB

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.Xilinx.Virtex2.RAMB16
                                  byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

All Implemented Interfaces:

BooleanFlags, Checkpointable, Clockable, LargeExternallyUpdateable, byucc.jhdl.base.Propagateable, TreeListable

Deprecated. Use RAMB16_S_S instead.

public class RAMB16DualParityB

extends byucc.jhdl.Xilinx.Virtex2.RAMB16

implements LargeExternallyUpdateable, Checkpointable

This class provides the functionality of the RAMB16_Sn_Sn Virtex2 dual ported block ram, with the special case of port B having a parity port, while A does not. This class has been deprecated. Do not instantiate this class directly. Use the RAMB16Dual wrapper class instead.

Field Summary

static CellInterface[]	cell_interface Deprecated.
protected int[]	contents Deprecated.
static CellInterface[]	implicit_interface Deprecated.

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

RAMB16DualParityB(Node parent, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB)
Deprecated. Constructs a new dual-ported Block RAM with parity port.

RAMB16DualParityB(Node parent, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, int[] contents)
Deprecated. Constructs a new dual-ported Block RAM with parity port.

RAMB16DualParityB(Node parent, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, int[] contents, java.lang.String name)
Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node parent, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, java.lang.String name)
Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node parent, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, java.lang.String[] contents)
Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParityB(Node parent, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, java.lang.String[] contents, java.lang.String name)
Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node parent, Wire clkA, Wire clkB, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB)
Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node parent, Wire clkA, Wire clkB, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, int[] contents)
Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node parent, Wire clkA, Wire clkB, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, int[] contents, java.lang.String name)
Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualParityB(Node parent, Wire clkA, Wire clkB, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, java.lang.String name)
Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node parent, Wire clkA, Wire clkB, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, java.lang.String[] contents)
Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node parent, Wire clkA, Wire clkB, Wire ssrA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire ssrB, Wire enB, Wire diB, Wire dipB, Wire weB, Wire addrB, Wire doB, Wire dopB, java.lang.String[] contents, java.lang.String name)
Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

Method Summary

protected void	addMyProperties() Deprecated.
protected void	addMyProperties(java.lang.String[] properties) Deprecated.
protected void	addParityProperties() Deprecated.
protected void	addParityProperties(java.lang.String[] properties) Deprecated.
boolean	cellInterfaceDeterminesUniqueNetlistStructure() Deprecated. When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.
protected void	connectImplicitPorts() Deprecated. Connects the implicit ports.
protected boolean	defaultSimulationModelIsBehavioral() Deprecated. The default simulation model is structural for Structural cells.
int[]	fetchState() Deprecated. This method is used to fetch the current state of the Cell.
java.lang.String	getCellName() Deprecated. Access the cell name associated with a derived class.
java.io.Serializable	getData() Deprecated. Called by the checkpointing code to get all of the data that should be checkpointed.
protected java.lang.String[]	InitializeContents(int[] array, int width) Deprecated. This method is called from RAMB16_S and RAMB16_S_S and is used to initialize the contents array.
protected java.lang.String[]	InitializeParity(int[] array, int width) Deprecated.
protected java.lang.String[]	IntArrayToPropertyStrings(int[] array) Deprecated.
boolean	isNetlistLeaf() Deprecated. A few rare cells are leafCells during netlisting, but not during simulation.
protected int[]	PropertyStringsToIntArray(java.lang.String[] pstr) Deprecated.
void	setData(java.io.Serializable data) Deprecated. This is called on a checkpoint restore, and the object checkpointed out is passed back in.
void	updateState(int[] update_value) Deprecated. This method is used to update the state of the Cell in simulator.

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clock, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagate, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, reset, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

implicit_interface

public static CellInterface[] implicit_interface

Deprecated.

cell_interface

public static CellInterface[] cell_interface

Deprecated.

contents

protected int[] contents

Deprecated.

Constructor Detail

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB)

Deprecated.

Constructs a new dual-ported Block RAM with parity port.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         int[] contents)

Deprecated.

Constructs a new dual-ported Block RAM with parity port.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

contents - An int[] representing the contents of the entire BlockRam.

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         int[] contents,
                         java.lang.String name)

Deprecated.

Constructs a new named, dual-ported Block RAM with parity port.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

contents - An int[] representing the contents of the entire BlockRam.

name - Instance name of the RAMB16DualParityB

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         java.lang.String name)

Deprecated.

Constructs a new named, dual-ported Block RAM with parity port.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

name - Instance name of the RAMB16DualParityB

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         java.lang.String[] contents,
                         java.lang.String name)

Deprecated.

Constructs a new named, dual-ported Block RAM with parity port.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

contents - An String[] representing the contents of the entire BlockRam, each string containing the init string that corresponds to the INIT_00 ... INIT_3F properties.

name - Instance name of the RAMB16DualParityB

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         java.lang.String[] contents)

Deprecated.

Constructs a new named, dual-ported Block RAM with dual parity ports.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

contents - An String[] representing the contents of the entire BlockRam, each string containing the init string that corresponds to the INIT_00 ... INIT_3F properties.

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire clkA,
                         Wire clkB,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB)

Deprecated.

Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

clkA - The Wire to be connected to clock port clkA

clkB - The Wire to be connected to clock port clkB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire clkA,
                         Wire clkB,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         java.lang.String name)

Deprecated.

Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

clkA - The Wire to be connected to clock port clkA

clkB - The Wire to be connected to clock port clkB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

name - Instance name of the RAMB16DualParityB

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire clkA,
                         Wire clkB,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         java.lang.String[] contents)

Deprecated.

Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

clkA - The Wire to be connected to clock port clkA

clkB - The Wire to be connected to clock port clkB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

contents - An String[] representing the contents of the entire BlockRam, each string containing the init string that corresponds to the INIT_00 ... INIT_3F properties.

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire clkA,
                         Wire clkB,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         java.lang.String[] contents,
                         java.lang.String name)

Deprecated.

Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

clkA - The Wire to be connected to clock port clkA

clkB - The Wire to be connected to clock port clkB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

contents - An String[] representing the contents of the entire BlockRam, each string containing the init string that corresponds to the INIT_00 ... INIT_3F properties.

name - Instance name of the RAMB16DualParityB

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire clkA,
                         Wire clkB,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         int[] contents)

Deprecated.

Constructs a new named, dual-ported, multi-clock Block RAM with dual parity ports.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

clkA - The Wire to be connected to clock port clkA

clkB - The Wire to be connected to clock port clkB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

contents - An int[] representing the contents of the entire BlockRam.

RAMB16DualParityB

public RAMB16DualParityB(Node parent,
                         Wire clkA,
                         Wire clkB,
                         Wire ssrA,
                         Wire enA,
                         Wire diA,
                         Wire weA,
                         Wire addrA,
                         Wire doA,
                         Wire ssrB,
                         Wire enB,
                         Wire diB,
                         Wire dipB,
                         Wire weB,
                         Wire addrB,
                         Wire doB,
                         Wire dopB,
                         int[] contents,
                         java.lang.String name)

Deprecated.

Constructs a new named, dual-ported, multi-clock Block RAM.

Parameters:

parent - The parent Cell to the RAMB16DualParityB

clkA - The Wire to be connected to clock port clkA

clkB - The Wire to be connected to clock port clkB

ssrA - The Wire to be connected to input port ssrA

enA - The Wire to be connected to input port enA

diA - The Wire to be connected to input port diA

weA - The Wire to be connected to input port weA

addrA - The Wire to be connected to input port addrA

doA - The Wire to be connected to output port doA

ssrB - The Wire to be connected to input port ssrB

enB - The Wire to be connected to input port enB

diB - The Wire to be connected to input port diB

dipB - The Wire to be connected to input port dipB

weB - The Wire to be connected to input port weB

addrB - The Wire to be connected to input port addrB

doB - The Wire to be connected to output port doB

dopB - The Wire to be connected to output port dopB

contents - An int[] representing the contents of the entire BlockRam.

name - Instance name of the RAMB16DualParityB

Method Detail

connectImplicitPorts

protected void connectImplicitPorts()

Deprecated.

Description copied from class: Logic

Connects the implicit ports. Override this if you shadow #implicit_ports. If you used the old version of connect_implicit_ports, this method will use reflection to see that the old version gets called correctly.

Overrides:

connectImplicitPorts in class Logic

getCellName

public java.lang.String getCellName()

Deprecated.

Description copied from class: Cell

Access the cell name associated with a derived class. The cellname field is lazily evaluated on the first call of this method. Can be overriden to make cellname different by instance. If the field does not exist, this defaults to the classname.

Overrides:

getCellName in class Cell

Returns:

the cell name associated with a derived class, null if not declared.

isNetlistLeaf

public boolean isNetlistLeaf()

Deprecated.

Description copied from class: Cell

A few rare cells are leafCells during netlisting, but not during simulation. Overriding this method should allow that behavior.

Overrides:

isNetlistLeaf in class Cell

Returns:

true is this cell is a leaf during netlisting, false otherwise.

cellInterfaceDeterminesUniqueNetlistStructure

public final boolean cellInterfaceDeterminesUniqueNetlistStructure()

Deprecated.

Description copied from class: Cell

When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. Overriding this method to return true allows JHDL to save memory and netlists to be smaller by sharing the netlist structures that are guaranteed to be identical. NOTE: Do not override this unless every possible condition responsible for structural differences in a class (types and amount of children cells created, and arrangements of wires connected to ports) is included in the cellInterface[] of that class.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

false if not overridden, preventing all memory sharing

defaultSimulationModelIsBehavioral

protected boolean defaultSimulationModelIsBehavioral()

Deprecated.

Description copied from class: Structural

The default simulation model is structural for Structural cells. If the default should be behavioral, the user will need to overload this method to return true in cases besides TestBenches or leaf cells.

Overrides:

defaultSimulationModelIsBehavioral in class Structural

Returns:

true if TestBench or leafCell, false otherwise.

updateState

public void updateState(int[] update_value)

Deprecated.

Description copied from interface: LargeExternallyUpdateable

This method is used to update the state of the Cell in simulator.

Specified by:

updateState in interface LargeExternallyUpdateable

Parameters:

update_value - the state to update to

fetchState

public int[] fetchState()

Deprecated.

Description copied from interface: LargeExternallyUpdateable

This method is used to fetch the current state of the Cell.

Specified by:

fetchState in interface LargeExternallyUpdateable

Returns:

the current state

getData

public java.io.Serializable getData()

Deprecated.

Description copied from interface: Checkpointable

Called by the checkpointing code to get all of the data that should be checkpointed. The data in the object returned should include all literal values last "put" onto all output wires, and any internal state that must be saved

Specified by:

getData in interface Checkpointable

Returns:

all state to be saved

setData

public void setData(java.io.Serializable data)

Deprecated.

Description copied from interface: Checkpointable

This is called on a checkpoint restore, and the object checkpointed out is passed back in. In this function it is the responsibility of the circuit to do "put"s on all output wires using the *literal* (non-calculated) values checkpointed.

Specified by:

setData in interface Checkpointable

Parameters:

data - the state that was saved earlier

InitializeContents

protected java.lang.String[] InitializeContents(int[] array,
                                                int width)

Deprecated.

This method is called from RAMB16_S and RAMB16_S_S and is used to initialize the contents array. The array should should be an int array and should no longer be packed. Each element of the array corresponds to the associated address in the BlockRam, regardless of data-width. For example, contents[3] corresponds to addr 3. Data width is a parameter to ensure correct operation.

InitializeParity

protected java.lang.String[] InitializeParity(int[] array,
                                              int width)

Deprecated.

PropertyStringsToIntArray

protected int[] PropertyStringsToIntArray(java.lang.String[] pstr)

Deprecated.

IntArrayToPropertyStrings

protected java.lang.String[] IntArrayToPropertyStrings(int[] array)

Deprecated.

addMyProperties

protected void addMyProperties()

Deprecated.

addParityProperties

protected void addParityProperties()

Deprecated.

addMyProperties

protected void addMyProperties(java.lang.String[] properties)

Deprecated.

addParityProperties

protected void addParityProperties(java.lang.String[] properties)

Deprecated.