byucc.jhdl.Logic
Class Logic

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic

All Implemented Interfaces:

BooleanFlags, Clockable, byucc.jhdl.base.Propagateable, TreeListable

Direct Known Subclasses:

accum, accum, Add, ADD_F_CI, ADD_FG_CI, ADD_G_F1, AddPass, AddPass, AddPassGeneric, AddPassVirtex, AddPassXC4000, ADDSUB_F_CI, ADDSUB_FG_CI, ADDSUB_G_F1, ADDSUB_G_F3_, Adsu, Adsu, adsuovf1, adsuovf16, Algorithm, arrayMult, arrayMult, arrayMult, arrayMult, arrayMult, BarrelShiftL, BarrelShiftR, BasicMemory, BlockRam, BlockRamView, BlockRamView, BlockRamView, BlockRamViewL, BlockRamViewParity, booth, booth, booth, booth, booth, bram_1k, bram_4k, brir, bscan_virtex2, bufgce, bufgce_1, BuildJHDL, Calculator, carryLogic, char_fsm2, char_slice2, charcomp2, clkdll, clkdllhf, Col_reg, Col_reg, COMPARATORS, Constant, Constant, control, Cordic, Cordic, Cordic_ctrl, Cordic_ctrl, Cordicl, Cordicl_ctrl, CordicRP, CORDICS, counter, COUNTERS, CSRCCL, CSRCFD, datapath, DBone, dec16, Decoder, DECODERS, delay, delay, delay, delay, DelayS, DesignRuleCheckerTester, DesktopTest, DESLogic, DIVIDERS, downcnt, downcnt, downcnt, downcnt, downcnt, DPSR, DS_FIR, DS_FIR_module, DS2Pconv, DSadder, DScontrol, DScross, DSMult, DSmult_module, DSmult_module_last, DSmultiplier, DSPR, Duplicate, DynamicTestBench, edistance2, EmbeddedMultiplier, Encoder, End_rot, End_rot, eq, eq, Equals, Equals, EXAMINE_CI_Virtex, EXAMINE_CI_Virtex, EXAMINE_CI_Virtex2, Exponent, FD, fddrcpe, fddrrse, FLOATINGPOINT, fmap_g, fmap_g, FP_ALU, FP_ALU, FPAddSub, FPAddSub, FPCompare, FPDiv_radix2, FPDiv_radix2, FPDiv_radix2, FPDiv_radix4, FPDiv_radix4, FPDiv_radix4, FPDiv_radix8, FPDiv_radix8, FPDiv_radix8, FPDivide, FPDivide, FPExponentMatch, FPExponentMatch, FPMantissaDivide, FPMult, FPMult, FPPack, FPUnpack, Frac, FreeRunTimer, Fsm, FullAdder, GenericBoard, GenericInterfaceCell, GenericProcessingElement, GenericUserCore, GraphTestBench, gt, gt, Init_rot, Init_rot, IntDivide, IntDivide, KCM_ROM, KCMMult, KCMRom_Adder, KCMRom_AdderBit, lcdoutport, left_edge2, LFSR4, LibrarySelfTester, LogicMisplacement, logicops, LogicSubCell, LogShiftL, LogShiftR, LookupTableBlockRAM, lt, lt, Maximum, Maximum, mod4count2, mult18x18s, MultAdd, MultAdd, MultAdd, MultAdd, MultAdd, MultAddGeneric, MultAddVirtex, MultAddVirtex, MultAddVirtex2, MultAddXC4000, MultAddXC4000, MultCell, multCol, multCol, multCol, multCol, multCol, MultiContextTestBench, MultiplePuts, MultiplierBlock, MultiplierBlockSigned, MULTIPLIERS, MultRow, MultSub, MultSub, MultSub, MultSub, MultSub, MultSubGeneric, MultSubVirtex, MultSubVirtex, MultSubVirtex2, MultSubXC4000, MultSubXC4000, Mux, Mux, NBitAdder, NoBufg, Normalize, Normalize, NormalizePE, ofddrcpe, ofddrrse, OTHERS, P2DSconv, ParallelLeftShiftReg, ParallelRightShiftReg, ParellelDSMult, parinport, paroutport, Pipe_algorithm, Pipe_Algorithm_Stage, Pipe_Frac, Pipe_Reg_e, Pipe_Reg_f, Pipe_Remainder, Pipe_Scale, Pipe_Scale_back, Pipe_sigs, Pipe_sigs, Pipe_Square_root, Pipe_SquareRoot, Pipe_Stage, Pipe_Stages, Priority, Priority, PriorityEncoder, PriorityEncoder, PriorityEncoder, PSR, ram_base, RAMB16, byucc.jhdl.Xilinx.Virtex2.RAMB16, byucc.jhdl.Xilinx.Virtex.RAMB4, RAMB4_Dual, RAMB4_Single, ramrom, ramrom, ramrom, regfile, regX, Remainder, Reverse, RightShiftReg, rom128x1, Rom128x1View, rom256x1, Rom256x1View, rom64x1, Rom64x1View, Round, Round, rounder, rounder, S2Pconv, scale, scale, scale, scale, scale, scale, scale, scale, scale, Scale, scale_back, scale_back, scale_back, scale_back, scale_back, scale_back, scale_back, scale_back, scale_back, Scale_back, ShiftBit, Shifter, Shifter, Shifter, Shifter, Shifter, Shifter, ShifterTable, ShiftMuxR, ShiftRegBit, specialHandler, specialHandler, specialHandler, specialHandler, specialHandler, specialHandler, specialHandler, specialHandler, specialHandler, sport, SPR, Square_root, SquareRoot, srl_array, srl_array, srl_array, SRLArray, SRLArray, SRLFifo, SRLFifo, stage, stage, stage, stage, stage, stage, Stage, Stage, Stagel, StageRP, stages, stages, stages, stages, stages, stages, stages, stages, stages, Stimulator, Sub, SUB_F_CI, SUB_FG_CI, SUB_G_1, SUB_G_F1, SynthesizedFsm, table, table, table, table, table, table, tb_DS_FIR, tb_FPDiv_radix2, tb_FPDiv_radix2, tb_FPDiv_radix2, tb_FPDiv_radix4, tb_FPDiv_radix4, tb_FPDiv_radix4, tb_FPDiv_radix8, tb_FPDiv_radix8, tb_FPDiv_radix8, tb_Template, tb_VirtexKCMMultiplier, tbcomp_IntDivide, Tbone, Tc_mux, Tc_mux, TERACL, TestOverflow, TestOverflow, timerefs, toFixed, toFloat, toFloatExample, toggle, Toggler, uar, uat, UIntDivide, upcnt, upcnt, upcnt, upcnt, upcnt, UpDownCount, upDownCounter, Valid, VarShiftR, Virtex_IOB, XC4000_IOB, XilinxCL, XilinxFD, XilinxLatch, xr16vx_1k, xr16vx_4k, xr16vxcpu, Z_Mux, Z_Mux

public class Logic

extends LogicStatic

The Logic class provides a platform-independent interface into FPGA circuit design. It provides many convenience methods for accelerating structural design. It should be emphasized that none of these methods provide any compution whatsoever, they only are shortcuts for instantiating gates. For example, the method call and(a, b) instantiates a new 2-input and gate for you, wires up a and b to the inputs, instantiates a new wire for you, connects the new wire to the output of the gate, and returns the new wire. Because these method calls return wires, not gates, it allows you to have nested method calls to quickly build up complex logic circuits. For example:

Wire carryOut = or( and(a, b), and(a, ci), and(b, ci) );

One more time: this instantiates 3 "and" gates and 1 "or" gate, it does not compute the resulting carry value. The gates are instantiated as technology-specific primitives from an appropriate vendor library via a TechMapper object.

One more style convention is noteworthy. Most every logic function provided has two versions. One version creates a new output wire for you and returns that wire. The other version lets you pass in the wire reference that you want to use as output; it will return the output wire you pass simply to facilitate nesting. For example, here are the different prototypes for a multiplexor and a 2-input and gate:

and ( Wire in1, Wire in2 ); // Creates a new wire for the output, and returns it

and_o ( Wire in1, Wire in2, Wire out ); // Uses out as the output wire, and returns it

mux ( Wire d0, Wire d1, Wire sel ); // Creates a new wire as the output, and returns it.

mux_o ( Wire d0, Wire d1, Wire sel, Wire out ); // Uses out as the output wire, and returns it.

Note that both gates use a slightly different method call name for the different cases. This is because we need to differentiate the and_o(Wire in1, Wire in2, Wire, out) call from a three-input and-gate: and(Wire in1, Wire in2, Wire in3). This general naming convention will apply for all logic methods -- the suffix "_o" is appended if you provide the output wire; the suffix is not appended when you do not provide the output wire.

Say that you need an and gate. Which version of and should you use? Should be obvious with a little thought: if you already have a reference to the output wire, you need to pass that wire into the function. This is common when the wire has been passed to you and connected to one of the ports, for example. If you don't have a reference, you can let the Logic methods create it for you. This approach is common when building up intermediate logic.

Since:

JHDL0.3

Version:

0.3

Author:

Peter Bellows, Brad Hutchings

Field Summary

static Directive	ABOVE Relational Placement directive which indicates that the current cell should be placed in the negative Y direction on the JHDL grid from a previous cell.
static int	ALIGN_BOTTOM
static int	ALIGN_CENTER
static int	ALIGN_LEFT
static int	ALIGN_LSB
static int	ALIGN_MSB
static int	ALIGN_RIGHT
static int	ALIGN_TOP
static Directive	BELOW Relational Placement directive which indicates that the current cell should be placed in the positive Y direction on the JHDL grid from a previous cell.
static int	DOWN Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.
static Directive	EAST_OF Relational Placement directive which indicates that the current cell should be placed in the positive X direction on the JHDL grid from a previous cell.
static Directive	LEFT_OF Relational Placement directive which indicates that the current cell should be placed in the negative X direction on the JHDL grid from a previous cell.
static int	MAX_PACK Placement directive representing maximal "primitive" packing.
static Directive	NORTH_OF Relational Placement directive which indicates that the current cell should be placed in the negative Y direction on the JHDL grid from a previous cell.
static Directive	ON Relational Placement directive which indicates that the current cell should be placed in the same spot on the JHDL grid as a previous cell.
static int	ONTOP Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.
static Directive	ONTOP_OF Relational Placement directive which indicates that the current cell should be placed in the same spot on the JHDL grid as a previous cell.
static Directive	RIGHT_OF Relational Placement directive which indicates that the current cell should be placed in the positive X direction on the JHDL grid from a previous cell.
static Directive	SOUTH_OF Relational Placement directive which indicates that the current cell should be placed in the positive Y direction on the JHDL grid from a previous cell.
static int	TOLEFT Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.
static int	TORIGHT Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.
static int	UNCONSTRAINED The value representing an unconstrained coordinate in placement.
static int	UP Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.
static Directive	WEST_OF Relational Placement directive which indicates that the current cell should be placed in the negative X direction on the JHDL grid from a previous cell.

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, implicit_interface, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

	Logic(Node parent) Constructs a new Logic object with given node as parent.
	Logic(Node parent, boolean connect_implicit_ports) Constructs a new Logic object with given node as parent.
	Logic(Node parent, java.lang.String name) Constructs a new Logic object with given node as parent, naming it with the given string.
	Logic(Node parent, java.lang.String name, boolean connect_implicit_ports) Constructs a new Logic object with given node as parent, naming it with the given string.
protected	Logic(Node parent, TechMapper tm) Constructs a new Logic object with given node as parent, using the given TechMapper object for technology mapping.
protected	Logic(Node parent, TechMapper tm, java.lang.String name, boolean connect_implicit_ports) Constructs a new Logic object with given node as parent, naming it with the given string, and using the given TechMapper object for technology mapping.

Method Summary

Wire	clockDriver(Wire clock, java.lang.String schedule)
Wire	clockDriver(Wire clock, java.lang.String schedule, java.lang.String name)
protected void	connect_implicit_ports() Deprecated. You should now use the method name of connectImplicitPorts().
protected void	connectImplicitPorts() Connects the implicit ports.
SubCell	constructSubCell(Node parent, java.lang.String name) This call overrides that in Cell, so that pushHierarchy returns a Logic cell.
SubCell	constructSubCellNoImplicitPorts(Node parent, java.lang.String name) This call is used to determine which underlying class is created in Cell.pushHierarchyNoImplicitPorts(CellInterface[], String, boolean, String).
static boolean	enableNewPlacement()
void	enableNewPlacement(boolean enp)
Wire	extend(boolean signed, Wire a, int len) Extend a wire to the left
Wire	extend(boolean signed, Wire a, int len, java.lang.String name) Extend a wire to the left (named)
Wire	getDefaultClock() Returns the default clock for this part of the circuit.
static TechMapper	getDefaultTechMapper() Returns the TechMapper object associated with the Logic class.
Wire	getGlobalClock(HWSystem system) Deprecated. Use getDefaultClock()
static Cell	getSinkCell(Wire w) Finds the simulation sink of the wire parameter.
static Cell	getSourceCell(Cell parent, Wire w) Finds the hierarchical/simulation source of the wire parameter.
Cell	getSourceCell(Wire w) Finds the hierarchical/simulation source of the wire parameter.
static Cell	getSourceLeaf(Wire w) Finds the leaf source of the wire parameter.
Cell	getSourcePlaceable(Wire w) Finds the placeable hierarchical source of the wire parameter.
Cell	getSourcePlaceableLeaf(Wire w) Finds the placeable leaf source of the wire parameter.
java.lang.Class	getSubCellClass() This call overrides that in Cell, so that pushHierarchy knows what Class is created in constructSubCell.
java.lang.String	getTechMapHint(Cell c) Returns a String describing the technology mapping hints for the Cell parameter.
java.lang.String	getTechMapHint(Wire w) Returns a String describing the technology mapping hints for the Cell that is the source for the wire parameter.
TechMapper	getTechMapper() Returns the TechMapper object associated with Logic.
Wire	growAndShiftl(Wire a, int len) Deprecated.
static void	lockChildPlacement(Cell c) Locks the placement of the children of the specified cell.
static Wire	lsb(Wire a) Pick off least significant bit of wire
static Wire	lsb(Wire a, int n) Pick off n-th least significant bit of wire
protected Cell	map(Wire[] warray, Wire o, java.lang.String hints)
Cell	map(Wire i1, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
Cell	map(Wire i1, Wire i2, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire i2, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
Cell	map(Wire i1, Wire i2, Wire i3, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire i2, Wire i3, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire i6, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire i6, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire i6, Wire i7, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire i6, Wire i7, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire i6, Wire i7, Wire i8, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire i6, Wire i7, Wire i8, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire i6, Wire i7, Wire i8, Wire i9, Wire o) Attempts to map given wires to a single architectural "primitive" in the target device.
Cell	map(Wire i1, Wire i2, Wire i3, Wire i4, Wire i5, Wire i6, Wire i7, Wire i8, Wire i9, Wire o, java.lang.String hints) Attempts to map given wires to a single architectural "primitive" in the target device, with String hints.
static Wire	msb(Wire a) Pick off most significant bit of wire
static Wire	msb(Wire a, int n) Pick off n-th most significant bit of wire
static int	msbIndx(Wire a) Return index of MSB of wire
void	netlist() Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.
void	netlist(boolean flat) Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.
void	netlist(boolean flat, java.lang.String filename) Creates a netlist of the default variety determined by the techmapper
static void	netlist(Cell cell) Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.
static void	netlist(Cell cell, boolean flat) Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.
static void	netlist(Cell cell, boolean flat, java.lang.String filename) Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.
static void	netlist(Cell cell, java.lang.String filename) Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.
void	netlist(java.lang.String filename) Creates a netlist of the default variety determined by the techmapper
Wire	padClock_o(Wire pad, Wire in) Create a clock pad.
Wire	padClock_o(Wire pad, Wire in, java.lang.String[] mods) Create a clock pad.
Wire	padClock_o(Wire pad, Wire in, java.lang.String[] mods, java.lang.String name) Create a clock pad.
Wire	padClock(Wire pad) Create a clock pad.
Wire	padClock(Wire pad, java.lang.String[] mods) Create a clock pad.
Wire	padClock(Wire pad, java.lang.String[] mods, java.lang.String name) Create a clock pad.
Wire	padIn_o(Wire pad, Wire in, boolean clocked) Create an input pad.
Wire	padIn_o(Wire pad, Wire in, boolean clocked, java.lang.String[] mods) Create an input pad.
Wire	padIn_o(Wire pad, Wire in, boolean clocked, java.lang.String[] mods, java.lang.String name) Create an input pad.
Wire	padIn(Wire pad, boolean clocked) Create an input pad.
Wire	padIn(Wire pad, boolean clocked, java.lang.String[] mods) Create an input pad.
Wire	padIn(Wire pad, boolean clocked, java.lang.String[] mods, java.lang.String name) Create an input pad.
Wire	padInout_o(Wire out, Wire ena, Wire pad, Wire in, boolean clockedOut, boolean clockedIn) Create an input/output pad.
Wire	padInout_o(Wire out, Wire ena, Wire pad, Wire in, boolean clockedOut, boolean clockedIn, java.lang.String[] mods) Create an input/output pad.
Wire	padInout_o(Wire out, Wire ena, Wire pad, Wire in, boolean clockedOut, boolean clockedIn, java.lang.String[] mods, java.lang.String name) Create an input/output pad.
Wire	padInout(Wire out, Wire ena, Wire pad, boolean clockedOut, boolean clockedIn) Create an input/output pad.
Wire	padInout(Wire out, Wire ena, Wire pad, boolean clockedOut, boolean clockedIn, java.lang.String[] mods) Create an input/output pad.
Wire	padInout(Wire out, Wire ena, Wire pad, boolean clockedOut, boolean clockedIn, java.lang.String[] mods, java.lang.String name) Create an input/output pad.
Wire	padOut_o(Wire out, Wire pad, boolean clocked) Create an output pad.
Wire	padOut_o(Wire out, Wire pad, boolean clocked, java.lang.String[] mods) Create an output pad.
Wire	padOut_o(Wire out, Wire pad, boolean clocked, java.lang.String[] mods, java.lang.String name) Create an output pad.
Wire	padOut(Wire pad, boolean clocked) Create an output pad.
Wire	padOut(Wire pad, boolean clocked, java.lang.String[] mods) Create an output pad.
Wire	padOut(Wire pad, boolean clocked, java.lang.String[] mods, java.lang.String name) Create an output pad.
Wire	padOutT_o(Wire out, Wire ena, Wire pad, boolean clocked) Create a tri-state output pad.
Wire	padOutT_o(Wire out, Wire ena, Wire pad, boolean clocked, java.lang.String[] mods) Create a tri-state output pad.
Wire	padOutT_o(Wire out, Wire ena, Wire pad, boolean clocked, java.lang.String[] mods, java.lang.String name) Create a tri-state output pad.
Wire	padOutT(Wire ena, Wire pad, boolean clocked) Create a tri-state output pad.
Wire	padOutT(Wire ena, Wire pad, boolean clocked, java.lang.String[] mods) Create a tri-state output pad.
Wire	padOutT(Wire ena, Wire pad, boolean clocked, java.lang.String[] mods, java.lang.String name) Create a tri-state output pad.
void	place(Cell curr_cell, Directive dir, Cell prev_cell) Places the cell curr_cell in the direction of dir from prev_cell.
void	place(Cell curr_cell, Directive dir, Wire prev_out) Places curr_cell in the direction of dir from the cell associate with prev_out.
void	place(Cell c, int x, int y) Annotates [x,y] placement hint onto the Cell parameter.
static void	place(Cell c, int x, int y, java.lang.String s) Aqnnotates [x,y] placement hint and target-specific String hint onto the Cell parameter.
static void	place(Cell c, int x, int y, java.lang.String s, boolean complain) This is just here to let internal Logic placement not have warning messages.
void	place(Cell c, java.lang.String s) Annotates target-specific String placement hint onto the Cell parameter.
void	place(Wire currWire, Cell curr_cell, Directive dir, Wire prevWire, Cell prev_cell) This place method is the interface through which all port placement is done.
void	place(Wire currWire, Cell curr_cell, Directive dir, Wire prevWire, Wire prev_out) This place method is a convenience method for port placement.
void	place(Wire curr_out, Directive dir, Cell prev_cell) Places the cell associate with curr_out in the direction of dir from prev_cell.
void	place(Wire curr_out, Directive dir, Wire prev_out) Places the cell associate with curr_out in the direction of dir from prev_out.
void	place(Wire out1, int x, int y) Annotates placement hint (x,y) onto the Cell which drives wire out1.
void	place(Wire out1, int x, int y, int dx, int dy) Annotates placement hint (x,y) onto the Cell which drives wire out1.
void	place(Wire out1, int x, int y, int dx, int dy, java.lang.String s) Deprecated. Iterated placement has caused much painful confusion. Therefore we suggest that you use standard placement, cell transformations, and relational placement instead. This should also simplify your code.
void	place(Wire out1, int x, int y, java.lang.String s) Annotates [x,y] placement hint and target-specific String hint onto the Cell which drives the wire parameter.
void	place(Wire out1, java.lang.String s) Annotates target-specific String placement hint onto the Cell which drives the wire parameter.
void	place(Wire currWire, Wire curr_out, Directive dir, Wire prevWire, Cell prev_cell) This place method is a convenience method for port placement.
void	place(Wire currWire, Wire curr_out, Directive dir, Wire prevWire, Wire prev_out) This place method is a convenience method for port placement.
void	printTechMapHints() Debugging method.
Wire	range(Wire src, int hi, int lo) Returns the sub-range of bits, [hi, lo] (inclusive) from a bus.
Cell	rotate(Cell c, int degrees) Rotates the specified cell by the specifed number of degrees in a counter-clockwise direction.
Cell	rotate(Wire w, int degrees) Rotates the source of the specified wire by the specifed number of degrees in a counter-clockwise direction.
Cell	scale(Cell c, int xFact, int yFact) Scales the specified cell by the specifed amount in the x direction and by the specified amount in the y direction.
Cell	scale(Wire w, int xFact, int yFact) Scales the source of the specified wire by the specifed amount in the x direction and by the specified amount in the y direction.
static java.awt.Point	setBBox(Cell par) This method computes the bounding box of a cell, translates the children of that cell to position the upper left hand corner at (0,0) and returns how far the children were translated.
static void	setDefaultTechMapper(TechMapper tm) Sets the default TechMapper associated with the Logic class.
static void	setFloorPlannerIsMaster(java.lang.Object fp, boolean b) Deprecated. floorPlannerIsMaster is not currently supported.
static void	setTechMappingEnabled(boolean b) Specifies whether technology mapping hints are to be annotated.
protected java.awt.Point	setWandH(Cell par)
Wire	signExtend_o(Wire a, Wire q) Sign extend to width of output wire
Wire	signExtend(Wire a, int len) Sign extend a wire
Wire	signExtend(Wire a, int len, java.lang.String name) Sign extend a wire (named)
Cell	sink(Wire w, Cell c)
Cell	source(Wire w) Deprecated. Use getSourceCell(Wire w), getSourceLeaf(Wire w), or getSourcePlaceable(Wire w), getSourcePlaceableLeaf(Wire w)
Wire	takeBot_o(Wire a, Wire q) Take the bottom part of a and put into output.
Wire	takeBot(Wire a, int len) Take the bottom part of a and put into output.
Wire	takeBot(Wire a, int len, java.lang.String name) Take the bottom part of a and put into output (named).
Wire	takeBotSigned_o(Wire a, Wire q) Take the bottom part of a and put into output.
Wire	takeBotSigned(Wire a, int len) Take the bottom part of a and put into output.
Wire	takeTop_o(Wire a, Wire q) Take the top part of a and put into output.
Wire	takeTop(Wire a, int len) Take the top part of a and put into output.
Wire	takeTop(Wire a, int len, java.lang.String name) Take the top part of a and put into output (named).
void	techmap(java.lang.Object arg) Initiates any necessary post-processing steps in the TechMapper.
static boolean	techMappingEnabled() Indicates the current enable status of technology hint annotation.
Cell	translate(Cell c, int dx, int dy) Translates the specified cell by dx in the x direction and dy in the y direction.
Cell	translate(Wire w, int dx, int dy) Translate the source of wire w by dx in the x direction and dy in the y direction.
Wire	zeroExtend_o(Wire a, Wire q) Zero extend to width of output wire
Wire	zeroExtend(Wire a, int len) Zero extend a wire
Wire	zeroExtend(Wire a, int len, java.lang.String name) Zero extend a wire (named)
Wire	zeroExtendRight_o(Wire a, Wire q) Zero extend a wire on right to width of output
Wire	zeroExtendRight(Wire a, int len) Zero extend a wire on the right

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clock, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, defaultSimulationModelIsBehavioral, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagate, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, reset, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, cellInterfaceDeterminesUniqueNetlistStructure, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

UNCONSTRAINED

public static final int UNCONSTRAINED

The value representing an unconstrained coordinate in placement.

See Also:

Constant Field Values

MAX_PACK

public static final int MAX_PACK

Placement directive representing maximal "primitive" packing.

See Also:

Constant Field Values

UP

public static final int UP

Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.

See Also:

Constant Field Values

DOWN

public static final int DOWN

Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.

See Also:

Constant Field Values

TORIGHT

public static final int TORIGHT

Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.

See Also:

Constant Field Values

TOLEFT

public static final int TOLEFT

Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.

See Also:

Constant Field Values

ONTOP

public static final int ONTOP

Value stored in class byucc.jhdl.Logic.Directive that indicates direction of relational placement.

See Also:

Constant Field Values

ALIGN_RIGHT

public static final int ALIGN_RIGHT

See Also:

Constant Field Values

ALIGN_LEFT

public static final int ALIGN_LEFT

See Also:

Constant Field Values

ALIGN_TOP

public static final int ALIGN_TOP

See Also:

Constant Field Values

ALIGN_BOTTOM

public static final int ALIGN_BOTTOM

See Also:

Constant Field Values

ALIGN_CENTER

public static final int ALIGN_CENTER

See Also:

Constant Field Values

ALIGN_MSB

public static final int ALIGN_MSB

See Also:

Constant Field Values

ALIGN_LSB

public static final int ALIGN_LSB

See Also:

Constant Field Values

ABOVE

public static Directive ABOVE

Relational Placement directive which indicates that the current cell should be placed in the negative Y direction on the JHDL grid from a previous cell.

BELOW

public static Directive BELOW

Relational Placement directive which indicates that the current cell should be placed in the positive Y direction on the JHDL grid from a previous cell.

RIGHT_OF

public static Directive RIGHT_OF

Relational Placement directive which indicates that the current cell should be placed in the positive X direction on the JHDL grid from a previous cell.

LEFT_OF

public static Directive LEFT_OF

Relational Placement directive which indicates that the current cell should be placed in the negative X direction on the JHDL grid from a previous cell.

ON

public static Directive ON

Relational Placement directive which indicates that the current cell should be placed in the same spot on the JHDL grid as a previous cell.

NORTH_OF

public static Directive NORTH_OF

Relational Placement directive which indicates that the current cell should be placed in the negative Y direction on the JHDL grid from a previous cell.

SOUTH_OF

public static Directive SOUTH_OF

Relational Placement directive which indicates that the current cell should be placed in the positive Y direction on the JHDL grid from a previous cell.

EAST_OF

public static Directive EAST_OF

Relational Placement directive which indicates that the current cell should be placed in the positive X direction on the JHDL grid from a previous cell.

WEST_OF

public static Directive WEST_OF

Relational Placement directive which indicates that the current cell should be placed in the negative X direction on the JHDL grid from a previous cell.

ONTOP_OF

public static Directive ONTOP_OF

Relational Placement directive which indicates that the current cell should be placed in the same spot on the JHDL grid as a previous cell.

Constructor Detail

Logic

public Logic(Node parent)

Constructs a new Logic object with given node as parent. Clones the default TechMapper object to get its TechMapper.

Parameters:

parent - The Node object to be used as parent.

Logic

public Logic(Node parent,
             java.lang.String name)

Constructs a new Logic object with given node as parent, naming it with the given string. Clones the default TechMapper object to get its TechMapper.

Parameters:

parent - The Node object to be used as parent.

name - The name of the cell.

Logic

public Logic(Node parent,
             boolean connect_implicit_ports)

Constructs a new Logic object with given node as parent. Clones the default TechMapper object to get its TechMapper.

Parameters:

parent - The Node object to be used as parent.

connect_implicit_ports - Should Logic be responsible for connecting implicit ports

Logic

public Logic(Node parent,
             java.lang.String name,
             boolean connect_implicit_ports)

Constructs a new Logic object with given node as parent, naming it with the given string. Clones the default TechMapper object to get its TechMapper.

Parameters:

parent - The Node object to be used as parent.

name - The name of the cell.

connect_implicit_ports - Should Logic be responsible for connecting implicit ports

Logic

protected Logic(Node parent,
                TechMapper tm)

Constructs a new Logic object with given node as parent, using the given TechMapper object for technology mapping.

Parameters:

parent - The Node object to be used as parent.

tm - The TechMapper object to use for technology mapping.

Logic

protected Logic(Node parent,
                TechMapper tm,
                java.lang.String name,
                boolean connect_implicit_ports)

Constructs a new Logic object with given node as parent, naming it with the given string, and using the given TechMapper object for technology mapping.

Parameters:

parent - The Node object to be used as parent.

tm - The TechMapper object to use for technology mapping.

name - The name of the cell.

Method Detail

getTechMapper

public TechMapper getTechMapper()

Returns the TechMapper object associated with Logic.

Returns:

The TechMapper associated with Logic.

getDefaultTechMapper

public static TechMapper getDefaultTechMapper()

Returns the TechMapper object associated with the Logic class.

Returns:

The TechMapper associated with the Logic class.

setDefaultTechMapper

public static void setDefaultTechMapper(TechMapper tm)

Sets the default TechMapper associated with the Logic class. The default TechMapper is basically cloned by a new Logic object, unless a different TechMapper is explicitly specified. Therefore, you generally only need to set the default TechMapper once before you construct your circuit.

Parameters:

tm - The TechMapper object to be associated with the Logic class.

enableNewPlacement

public static boolean enableNewPlacement()

enableNewPlacement

public void enableNewPlacement(boolean enp)

setFloorPlannerIsMaster

public static void setFloorPlannerIsMaster(java.lang.Object fp,
                                           boolean b)

Deprecated. floorPlannerIsMaster is not currently supported.

Forces all tech-mapping control to be mastered by a FloorPlanner module.

Parameters:

fp - The FloorPlanner module that will be the master

b - true if the FloorPlanner is to be master

setTechMappingEnabled

public static void setTechMappingEnabled(boolean b)

Specifies whether technology mapping hints are to be annotated. If technology mapping is disabled, the map() and place() methods will have no effect.

Parameters:

b - The enable value: true to enable, false to disable.

techMappingEnabled

public static boolean techMappingEnabled()

Indicates the current enable status of technology hint annotation.

Returns:

true if enabled, false if disabled.

connect_implicit_ports

protected void connect_implicit_ports()

Deprecated. You should now use the method name of connectImplicitPorts().

This method used to be used in tandem with #implicit_ports. For backwards compatibility reasons, it is still called by reflection if you have instantiated it, but this practice is discouraged. Instead, you should override the new name.

connectImplicitPorts

protected void connectImplicitPorts()

Connects the implicit ports. Override this if you shadow #implicit_ports. If you used the old version of connect_implicit_ports, this method will use reflection to see that the old version gets called correctly.

getGlobalClock

public Wire getGlobalClock(HWSystem system)

Deprecated. Use getDefaultClock()

Returns the global clock wire associated with the current TechMapper.

Parameters:

system - The HWSystem with which to register the global clock

Returns:

The global clock wire from the current TechMapper.

getDefaultClock

public Wire getDefaultClock()

Returns the default clock for this part of the circuit. If no default clock has been registered, then this method also creates the default clock with a schedule of "01". Thus, this method will always return a Wire, never null, unlike the one it overrides.

Overrides:

getDefaultClock in class Node

Returns:

The default clock for this subtree of the circuit.

clockDriver

public Wire clockDriver(Wire clock,
                        java.lang.String schedule)

clockDriver

public Wire clockDriver(Wire clock,
                        java.lang.String schedule,
                        java.lang.String name)

range

public Wire range(Wire src,
                  int hi,
                  int lo)

Returns the sub-range of bits, [hi, lo] (inclusive) from a bus.

Parameters:

src - Source wire.

hi - Highest-order bit to retrieve (inclusive).

lo - Lowest-order bit to retrieve (inclusive).

Returns:

A new Wire composed only of the bits in the subrange.

map

public Cell map(Wire i1,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire i6,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

i6 - Input 6 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire i6,
                Wire i7,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

i6 - Input 6 to "primitive".

i7 - Input 7 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire i6,
                Wire i7,
                Wire i8,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

i6 - Input 6 to "primitive".

i7 - Input 7 to "primitive".

i8 - Input 8 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire i6,
                Wire i7,
                Wire i8,
                Wire i9,
                Wire o)

Attempts to map given wires to a single architectural "primitive" in the target device. This call is interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

i6 - Input 6 to "primitive".

i7 - Input 7 to "primitive".

i8 - Input 8 to "primitive".

i9 - Input 9 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire i6,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

i6 - Input 6 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire i6,
                Wire i7,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

i6 - Input 6 to "primitive".

i7 - Input 7 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire i6,
                Wire i7,
                Wire i8,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

i6 - Input 6 to "primitive".

i7 - Input 7 to "primitive".

i8 - Input 8 to "primitive".

o - Output to "primitive".

map

public Cell map(Wire i1,
                Wire i2,
                Wire i3,
                Wire i4,
                Wire i5,
                Wire i6,
                Wire i7,
                Wire i8,
                Wire i9,
                Wire o,
                java.lang.String hints)

Attempts to map given wires to a single architectural "primitive" in the target device, with String hints. The mapping call and hint string are interpreted as appropriate by the TechMapper object associated with this Logic object.

Parameters:

i1 - Input 1 to "primitive".

i2 - Input 2 to "primitive".

i3 - Input 3 to "primitive".

i4 - Input 4 to "primitive".

i5 - Input 5 to "primitive".

i6 - Input 6 to "primitive".

i7 - Input 7 to "primitive".

i8 - Input 8 to "primitive".

i9 - Input 9 to "primitive".

o - Output to "primitive".

map

protected Cell map(Wire[] warray,
                   Wire o,
                   java.lang.String hints)

place

public void place(Wire out1,
                  java.lang.String s)

Annotates target-specific String placement hint onto the Cell which drives the wire parameter. This form is used to facilitate the placement of cells which are constructed using other gate-constructing method calls in the Logic class, as explained above.

The meaning of the placement hint is determined by the TechMapper associated with this Logic object.

Parameters:

out1 - Wire whose driver is the gate to be placed.

s - Target-specific placement hint string.

place

public void place(Wire out1,
                  int x,
                  int y)

Annotates placement hint (x,y) onto the Cell which drives wire out1. This form is used to facilitate the placement of cells which are constructed using other gate-constructing method calls in the Logic class. For example, the in the following code we create an and gate and place it, all without every explicitly referencing the gate itself:

Wire and_out = and ( a, b, c, d );

place ( and_out, 5, 6 );

The meaning of the placement hint is determined by the TechMapper associated with this Logic object.

Parameters:

out1 - Wire whose driver is the gate to be placed.

x - X-placement hint.

y - Y-placement hint.

place

public void place(Wire out1,
                  int x,
                  int y,
                  java.lang.String s)

Annotates [x,y] placement hint and target-specific String hint onto the Cell which drives the wire parameter. This form is used to facilitate the placement of cells which are constructed using other gate-constructing method calls in the Logic class, as explained above.

The meaning of the placement hint is determined by the TechMapper associated with this Logic object.

Parameters:

out1 - Wire whose driver is the gate to be placed.

x - X-placement hint.

y - Y-placement hint.

s - Target-specific placement hint string.

place

public void place(Wire out1,
                  int x,
                  int y,
                  int dx,
                  int dy)

Annotates placement hint (x,y) onto the Cell which drives wire out1. This form is used to facilitate the placement of cells which are constructed using other gate-constructing method calls in the Logic class, as explained above.

This form is used for iteratively placing all the cells that drive the individual bits of the wire.

The meaning of the placement hint is determined by the TechMapper associated with this Logic object.

Parameters:

out1 - Wire whose driver is the gate to be placed.

x - X-placement hint.

y - Y-placement hint.

dx - X-increment for iterated placement.

dy - Y-increment for iterated placement.

place

public void place(Wire out1,
                  int x,
                  int y,
                  int dx,
                  int dy,
                  java.lang.String s)

Deprecated. Iterated placement has caused much painful confusion. Therefore we suggest that you use standard placement, cell transformations, and relational placement instead. This should also simplify your code.

Annotates [x,y] placement hint and target-specific String hint onto the Cell which drives the wire parameter. This form is used to facilitate the placement of cells which are constructed using other gate-constructing method calls in the Logic class, as explained above.

This form is also used for iteratively placing all the cells that drive the individual bits of the wire. For example, assume that we have the following code, which instantiates and places 8 bits of register:

Wire in = wire( 8 ); Wire out = reg( in ); place( in, 0, 0, 1, 3 ); should result in placing the registers in positions (0,0), (1,3), (2,6), (3,9), ... The meaning of each placement hint is determined by the TechMapper associated with this Logic object.

Parameters:

out1 - Wire whose driver is the gate to be placed.

x - X-placement hint.

y - Y-placement hint.

dx - X-increment for iterated placement.

dy - Y-increment for iterated placement.

s - Target-specific placement hint string.

place

public void place(Cell c,
                  int x,
                  int y)

Annotates [x,y] placement hint onto the Cell parameter. The meaning of the placement hint is determined by the TechMapper associated with this Logic object.

Parameters:

c - Cell to be placed.

place

public void place(Cell c,
                  java.lang.String s)

Annotates target-specific String placement hint onto the Cell parameter. The meaning of the placement hint is determined by the TechMapper associated with this Logic object.

Parameters:

c - Cell to be placed.

s - Target-specific placement hint string.

place

public static void place(Cell c,
                         int x,
                         int y,
                         java.lang.String s)

Aqnnotates [x,y] placement hint and target-specific String hint onto the Cell parameter. The meaning of the placement hint is determined by the TechMapper associated with this Logic object.

Parameters:

c - Cell to be placed.

x - X-placement hint.

y - Y-placement hint.

s - Target-specific placement hint string.

place

public static void place(Cell c,
                         int x,
                         int y,
                         java.lang.String s,
                         boolean complain)

This is just here to let internal Logic placement not have warning messages.

place

public void place(Wire curr_out,
                  Directive dir,
                  Wire prev_out)

Places the cell associate with curr_out in the direction of dir from prev_out. This version of the place() method places the cell associated with an output Wire (curr_out) in the direction of the Directive parameter (dir) from a previously placed cell using the output Wire (prev_out) of the previously placed Cell. If the previous Cell was not placed it will get placed at (0,0). This method will then call a more basic place() method which will annotate the calculated placement Hint onto that cell and interpret them as determined by the techmapper.

Parameters:

curr_out - The output Wire of the cell to be placed.

dir - A Directive object that specifies how this cell is to be placed and aligned relative to the previous cell.

prev_out - The output Wire of the cell we are placing relative to.

place

public void place(Cell curr_cell,
                  Directive dir,
                  Wire prev_out)

Places curr_cell in the direction of dir from the cell associate with prev_out. This version of the place() method places the cell (curr_cell) in the direction of the Directive parameter (dir) from a previously placed cell using the output Wire (prev_out) of the previously placed Cell. If the previous Cell was not placed it will get placed at (0,0). This method will then call a more basic place() method which will annotate the calculated placement Hint onto this cell and interpret them as determined by the techmapper.

Parameters:

curr_cell - The cell to be placed.

dir - A Directive object that specifies how this cell is to be placed and aligned relative to the previous cell.

prev_out - The output Wire of the cell we are placing relative to.

place

public void place(Wire curr_out,
                  Directive dir,
                  Cell prev_cell)

Places the cell associate with curr_out in the direction of dir from prev_cell. This version of the place() method places the cell associated with an output Wire (curr_out) in the direction of the Directive parameter (dir) from a previously placed cell (prev_cell). If the previous Cell was not placed it will get placed at (0,0). This method will then call a more basic place() method which will annotate the calculated placement Hint onto that cell and interpret them as determined by the techmapper.

Parameters:

curr_out - The output Wire of the cell to be placed.

dir - A Directive object that specifies how this cell is to be placed and aligned relative to the previous cell.

prev_cell - The cell we are placing relative to.

place

public void place(Cell curr_cell,
                  Directive dir,
                  Cell prev_cell)

Places the cell curr_cell in the direction of dir from prev_cell. This version of the place() method places the cell (curr_out) in the direction of the Directive parameter (dir) from a previously placed cell (prev_cell). If the previous Cell was not placed it will get placed at (0,0). This method will then call a more basic place() method which will annotate the calculated placement Hint onto that cell and interpret them as determined by the techmapper.
If the directive specified has an alignment wire associated with it, the the appropriate port placement call. This is determined by whether the current cell to be placed is the source of the alignment wire or not.

Parameters:

curr_cell - The cell to be placed.

dir - A Directive object that specifies how this cell is to be placed and aligned relative to the previous cell.

prev_cell - The cell we are placing relative to.

place

public void place(Wire currWire,
                  Wire curr_out,
                  Directive dir,
                  Wire prevWire,
                  Wire prev_out)

This place method is a convenience method for port placement. The basic stradegy is to place the source of current wire in the direction of the directive from the source of previous out and to align the leaf cell in current cell that is attached to currWire with the leaf cell that is attached to prevWire in previous cell. If the the current cell has both a source and a sink of inwire within it, the default action is to use the source. The same is true for the leaf source or sink of the previous wire within the previous cell.

Parameters:

currWire - the Wire to align curr_cell with.

curr_out - the Wire whose source is to be placed.

dir - The Directive which specifies the direction to place in.

prevWire - the Wire to align the previous cell with.

prev_out - the Wire whose source we are placing relationally to.

place

public void place(Wire currWire,
                  Cell curr_cell,
                  Directive dir,
                  Wire prevWire,
                  Wire prev_out)

This place method is a convenience method for port placement. The basic stradegy is to place the current cell in the direction of the directive from the source of previous out and to align the leaf cell in current cell that is attached to currwire with the leaf cell that is attached to prevwire in previous cell. If the the current cell has both a source and a sink of inwire within it, the default action is to use the source. The same is true for the leaf source or sink of previous wire within the previous cell.

Parameters:

currWire - the Wire to align curr_cell with.

curr_cell - the Cell to be placed.

dir - The Directive which specifies the direction to place in.

prevWire - the Wire to align the previous cell with.

prev_out - the Wire whose source we are placing relationally to.

place

public void place(Wire currWire,
                  Wire curr_out,
                  Directive dir,
                  Wire prevWire,
                  Cell prev_cell)

This place method is a convenience method for port placement. The basic stradegy is to place the source of current out in the direction of the directive from the previous cell and to align the leaf cell in current cell that is attached to currWire with the leaf cell that is attached to prevWire in previous cell. If the the current cell has both a source and a sink of currWire within it, the default action is to use the source. The same is true for the leaf source or sink of prevWire within the previous cell.

Parameters:

currWire - the Wire to align curr_cell with.

curr_out - the Wire whose source is to be placed.

dir - The Directive which specifies the direction to place in.

prevWire - the Wire to align the previous cell with.

prev_cell - the Cell that we are placing relationally to.

place

public void place(Wire currWire,
                  Cell curr_cell,
                  Directive dir,
                  Wire prevWire,
                  Cell prev_cell)

This place method is the interface through which all port placement is done. The basic stradegy is to place the current cell in the direction of the directive from the previous cell and to align the leaf cell in current cell that is attached to inwire with the leaf cell that is attached to outwire in previous cell. If the the current cell has both a source and a sink of inwire within it, the default action is to use the source. The same is true for the leaf source or sink of outwire within the previous cell.

Parameters:

currWire - the Wire to align curr_cell with.

curr_cell - the Cell to be placed.

dir - The Directive which specifies the direction to place in.

prevWire - the Wire to align the previous cell with.

prev_cell - the Cell that we are placing relationally to.

translate

public Cell translate(Wire w,
                      int dx,
                      int dy)

Translate the source of wire w by dx in the x direction and dy in the y direction. This is only permitted on a cell that has already been placed and that is not locked with respect to it's siblings.

Parameters:

w - The output wire of the cell to be tranlated.

dx - How far to translate the cell in the x direction.

dy - How far to translate the cell in the y direction.

Returns:

The translated cell;

translate

public Cell translate(Cell c,
                      int dx,
                      int dy)

Translates the specified cell by dx in the x direction and dy in the y direction. This is only permitted on a cell that has already been placed and that is not locked with respect to it's siblings.

Parameters:

dx - How far to translate the cell in the x direction.

dy - How far to translate the cell in the y direction.

Returns:

The translated cell;

rotate

public Cell rotate(Wire w,
                   int degrees)

Rotates the source of the specified wire by the specifed number of degrees in a counter-clockwise direction. This is only defined on a cell that has not already been placed. Only integer degree values between -270 and 360 that are multiples of 90 degrees are currently supported.

Parameters:

w - The output wire of the cell to be rotated.

degrees - How far to rotate the cell in the Counter-clockwise direction.

Returns:

The rotated cell;

rotate

public Cell rotate(Cell c,
                   int degrees)

Rotates the specified cell by the specifed number of degrees in a counter-clockwise direction. This is only defined on a cell that has not already been placed. Only integer degree values between -270 and 360 that are multiples of 90 degrees are currently supported.

Parameters:

c - The cell to be rotated.

degrees - How far to rotate the cell in the Counter-clockwise direction.

Returns:

The rotated cell;

scale

public Cell scale(Wire w,
                  int xFact,
                  int yFact)

Scales the source of the specified wire by the specifed amount in the x direction and by the specified amount in the y direction. This is only defined on a cell that has not already been placed. Only integer values are currently supported. This scaling will recursively scale all children of the specified cell by the same amount. However, the interpretation of the placement values is VERY technology dependant. That is, whether the JHDL coordinate grid is interpreted as a CLB grid, a Slice grid, or a LUT grid is based on the techmapper being used. The result of scaling will also be determined by the techmapper of choice.

Parameters:

w - The output wire of the cell to be scaled.

xFact - How much to scale the cell by in the X direction.

yFact - How much to scale the cell by in the Y direction.

Returns:

The scaled cell;

scale

public Cell scale(Cell c,
                  int xFact,
                  int yFact)

Scales the specified cell by the specifed amount in the x direction and by the specified amount in the y direction. This is only defined on a cell that has not already been placed. Only integer values are currently supported. This scaling will recursively scale all children of the specified cell by the same amount. However, the interpretation of the placement values is VERY technology dependant. That is, whether the JHDL coordinate grid is interpreted as a CLB grid, a Slice grid, or a LUT grid is based on the techmapper being used. The result of scaling will also be determined by the techmapper of choice.

Parameters:

c - The cell to be scaled.

xFact - How much to scale the cell by in the X direction.

yFact - How much to scale the cell by in the Y direction.

Returns:

The scaled cell;

setBBox

public static java.awt.Point setBBox(Cell par)

This method computes the bounding box of a cell, translates the children of that cell to position the upper left hand corner at (0,0) and returns how far the children were translated. This is done by iterating through the children of a cell and taking the point where each child was placed as the upper left hand corner, and the width and height added to that point to be the lower right hand corner. Then the maximum of the lower right hand x's and the maximum of the lower right hand y's becomes the lower right hand corner of the parent. While the minimum of the upper left corners in x and y becomes the upper left corner of the parent.
Then, if new placement is enabled, it will translate all the children of this cell such that the upper left hand corner is at (0,0) in the JHDL coordinate grid. a Point is returned that corresponds to difference between the cell's origin and the upper left hand corner.

Parameters:

par - The cell for which we are computing a bounding box.

Returns:

A new Point with the coordinates of the upper left hand corner relative to the current origin of the cell.

setWandH

protected java.awt.Point setWandH(Cell par)

lockChildPlacement

public static void lockChildPlacement(Cell c)

Locks the placement of the children of the specified cell. This means that in the future if one child is transformed in any way, all children must be transformed in the same way. In other words, the children of this cell are locked together.

Parameters:

c - The cell whose children will be locked together.

techmap

public void techmap(java.lang.Object arg)

Initiates any necessary post-processing steps in the TechMapper. Generally does not need to be called by the user.

source

public Cell source(Wire w)

Deprecated. Use getSourceCell(Wire w), getSourceLeaf(Wire w), or getSourcePlaceable(Wire w), getSourcePlaceableLeaf(Wire w)

Returns the Cell which is the source for the wire paramater in the current level of hierarchy. This is different than the source nodes listed in the wires sinks/sources list -- for example, say we have the following:

new adder(a, b, sum); // A structural adder

Cell c = source(sum); // Find the source

In the above example, c will be a reference to the new adder. If we looked at sum's source nodes, however, we would only find the individual xor gates, etc. inside the adder that drive the wire in simulation.

Parameters:

w - Wire whose source is to be found.

Returns:

The Cell which is the hierarchical source of the wire.

getSourceCell

public Cell getSourceCell(Wire w)

Finds the hierarchical/simulation source of the wire parameter. This is derived from the sink/source lists in the wire. If multiple drivers are found, an exception is thrown.

Parameters:

w - Wire whose simulation sources is to be found.

Returns:

The Cell which is the hierarchical source of the wire.

getSourceCell

public static Cell getSourceCell(Cell parent,
                                 Wire w)

Finds the hierarchical/simulation source of the wire parameter. This is derived from the sink/source lists in the wire. If multiple drivers are found, an exception is thrown.

Parameters:

parent - Cell who is the hierarchical/simulation parent of the cell to return.

w - Wire whose simulation sources is to be found.

Returns:

The Cell which is the hierarchical source of the wire.

getSourceLeaf

public static Cell getSourceLeaf(Wire w)

Finds the leaf source of the wire parameter. This is derived from the sink/source lists in the wire. If multiple drivers are found, an exception is thrown.

Parameters:

w - Wire whose simulation sources is to be found.

Returns:

The Cell which is the leaf source of the wire.

getSourcePlaceable

public Cell getSourcePlaceable(Wire w)

Finds the placeable hierarchical source of the wire parameter. This is derived from the sink/source lists in the wire. If multiple drivers are found, an exception is thrown.

Parameters:

w - Wire whose simulation sources is to be found.

Returns:

The Cell which is the leaf source of the wire.

getSourcePlaceableLeaf

public Cell getSourcePlaceableLeaf(Wire w)

Finds the placeable leaf source of the wire parameter. This is derived from the sink/source lists in the wire. If multiple drivers are found, an exception is thrown.

Parameters:

w - Wire whose simulation sources is to be found.

Returns:

The Cell which is the leaf source of the wire.

sink

public Cell sink(Wire w,
                 Cell c)

getSinkCell

public static Cell getSinkCell(Wire w)

Finds the simulation sink of the wire parameter. This is derived from the sink/source lists in the wire. If multiple sinks are found, an exception is thrown.

Parameters:

w - Wire whose simulation sink is to be found.

Returns:

The Cell which is the simulation sink of the wire.

getTechMapHint

public java.lang.String getTechMapHint(Wire w)

Returns a String describing the technology mapping hints for the Cell that is the source for the wire parameter. Meaning of hint string is determined by the TechMapper object associated with this Logic object.

Parameters:

w - Wire driven by the desired source Cell.

Returns:

Current technology mapping hints associated with the cell encoded in a target-specific string.

getTechMapHint

public java.lang.String getTechMapHint(Cell c)

Returns a String describing the technology mapping hints for the Cell parameter. Meaning of hint string is determined by the TechMapper object associated with this Logic object.

Parameters:

c - Cell whose technology mapping hints are to be returned.

Returns:

Current technology mapping hints associated with the cell encoded in a target-specific string.

printTechMapHints

public void printTechMapHints()

Debugging method. Prints out TechMapper-specific status string.

constructSubCell

public SubCell constructSubCell(Node parent,
                                java.lang.String name)

This call overrides that in Cell, so that pushHierarchy returns a Logic cell.

Overrides:

constructSubCell in class Cell

Parameters:

parent - the parent of the subcell

name - the name of the subcell

Returns:

the newly created subcell

constructSubCellNoImplicitPorts

public SubCell constructSubCellNoImplicitPorts(Node parent,
                                               java.lang.String name)

Description copied from class: Cell

This call is used to determine which underlying class is created in Cell.pushHierarchyNoImplicitPorts(CellInterface[], String, boolean, String). The SubCell interface should only be applied to an object that extends Cell. When extending this, be sure to also extend getSubCellClass.

Overrides:

constructSubCellNoImplicitPorts in class Cell

Parameters:

parent - the parent of the subcell

name - the name of the subcell

Returns:

the newly created subcell

getSubCellClass

public java.lang.Class getSubCellClass()

This call overrides that in Cell, so that pushHierarchy knows what Class is created in constructSubCell.

Overrides:

getSubCellClass in class Cell

Returns:

the Class LogicSubCell

takeTop

public Wire takeTop(Wire a,
                    int len)

Take the top part of a and put into output. Zero pad on the right if necessary. Do not round.

Parameters:

a - the input wire

len - length to chop to

Returns:

the output wire

takeTop

public Wire takeTop(Wire a,
                    int len,
                    java.lang.String name)

Take the top part of a and put into output (named). Zero pad on the right if necessary. Do not round.

Parameters:

a - the input wire

len - length to chop to

name - name of the cell and output wire

Returns:

the output wire

takeTop_o

public Wire takeTop_o(Wire a,
                      Wire q)

Take the top part of a and put into output. Zero pad on the right if necessary. Do not round.

Parameters:

a - the input wire

q - the output wire

Returns:

the output wire

takeBot

public Wire takeBot(Wire a,
                    int len)

Take the bottom part of a and put into output. Zero pad on the left if necessary.

Parameters:

a - the input wire

len - length to chop to

Returns:

the output wire

takeBot

public Wire takeBot(Wire a,
                    int len,
                    java.lang.String name)

Take the bottom part of a and put into output (named). Zero pad on the left if necessary.

Parameters:

a - the input wire

len - length to chop to

Returns:

the output wire

takeBot_o

public Wire takeBot_o(Wire a,
                      Wire q)

Take the bottom part of a and put into output. Zero pad on the left if necessary.

Parameters:

a - the input wire

q - the output wire

Returns:

the output wire

takeBotSigned

public Wire takeBotSigned(Wire a,
                          int len)

Take the bottom part of a and put into output. Sign-extend if necessary.

Parameters:

a - the input wire

len - length to chop to

Returns:

the output wire

takeBotSigned_o

public Wire takeBotSigned_o(Wire a,
                            Wire q)

Take the bottom part of a and put into output. Sign-extend if necessary.

Parameters:

a - the input wire

Returns:

the output wire

extend

public Wire extend(boolean signed,
                   Wire a,
                   int len)

Extend a wire to the left

Parameters:

signed - tell whether to do signed extend or zero pad

a - the input wire

Returns:

the output wire

extend

public Wire extend(boolean signed,
                   Wire a,
                   int len,
                   java.lang.String name)

Extend a wire to the left (named)

Parameters:

signed - tell whether to do signed extend or zero pad

a - the input wire

name - name of the cell and output wire

Returns:

the output wire

signExtend

public Wire signExtend(Wire a,
                       int len)

Sign extend a wire

Parameters:

a - the input wire

len - number of places to extend to

Returns:

the output wire

signExtend

public Wire signExtend(Wire a,
                       int len,
                       java.lang.String name)

Sign extend a wire (named)

Parameters:

a - the input wire

len - number of places to extend to

name - name of the cell and output wire

Returns:

the output wire

signExtend_o

public Wire signExtend_o(Wire a,
                         Wire q)

Sign extend to width of output wire

Parameters:

a - the input wire

q - the output wire

Returns:

the output wire

zeroExtend

public Wire zeroExtend(Wire a,
                       int len)

Zero extend a wire

Parameters:

a - the input wire

len - number of places to extend to

Returns:

the output wire

zeroExtend

public Wire zeroExtend(Wire a,
                       int len,
                       java.lang.String name)

Zero extend a wire (named)

Parameters:

a - the input wire

len - number of places to extend to

name - name of the cell and output wire

Returns:

the output wire

zeroExtend_o

public Wire zeroExtend_o(Wire a,
                         Wire q)

Zero extend to width of output wire

Parameters:

a - the input wire

q - the output wire

Returns:

the output wire

zeroExtendRight

public Wire zeroExtendRight(Wire a,
                            int len)

Zero extend a wire on the right

Parameters:

a - the input wire

len - number of places to extend to

Returns:

the output wire

zeroExtendRight_o

public Wire zeroExtendRight_o(Wire a,
                              Wire q)

Zero extend a wire on right to width of output

Parameters:

a - the input wire

q - the output wire

Returns:

the output wire

growAndShiftl

public Wire growAndShiftl(Wire a,
                          int len)

Deprecated.

Zero extend a wire on the right

Parameters:

a - the input wire

len - number of places to extend to

msb

public static Wire msb(Wire a)

Pick off most significant bit of wire

Parameters:

a - the wire

Returns:

the requested bit

msb

public static Wire msb(Wire a,
                       int n)

Pick off n-th most significant bit of wire

Parameters:

a - the wire

n - 0=MSB, 1=next to MSB, etc...

Returns:

the requested bit

lsb

public static Wire lsb(Wire a)

Pick off least significant bit of wire

Parameters:

a - the wire

Returns:

the requested bit

lsb

public static Wire lsb(Wire a,
                       int n)

Pick off n-th least significant bit of wire

Parameters:

a - the wire

n - 0=LSB, 1=next to LSB, etc...

Returns:

the requested bit

msbIndx

public static int msbIndx(Wire a)

Return index of MSB of wire

Parameters:

a - the wire

Returns:

the index of the MSB

padIn

public Wire padIn(Wire pad,
                  boolean clocked)

Create an input pad. Can be clocked.

Parameters:

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padIn

public Wire padIn(Wire pad,
                  boolean clocked,
                  java.lang.String[] mods)

Create an input pad. Can be clocked. Modifiers are technology-dependent.

Parameters:

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000=none, Virtex=none.

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padIn

public Wire padIn(Wire pad,
                  boolean clocked,
                  java.lang.String[] mods,
                  java.lang.String name)

Create an input pad. Can be clocked. Modifiers are technology-dependent.

Parameters:

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000=none, Virtex=none.

name - the name of the buffer or flip flop output wire created

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padIn_o

public Wire padIn_o(Wire pad,
                    Wire in,
                    boolean clocked)

Create an input pad. Can be clocked.

Parameters:

pad - the pad wire

in - a wire to hook up the buffer or flip flop output to

clocked - flag indicating whether it should be a clocked pad or just combinational

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padIn_o

public Wire padIn_o(Wire pad,
                    Wire in,
                    boolean clocked,
                    java.lang.String[] mods)

Create an input pad. Can be clocked. Modifiers are technology-dependent.

Parameters:

pad - the pad wire

in - a wire to hook up the buffer or flip flop output to

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000=none, Virtex=none.

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padIn_o

public Wire padIn_o(Wire pad,
                    Wire in,
                    boolean clocked,
                    java.lang.String[] mods,
                    java.lang.String name)

Create an input pad. Can be clocked. Modifiers are technology-dependent.

Parameters:

pad - the pad wire

in - a wire to hook up the buffer or flip flop output to

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000=none, Virtex=none.

name - the name of the buffer or flip flop output wire created

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padOut

public Wire padOut(Wire pad,
                   boolean clocked)

Create an output pad. Can be clocked. This cell is unusual in that the created wire is the INPUT to the output buffer or IOB flip flop created. That is the wire returned as well.

Parameters:

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

Returns:

the input to the output buffer or flip flop - to be used inside circuit core

padOut

public Wire padOut(Wire pad,
                   boolean clocked,
                   java.lang.String[] mods)

Create an output pad. Can be clocked. Modifiers are technology-dependent. This cell is unusual in that the created wire is the INPUT to the output buffer or IOB flip flop created. That is the wire returned as well.

Parameters:

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

Returns:

the input to the output buffer or flip flop - to be used inside circuit core

padOut

public Wire padOut(Wire pad,
                   boolean clocked,
                   java.lang.String[] mods,
                   java.lang.String name)

Create an output pad. Can be clocked. Modifiers are technology-dependent. This cell is unusual in that the created wire is the INPUT to the output buffer or IOB flip flop created. That is the wire returned as well.

Parameters:

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

name - name of wire created as the input to the output buffer or flip flop and name of buffer or flip flop

Returns:

the input to the output buffer or flip flop - to be used inside circuit core

padOut_o

public Wire padOut_o(Wire out,
                     Wire pad,
                     boolean clocked)

Create an output pad. Can be clocked.

Parameters:

out - the wire in your circuit which should be the input to the output buffer or flip flop

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

Returns:

the input to the output buffer or flip flop - to be used inside circuit core

padOut_o

public Wire padOut_o(Wire out,
                     Wire pad,
                     boolean clocked,
                     java.lang.String[] mods)

Create an output pad. Can be clocked. Modifiers are technology-dependent.

Parameters:

out - the wire in your circuit which should be the input to the output buffer or flip flop

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

Returns:

the input to the output buffer or flip flop - to be used inside circuit core

padOut_o

public Wire padOut_o(Wire out,
                     Wire pad,
                     boolean clocked,
                     java.lang.String[] mods,
                     java.lang.String name)

Create an output pad. Can be clocked. Modifiers are technology-dependent.

Parameters:

out - the wire in your circuit which should be the input to the output buffer or flip flop

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

name - name of buffer or flip flop created

Returns:

the input to the output buffer or flip flop - to be used inside circuit core

padOutT

public Wire padOutT(Wire ena,
                    Wire pad,
                    boolean clocked)

Create a tri-state output pad. Can be clocked. This cell is unusual in that the created wire is the INPUT to the tri-state buffer or IOB flip flop created. That is the wire returned as well.

Parameters:

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

Returns:

the input to the output buffer or flip flop - to be used inside circuit core

padOutT

public Wire padOutT(Wire ena,
                    Wire pad,
                    boolean clocked,
                    java.lang.String[] mods)

Create a tri-state output pad. Can be clocked. Modifiers are technology-dependent. This cell is unusual in that the created wire is the INPUT to the tri-state buffer or IOB flip flop created. That is the wire returned as well.

Parameters:

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

Returns:

the input to the output buffer or flip flop - to be used inside circuit core

padOutT

public Wire padOutT(Wire ena,
                    Wire pad,
                    boolean clocked,
                    java.lang.String[] mods,
                    java.lang.String name)

Create a tri-state output pad. Can be clocked. Modifiers are technology-dependent. This cell is unusual in that the created wire is the INPUT to the tri-state buffer or IOB flip flop created. That is the wire returned as well.

Parameters:

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

name - the name of the input wire created

Returns:

the input to the tri-state buffer or flip flop - to be used inside circuit core

padOutT_o

public Wire padOutT_o(Wire out,
                      Wire ena,
                      Wire pad,
                      boolean clocked)

Create a tri-state output pad. Can be clocked.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

Returns:

the input to the tri-state buffer or flip flop - to be used inside circuit core

padOutT_o

public Wire padOutT_o(Wire out,
                      Wire ena,
                      Wire pad,
                      boolean clocked,
                      java.lang.String[] mods)

Create a tri-state output pad. Can be clocked. Modifiers are technology-dependent.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

Returns:

the input to the tri-state buffer or flip flop - to be used inside circuit core

padOutT_o

public Wire padOutT_o(Wire out,
                      Wire ena,
                      Wire pad,
                      boolean clocked,
                      java.lang.String[] mods,
                      java.lang.String name)

Create a tri-state output pad. Can be clocked. Modifiers are technology-dependent.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clocked - flag indicating whether it should be a clocked pad or just combinational

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

name - the name of the buffer or register created.

Returns:

the input to the tri-state buffer or flip flop - to be used inside circuit core

padInout

public Wire padInout(Wire out,
                     Wire ena,
                     Wire pad,
                     boolean clockedOut,
                     boolean clockedIn)

Create an input/output pad. This simply instances a PadIn() and an padOutT(). Returns the output of the padIn() to be used inside circuit.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clockedOut - flag indicating whether a clocked tri-state should be used or just a simple tri-state buffer

clockedIn - flag indicating whether input path should be clocked

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padInout

public Wire padInout(Wire out,
                     Wire ena,
                     Wire pad,
                     boolean clockedOut,
                     boolean clockedIn,
                     java.lang.String[] mods)

Create an input/output pad. This simply instances a PadIn() and an padOutT(). Returns the output of the padIn() to be used inside circuit. Modifiers apply to tri-state output section. Modifiers are technology-dependent.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clockedOut - flag indicating whether a clocked tri-state should be used or just a simple tri-state buffer

clockedIn - flag indicating whether input path should be clocked

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padInout

public Wire padInout(Wire out,
                     Wire ena,
                     Wire pad,
                     boolean clockedOut,
                     boolean clockedIn,
                     java.lang.String[] mods,
                     java.lang.String name)

Create an input/output pad. This simply instances a PadIn() and an padOutT(). Returns the output of the padIn() to be used inside circuit. Modifiers apply to tri-state output section. Modifiers are technology-dependent.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

clockedOut - flag indicating whether a clocked tri-state should be used or just a simple tri-state buffer

clockedIn - flag indicating whether input path should be clocked

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

name - the name of the buffer or flip flop output wire created

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padInout_o

public Wire padInout_o(Wire out,
                       Wire ena,
                       Wire pad,
                       Wire in,
                       boolean clockedOut,
                       boolean clockedIn)

Create an input/output pad. This simply instances a PadIn() and an padOutT(). Returns the output of the padIn() to be used inside circuit.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

in - the output of the input buffer or flip flop

clockedOut - flag indicating whether a clocked tri-state should be used or just a simple tri-state buffer

clockedIn - flag indicating whether input path should be clocked

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padInout_o

public Wire padInout_o(Wire out,
                       Wire ena,
                       Wire pad,
                       Wire in,
                       boolean clockedOut,
                       boolean clockedIn,
                       java.lang.String[] mods)

Create an input/output pad. This simply instances a PadIn() and an padOutT(). Returns the output of the padIn() to be used inside circuit. Modifiers apply to tri-state output section. Modifiers are technology-dependent.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

in - the output of the input buffer or flip flop

clockedOut - flag indicating whether a clocked tri-state should be used or just a simple tri-state buffer

clockedIn - flag indicating whether input path should be clocked

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padInout_o

public Wire padInout_o(Wire out,
                       Wire ena,
                       Wire pad,
                       Wire in,
                       boolean clockedOut,
                       boolean clockedIn,
                       java.lang.String[] mods,
                       java.lang.String name)

Create an input/output pad. This simply instances a PadIn() and an padOutT(). Returns the output of the padIn() to be used inside circuit. Modifiers apply to tri-state output section. Modifiers are technology-dependent.

Parameters:

out - the wire in your circuit which should be the input to the tri-state buffer or flip flop

ena - the enable wire to the tri-state buffer. Active low.

pad - the pad wire

in - the output of the input buffer or flip flop

clockedOut - flag indicating whether a clocked tri-state should be used or just a simple tri-state buffer

clockedIn - flag indicating whether input path should be clocked

mods - String array of modifiers for pad. Legal modifers: XC4000="FAST", "SLOW", Virtex="FAST", "SLOW".

name - the name of the buffer or flip flop output wire created

Returns:

the output of the input buffer or flip flop - to be used inside circuit core

padClock

public Wire padClock(Wire pad)

Create a clock pad. If you use this you will need to also use #clockDriver() to set up your clock with a pattern and, optionally, DLL's or anything else your technology supports.

Parameters:

pad - the pad wire

Returns:

the output of the clock buffer - to be used in a call to clockDriver() inside circuit core

padClock

public Wire padClock(Wire pad,
                     java.lang.String[] mods)

Create a clock pad. If you use this you will need to also use #clockDriver() to set up your clock with a pattern and, optionally, DLL's or anything else your technology supports. Modifiers are technology-dependent.

Parameters:

pad - the pad wire

mods - String array of modifiers for pad. Legal modifers: XC4000=none, Virtex=none.

Returns:

the output of the clock buffer - to be used in a call to clockDriver() inside circuit core

padClock

public Wire padClock(Wire pad,
                     java.lang.String[] mods,
                     java.lang.String name)

Create a clock pad. If you use this you will need to also use #clockDriver() to set up your clock with a pattern and, optionally, DLL's or anything else your technology supports. Legal modifers: XC4000=none, Virtex=none.

Parameters:

pad - the pad wire

mods - String array of modifiers for pad. No modifiers currently recognized

name - name of the wire created and returned

Returns:

the output of the clock buffer - to be used in a call to clockDriver() inside circuit core

padClock_o

public Wire padClock_o(Wire pad,
                       Wire in)

Create a clock pad. If you use this you will need to also use #clockDriver() to set up your clock with a pattern and, optionally, DLL's or anything else your technology supports.

Parameters:

pad - the pad wire

in - a wire to hook up the buffer or flip flop output to

Returns:

the output of the clock buffer or flip flop - to be used in a call to clockDriver() inside circuit core

padClock_o

public Wire padClock_o(Wire pad,
                       Wire in,
                       java.lang.String[] mods)

Create a clock pad. If you use this you will need to also use #clockDriver() to set up your clock with a pattern and, optionally, DLL's or anything else your technology supports. Modifiers are technology-dependent.

Parameters:

pad - the pad wire

in - a wire to hook up the buffer or flip flop output to

mods - String array of modifiers for pad. Legal modifers: XC4000=none, Virtex=none.

Returns:

the output of the clock buffer or flip flop - to be used in a call to clockDriver() inside circuit core

padClock_o

public Wire padClock_o(Wire pad,
                       Wire in,
                       java.lang.String[] mods,
                       java.lang.String name)

Create a clock pad. If you use this you will need to also use #clockDriver() to set up your clock with a pattern and, optionally, DLL's or anything else your technology supports. Modifiers are technology-dependent.

Parameters:

pad - the pad wire

in - a wire to hook up the buffer or flip flop output to

mods - String array of modifiers for pad. Legal modifers: XC4000=none, Virtex=none.

name - name of the pad or buffer created

Returns:

the output of the clock buffer or flip flop - to be used in a call to clockDriver() inside circuit core

netlist

public void netlist()

Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.

netlist

public void netlist(java.lang.String filename)

Creates a netlist of the default variety determined by the techmapper

Parameters:

filename - the (top-level) file to write the netlist in

netlist

public static void netlist(Cell cell)

Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.

Parameters:

cell - the cell to netlist

netlist

public static void netlist(Cell cell,
                           java.lang.String filename)

Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.

Parameters:

cell - the cell to netlist

filename - the (top-level) file to write the netlist in

netlist

public void netlist(boolean flat)

Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.

Parameters:

flat - whether the netlist should be flat

netlist

public void netlist(boolean flat,
                    java.lang.String filename)

Creates a netlist of the default variety determined by the techmapper

Parameters:

flat - whether the netlist should be flat

filename - the (top-level) file to write the netlist in

netlist

public static void netlist(Cell cell,
                           boolean flat)

Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.

Parameters:

cell - the cell to netlist

flat - whether the netlist should be flat

netlist

public static void netlist(Cell cell,
                           boolean flat,
                           java.lang.String filename)

Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister.

Parameters:

cell - the cell to netlist

flat - whether the netlist should be flat

filename - the (top-level) file to write the netlist in