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java.lang.Objectbyucc.jhdl.base.Nameable
byucc.jhdl.base.Node
byucc.jhdl.base.Cell
byucc.jhdl.base.Structural
byucc.jhdl.Logic.LogicGates
byucc.jhdl.Logic.LogicStatic
byucc.jhdl.Logic.Logic
byucc.jhdl.Xilinx.Virtex.Modules.SRLFifo
arbitrary-width, arbitrary depth FIFO based on shift registers (SRL16). This FIFO supports simultaneous read/write, full and empty status flags, and a data count.
Writing to a full FIFO will do nothing, even if the read_enable is asserted at the same time. Reading from an empty FIFO will return the last entry read from the non-empty fifo, or if the write_enable is asserted, the value just written to the FIFO
The actual number of FIFO entries is the address space - 1, i.e., 5 address bits = 2^5 - 1 = 31 entries. This is done to provide true empty/full status flags.
Note: Virtex currently only supports up to 15-deep (1 SRL)
Field Summary | |
static CellInterface[] |
cell_interface
cell's interface to the outside world |
static int |
SINGLE_BIT
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Fields inherited from class byucc.jhdl.Logic.Logic |
ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF |
Fields inherited from class byucc.jhdl.Logic.LogicGates |
tech_mapper |
Constructor Summary | |
SRLFifo(Node parent,
Wire fifo_init,
Wire write_enable,
Wire read_enable,
Wire write_data,
Wire full,
Wire empty,
Wire read_data,
Wire data_count)
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Method Summary | |
protected void |
build()
|
void |
clock()
Users define synchronous behavior in this method using standard JHDL constructs. |
protected BV |
compute()
|
boolean |
defaultSimulationModelIsBehavioral()
The default simulation model is structural for Structural cells. |
protected void |
getValues()
|
protected void |
initBehavioralModel()
|
void |
propagate()
Users defined propagatable behavior using standard JHDL constructs. |
protected void |
putValues()
|
void |
reset()
If you define a behavior, you must also define a reset method for resetting the synchonous part of your model. |
Methods inherited from class byucc.jhdl.base.Node |
addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock |
Methods inherited from class byucc.jhdl.base.Nameable |
caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber |
Methods inherited from class java.lang.Object |
clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait |
Field Detail |
public static final int SINGLE_BIT
public static CellInterface[] cell_interface
Constructor Detail |
public SRLFifo(Node parent, Wire fifo_init, Wire write_enable, Wire read_enable, Wire write_data, Wire full, Wire empty, Wire read_data, Wire data_count)
Method Detail |
public void reset()
Structural
reset
in interface Clockable
reset
in class Structural
public void clock()
Structural
clock
in interface Clockable
clock
in class Structural
public void propagate()
Structural
propagate
in interface byucc.jhdl.base.Propagateable
propagate
in class Structural
protected BV compute()
protected void getValues()
protected void putValues()
protected void initBehavioralModel()
public boolean defaultSimulationModelIsBehavioral()
Structural
defaultSimulationModelIsBehavioral
in class Structural
protected void build()
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