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java.lang.Objectbyucc.jhdl.base.Nameable
byucc.jhdl.base.Node
byucc.jhdl.base.Cell
byucc.jhdl.base.Structural
byucc.jhdl.Logic.LogicGates
byucc.jhdl.Logic.LogicStatic
byucc.jhdl.Logic.Logic
byucc.jhdl.Xilinx.Virtex.BlockRam
This class provides the functionality of the RAMB4_Sn and RAMB4_Sn_Sn Virtex library elements. Due to problems with single-ported and one-bit wide implementations, this class has been deprecated.
Field Summary | |
static CellInterface[] |
cell_interface
Deprecated. |
protected int[] |
contents
Deprecated. |
static CellInterface[] |
implicit_interface
Deprecated. |
Fields inherited from class byucc.jhdl.Logic.Logic |
ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF |
Fields inherited from class byucc.jhdl.Logic.LogicGates |
tech_mapper |
Fields inherited from class byucc.jhdl.base.Cell |
BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD |
Constructor Summary | |
BlockRam(Node parent,
Wire rst,
Wire en,
Wire din,
Wire we,
Wire addr,
Wire dout)
Deprecated. Constructs a new single-ported BlockRam. |
|
BlockRam(Node parent,
Wire rst,
Wire en,
Wire din,
Wire we,
Wire addr,
Wire dout,
java.lang.String name)
Deprecated. Constructs a new named, single-ported BlockRam. |
|
BlockRam(Node parent,
Wire rstA,
Wire enA,
Wire diA,
Wire weA,
Wire addrA,
Wire doA,
Wire rstB,
Wire enB,
Wire diB,
Wire weB,
Wire addrB,
Wire doB)
Deprecated. Constructs a new dual-ported BlockRam. |
|
BlockRam(Node parent,
Wire rstA,
Wire enA,
Wire diA,
Wire weA,
Wire addrA,
Wire doA,
Wire rstB,
Wire enB,
Wire diB,
Wire weB,
Wire addrB,
Wire doB,
java.lang.String name)
Deprecated. Constructs a new named, dual-ported BlockRam. |
|
BlockRam(Node parent,
Wire rstA,
Wire enA,
Wire diA,
Wire weA,
Wire addrA,
Wire doA,
Wire rstB,
Wire enB,
Wire diB,
Wire weB,
Wire addrB,
Wire doB,
Wire clkA,
Wire clkB)
Deprecated. Constructs a new named, dual-ported, multi-clock BlockRam. |
|
BlockRam(Node parent,
Wire rstA,
Wire enA,
Wire diA,
Wire weA,
Wire addrA,
Wire doA,
Wire rstB,
Wire enB,
Wire diB,
Wire weB,
Wire addrB,
Wire doB,
Wire clkA,
Wire clkB,
java.lang.String name)
Deprecated. Constructs a new named, dual-ported, multi-clock BlockRam. |
Method Summary | |
static int |
addrWidthFromDataWidth(int width)
Deprecated. |
boolean |
cellInterfaceDeterminesUniqueNetlistStructure()
Deprecated. When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. |
protected void |
connectImplicitPorts()
Deprecated. Connects the implicit ports. |
protected boolean |
defaultSimulationModelIsBehavioral()
Deprecated. The default simulation model is structural for Structural cells. |
java.lang.String |
getCellName()
Deprecated. Access the cell name associated with a derived class. |
boolean |
isNetlistLeaf()
Deprecated. A few rare cells are leafCells during netlisting, but not during simulation. |
Methods inherited from class byucc.jhdl.base.Node |
addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock |
Methods inherited from class byucc.jhdl.base.Nameable |
caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber |
Methods inherited from class java.lang.Object |
clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait |
Field Detail |
public static CellInterface[] implicit_interface
public static CellInterface[] cell_interface
protected int[] contents
Constructor Detail |
public BlockRam(Node parent, Wire rst, Wire en, Wire din, Wire we, Wire addr, Wire dout)
parent
- The parent Cell
to the BlockRamrst
- The Wire
to be connected to input port rsten
- The Wire
to be connected to input port endin
- The Wire
to be connected to input port dinwe
- The Wire
to be connected to input port weaddr
- The Wire
to be connected to input port addrdout
- The Wire
to be connected to output port doutpublic BlockRam(Node parent, Wire rst, Wire en, Wire din, Wire we, Wire addr, Wire dout, java.lang.String name)
parent
- The parent Cell
to the BlockRamrst
- The Wire
to be connected to input port rsten
- The Wire
to be connected to input port endin
- The Wire
to be connected to input port dinwe
- The Wire
to be connected to input port weaddr
- The Wire
to be connected to input port addrdout
- The Wire
to be connected to output port doutname
- Instance name of the BlockRampublic BlockRam(Node parent, Wire rstA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire rstB, Wire enB, Wire diB, Wire weB, Wire addrB, Wire doB)
parent
- The parent Cell
to the BlockRamrstA
- The Wire
to be connected to input port rstAenA
- The Wire
to be connected to input port enAdiA
- The Wire
to be connected to input port diAweA
- The Wire
to be connected to input port weAaddrA
- The Wire
to be connected to input port addrAdoA
- The Wire
to be connected to output port doArstB
- The Wire
to be connected to input port rstBenB
- The Wire
to be connected to input port enBdiB
- The Wire
to be connected to input port diBweB
- The Wire
to be connected to input port weBaddrB
- The Wire
to be connected to input port addrBdoB
- The Wire
to be connected to output port doBpublic BlockRam(Node parent, Wire rstA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire rstB, Wire enB, Wire diB, Wire weB, Wire addrB, Wire doB, java.lang.String name)
parent
- The parent Cell
to the BlockRamrstA
- The Wire
to be connected to input port rstAenA
- The Wire
to be connected to input port enAdiA
- The Wire
to be connected to input port diAweA
- The Wire
to be connected to input port weAaddrA
- The Wire
to be connected to input port addrAdoA
- The Wire
to be connected to output port doArstB
- The Wire
to be connected to input port rstBenB
- The Wire
to be connected to input port enBdiB
- The Wire
to be connected to input port diBweB
- The Wire
to be connected to input port weBaddrB
- The Wire
to be connected to input port addrBdoB
- The Wire
to be connected to output port doBname
- Instance name of the BlockRampublic BlockRam(Node parent, Wire rstA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire rstB, Wire enB, Wire diB, Wire weB, Wire addrB, Wire doB, Wire clkA, Wire clkB)
parent
- The parent Cell
to the BlockRamrstA
- The Wire
to be connected to input port rstAenA
- The Wire
to be connected to input port enAdiA
- The Wire
to be connected to input port diAweA
- The Wire
to be connected to input port weAaddrA
- The Wire
to be connected to input port addrAdoA
- The Wire
to be connected to output port doArstB
- The Wire
to be connected to input port rstBenB
- The Wire
to be connected to input port enBdiB
- The Wire
to be connected to input port diBweB
- The Wire
to be connected to input port weBaddrB
- The Wire
to be connected to input port addrBdoB
- The Wire
to be connected to output port doBclkA
- The Wire
to be connected to clock port clkAclkB
- The Wire
to be connected to clock port clkBpublic BlockRam(Node parent, Wire rstA, Wire enA, Wire diA, Wire weA, Wire addrA, Wire doA, Wire rstB, Wire enB, Wire diB, Wire weB, Wire addrB, Wire doB, Wire clkA, Wire clkB, java.lang.String name)
parent
- The parent Cell
to the BlockRamrstA
- The Wire
to be connected to input port rstAenA
- The Wire
to be connected to input port enAdiA
- The Wire
to be connected to input port diAweA
- The Wire
to be connected to input port weAaddrA
- The Wire
to be connected to input port addrAdoA
- The Wire
to be connected to output port doArstB
- The Wire
to be connected to input port rstBenB
- The Wire
to be connected to input port enBdiB
- The Wire
to be connected to input port diBweB
- The Wire
to be connected to input port weBaddrB
- The Wire
to be connected to input port addrBdoB
- The Wire
to be connected to output port doBclkA
- The Wire
to be connected to clock port clkAclkB
- The Wire
to be connected to clock port clkBname
- Instance name of the BlockRamMethod Detail |
protected void connectImplicitPorts()
Logic
#implicit_ports
.
If you used the old version of connect_implicit_ports, this method will use
reflection to see that the old version gets called correctly.
connectImplicitPorts
in class Logic
public java.lang.String getCellName()
Cell
getCellName
in class Cell
public boolean isNetlistLeaf()
Cell
isNetlistLeaf
in class Cell
public final boolean cellInterfaceDeterminesUniqueNetlistStructure()
Cell
cellInterfaceDeterminesUniqueNetlistStructure
in class Cell
protected boolean defaultSimulationModelIsBehavioral()
Structural
defaultSimulationModelIsBehavioral
in class Structural
public static int addrWidthFromDataWidth(int width)
|
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