byucc.jhdl.contrib.modgen.CordicPack
Class Z_Mux

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.contrib.modgen.CordicPack.Z_Mux

All Implemented Interfaces:

BooleanFlags, Clockable, byucc.jhdl.base.Propagateable, TreeListable

public class Z_Mux

extends Logic

Field Summary

static int	AND
static CellInterface[]	cell_interface
static int	SINGLE
static int	XOR

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, implicit_interface, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

Z_Mux(Node parent, int sel_gate_type, boolean registered, Wire clk_en, Wire a, Wire b, Wire sel0, Wire sel1, Wire s)

Method Summary

boolean

cellInterfaceDeterminesUniqueNetlistStructure() When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, connectImplicitPorts, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clock, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, defaultSimulationModelIsBehavioral, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagate, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, reset, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

cell_interface

public static CellInterface[] cell_interface

SINGLE

public static final int SINGLE

See Also:

Constant Field Values

AND

public static final int AND

See Also:

Constant Field Values

XOR

public static final int XOR

See Also:

Constant Field Values

Constructor Detail

Z_Mux

public Z_Mux(Node parent,
             int sel_gate_type,
             boolean registered,
             Wire clk_en,
             Wire a,
             Wire b,
             Wire sel0,
             Wire sel1,
             Wire s)

Method Detail

cellInterfaceDeterminesUniqueNetlistStructure

public boolean cellInterfaceDeterminesUniqueNetlistStructure()

Description copied from class: Cell

When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. Overriding this method to return true allows JHDL to save memory and netlists to be smaller by sharing the netlist structures that are guaranteed to be identical. NOTE: Do not override this unless every possible condition responsible for structural differences in a class (types and amount of children cells created, and arrangements of wires connected to ports) is included in the cellInterface[] of that class.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

false if not overridden, preventing all memory sharing