byucc.jhdl.Xilinx.Virtex
Class clkdllhf

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.Xilinx.Virtex.clkdllhf

All Implemented Interfaces:

BooleanFlags, Clockable, PreDefinedSchematic, byucc.jhdl.base.Propagateable, TreeListable, XilinxClock

public final class clkdllhf

extends Logic

implements XilinxClock, PreDefinedSchematic

CLKDLLHF is a high frequency clock delay locked loop used to minimize clock skew. CLKDLLHF synchronizes the clock signal at the feed back clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within 250 ps of each other. The frequency of the clock signal at the CLKIN input must be in the range 60 - 180 MHz. The CLKIN pin must be driven by an IBUFG or a BUFG. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG input can only be connected to the CLK0 output of CLKDLLHF. The BUFG connected to the CLKFB input of the CLKDLLHF must be sourced from the CLK0 output of the same CLKDLLHF. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Only the CLK0 output can be used. CLK0 must be connected to the input of OBUF, an output buffer. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted output (CLK180) is the same as that of the CLK0 output. The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal at the RST input is synchronized to the clock signal at the CLKIN input. The reset becomes effective at the second Low-to-High transition of the clock signal at the CLKIN input after assertion of the RST signal. (Source: XACT Libraries Guide, Chapter 4 CLKDLLHF, Xilinx Corporation,

Field Summary

static CellInterface[]	cell_interface The port interface for: clkdllhf clkin : clk (1) clkfb : clk (1) rst : in (1) clk0 : out (1) clk180 : out (1) clkdv : out (1) locked : out (1)
static java.lang.String	cellname The static cellname (netlist reference name) for clkdllhf
static CellInterface[]	implicit_interface

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.apps.Viewers.Schematic.PreDefinedSchematic

PreDefinedSchematic_ADD, PreDefinedSchematic_ADDSUB, PreDefinedSchematic_AND, PreDefinedSchematic_BUF, PreDefinedSchematic_CONST, PreDefinedSchematic_GEN, PreDefinedSchematic_GND, PreDefinedSchematic_INC, PreDefinedSchematic_INV, PreDefinedSchematic_MUX, PreDefinedSchematic_NAND, PreDefinedSchematic_NOR, PreDefinedSchematic_OR, PreDefinedSchematic_PULLDOWN, PreDefinedSchematic_PULLUP, PreDefinedSchematic_REG, PreDefinedSchematic_SHL, PreDefinedSchematic_SHR, PreDefinedSchematic_TBUF, PreDefinedSchematic_VCC, PreDefinedSchematic_XNOR, PreDefinedSchematic_XOR

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

protected	clkdllhf(Node parent) Used only by child classes to pass up the parent cell.
	clkdllhf(Node parent, ArgBlockList abl) Constructs a new clkdllhf, connecting its ports as given by the String-Wire pairs in the ArgBlockList.
protected	clkdllhf(Node parent, java.lang.String name) Used only by child classes to pass up the parent cell and instance name.
	clkdllhf(Node parent, java.lang.String instanceName, ArgBlockList abl) Constructs a new clkdllhf, connecting its ports as given by the String-Wire pairs in the ArgBlockList.
	clkdllhf(Node parent, java.lang.String instanceName, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4, java.lang.String s5, Wire w5, java.lang.String s6, Wire w6) Constructs a new clkdllhf, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.
	clkdllhf(Node parent, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4, java.lang.String s5, Wire w5, java.lang.String s6, Wire w6) Constructs a new clkdllhf, connecting each Wire to the port whose name is given by the accompanying String parameter
	clkdllhf(Node parent, java.lang.String instanceName, Wire clkin, Wire clkfb, Wire rst, Wire clk0, Wire clk180, Wire clkdv, Wire locked) Constructs a new clkdllhf.
	clkdllhf(Node parent, Wire clkin, Wire clkfb, Wire rst, Wire clk0, Wire clk180, Wire clkdv, Wire locked) Constructs a new clkdllhf.

Method Summary

boolean	cellInterfaceDeterminesUniqueNetlistStructure() When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.
protected void	connectImplicitPorts() Connects the implicit ports.
java.lang.String	determineSchedule(Wire clk) Returns a schedule for the given output wire.
java.lang.String	getCellName() Access the cell name associated with a derived class.
Wire	getInputWire() Returns the input wire that may need a pad.
boolean	isNetlistLeaf() A few rare cells are leafCells during netlisting, but not during simulation.
static void	main(java.lang.String[] argv)
protected boolean	preorderCheck() Used to check validity of this cell before recursing down.
static void	test()
int	type() This method returns one of the predefined schematic constants to identify the type of this cell.

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clock, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, defaultSimulationModelIsBehavioral, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagate, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, reset, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

cellname

public static final java.lang.String cellname

The static cellname (netlist reference name) for clkdllhf

See Also:

Constant Field Values

cell_interface

public static CellInterface[] cell_interface

The port interface for: clkdllhf clkin : clk (1) clkfb : clk (1) rst : in (1) clk0 : out (1) clk180 : out (1) clkdv : out (1) locked : out (1)

implicit_interface

public static CellInterface[] implicit_interface

Constructor Detail

clkdllhf

protected clkdllhf(Node parent)

Used only by child classes to pass up the parent cell.

Parameters:

parent - Parent cell

clkdllhf

protected clkdllhf(Node parent,
                   java.lang.String name)

Used only by child classes to pass up the parent cell and instance name.

Parameters:

parent - Parent cell

name - Instance name of the cell

clkdllhf

public clkdllhf(Node parent,
                Wire clkin,
                Wire clkfb,
                Wire rst,
                Wire clk0,
                Wire clk180,
                Wire clkdv,
                Wire locked)

Constructs a new clkdllhf.

Parameters:

parent - The parent Cell to the clkdllhf

clkin - The Wire to be connected to clock port clkin

clkfb - The Wire to be connected to clock port clkfb

rst - The Wire to be connected to input port rst

clk0 - The Wire to be connected to output port clk0

clk180 - The Wire to be connected to output port clk180

clkdv - The Wire to be connected to output port clkdv

locked - The Wire to be connected to output port locked

clkdllhf

public clkdllhf(Node parent,
                java.lang.String instanceName,
                Wire clkin,
                Wire clkfb,
                Wire rst,
                Wire clk0,
                Wire clk180,
                Wire clkdv,
                Wire locked)

Constructs a new clkdllhf. The initial String parameter specifies the instance name.

Parameters:

parent - The parent Cell to the clkdllhf

instanceName - The instance name of the clkdllhf

clkin - The Wire to be connected to clock port clkin

clkfb - The Wire to be connected to clock port clkfb

rst - The Wire to be connected to input port rst

clk0 - The Wire to be connected to output port clk0

clk180 - The Wire to be connected to output port clk180

clkdv - The Wire to be connected to output port clkdv

locked - The Wire to be connected to output port locked

clkdllhf

public clkdllhf(Node parent,
                java.lang.String s0,
                Wire w0,
                java.lang.String s1,
                Wire w1,
                java.lang.String s2,
                Wire w2,
                java.lang.String s3,
                Wire w3,
                java.lang.String s4,
                Wire w4,
                java.lang.String s5,
                Wire w5,
                java.lang.String s6,
                Wire w6)

Constructs a new clkdllhf, connecting each Wire to the port whose name is given by the accompanying String parameter

Parameters:

parent - The parent Cell to the clkdllhf

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

s4 - The name of the port to which w4 will be connected

w4 - The Wire to be connected to the port specified by s4

s5 - The name of the port to which w5 will be connected

w5 - The Wire to be connected to the port specified by s5

s6 - The name of the port to which w6 will be connected

w6 - The Wire to be connected to the port specified by s6

clkdllhf

public clkdllhf(Node parent,
                java.lang.String instanceName,
                java.lang.String s0,
                Wire w0,
                java.lang.String s1,
                Wire w1,
                java.lang.String s2,
                Wire w2,
                java.lang.String s3,
                Wire w3,
                java.lang.String s4,
                Wire w4,
                java.lang.String s5,
                Wire w5,
                java.lang.String s6,
                Wire w6)

Constructs a new clkdllhf, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

Parameters:

parent - The parent Cell to the clkdllhf

instanceName - The instance name of the clkdllhf

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

s4 - The name of the port to which w4 will be connected

w4 - The Wire to be connected to the port specified by s4

s5 - The name of the port to which w5 will be connected

w5 - The Wire to be connected to the port specified by s5

s6 - The name of the port to which w6 will be connected

w6 - The Wire to be connected to the port specified by s6

clkdllhf

public clkdllhf(Node parent,
                ArgBlockList abl)

Constructs a new clkdllhf, connecting its ports as given by the String-Wire pairs in the ArgBlockList. Any generic assignments are made through String-String pairs in the ArgBlockList.

Parameters:

parent - The parent Cell to the clkdllhf

abl - The list of String-Wire pairs for port assignments, and String-String pairs for generic assignments.

clkdllhf

public clkdllhf(Node parent,
                java.lang.String instanceName,
                ArgBlockList abl)

Constructs a new clkdllhf, connecting its ports as given by the String-Wire pairs in the ArgBlockList. Any generic assignments are made through String-String pairs in the ArgBlockList. The initial String parameter is the instance name.

Parameters:

parent - The parent Cell to the clkdllhf

instanceName - The instance name of the clkdllhf

abl - The list of String-Wire pairs for port assignments, and String-String pairs for generic assignments.

Method Detail

getCellName

public java.lang.String getCellName()

Description copied from class: Cell

Access the cell name associated with a derived class. The cellname field is lazily evaluated on the first call of this method. Can be overriden to make cellname different by instance. If the field does not exist, this defaults to the classname.

Overrides:

getCellName in class Cell

Returns:

the cell name associated with a derived class, null if not declared.

connectImplicitPorts

protected void connectImplicitPorts()

Description copied from class: Logic

Connects the implicit ports. Override this if you shadow #implicit_ports. If you used the old version of connect_implicit_ports, this method will use reflection to see that the old version gets called correctly.

Overrides:

connectImplicitPorts in class Logic

cellInterfaceDeterminesUniqueNetlistStructure

public final boolean cellInterfaceDeterminesUniqueNetlistStructure()

Description copied from class: Cell

When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. Overriding this method to return true allows JHDL to save memory and netlists to be smaller by sharing the netlist structures that are guaranteed to be identical. NOTE: Do not override this unless every possible condition responsible for structural differences in a class (types and amount of children cells created, and arrangements of wires connected to ports) is included in the cellInterface[] of that class.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

false if not overridden, preventing all memory sharing

type

public int type()

Description copied from interface: PreDefinedSchematic

This method returns one of the predefined schematic constants to identify the type of this cell.

Specified by:

type in interface PreDefinedSchematic

Returns:

A predefined schematic constant

isNetlistLeaf

public boolean isNetlistLeaf()

Description copied from class: Cell

A few rare cells are leafCells during netlisting, but not during simulation. Overriding this method should allow that behavior.

Overrides:

isNetlistLeaf in class Cell

Returns:

true is this cell is a leaf during netlisting, false otherwise.

preorderCheck

protected boolean preorderCheck()

Description copied from class: Cell

Used to check validity of this cell before recursing down. Checks that every VP connected in children was created or ported at this level. Extend this to check for further conditions.

Overrides:

preorderCheck in class Cell

Returns:

true if no errors occured, false otherwise.

See Also:

Node#checkAllNodes().

getInputWire

public final Wire getInputWire()

Description copied from interface: XilinxClock

Returns the input wire that may need a pad.

Specified by:

getInputWire in interface XilinxClock

Returns:

the input wire to this clock component

determineSchedule

public java.lang.String determineSchedule(Wire clk)

Description copied from interface: XilinxClock

Returns a schedule for the given output wire.

Specified by:

determineSchedule in interface XilinxClock

Parameters:

clk - the clock wire to determine a schedule for

Returns:

A string containing its schedule

main

public static void main(java.lang.String[] argv)

test

public static void test()