byucc.jhdl.Xilinx.Virtex2.RamPack
Class BlockRamViewL

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.Xilinx.Virtex2.RamPack.BlockRamViewL

All Implemented Interfaces:

BooleanFlags, Clockable, MemoryInterface, MemoryUpdatable, byucc.jhdl.base.Propagateable, TreeListable

public class BlockRamViewL

extends Logic

implements MemoryInterface, MemoryUpdatable

This class is for the simulation of block ram's to work correctly. Do not instance this class directly.

Field Summary

static CellInterface[]	cell_interface
static CellInterface[]	implicit_interface
static int	READ_FIRST
static int	WRITE_FIRST

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

BlockRamViewL(Node parent, Wire rst, Wire en, Wire din, Wire we, Wire addr, Wire dout, java.lang.String name, long[] contents, long[] contentsP)

BlockRamViewL(Node parent, Wire rst, Wire en, Wire din, Wire we, Wire addr, Wire dout, java.lang.String name, long[] contents, long[] contentsP, boolean connect_implicit_ports)

BlockRamViewL(Node parent, Wire rst, Wire en, Wire din, Wire we, Wire addr, Wire dout, java.lang.String name, long[] contents, long[] contentsP, boolean connect_implicit_ports, int write_mode)

BlockRamViewL(Node parent, Wire rst, Wire en, Wire din, Wire we, Wire addr, Wire dout, java.lang.String name, long[] contents, long[] contentsP, int write_mode)

BlockRamViewL(Node parent, Wire clk, Wire rst, Wire en, Wire din, Wire we, Wire addr, Wire dout, java.lang.String name, long[] contents, long[] contentsP)

BlockRamViewL(Node parent, Wire clk, Wire rst, Wire en, Wire din, Wire we, Wire addr, Wire dout, java.lang.String name, long[] contents, long[] contentsP, int write_mode)

Method Summary

static int	addrWidthFromDataWidth(int width)
boolean	cellInterfaceDeterminesUniqueNetlistStructure() When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.
void	clock() Users define synchronous behavior in this method using standard JHDL constructs.
void	connectImplicitPorts() Connects the implicit ports.
boolean	defaultSimulationModelIsBehavioral() The default simulation model is structural for Structural cells.
BV	getMemoryElement(int addr) Return the given memory position
BV[]	getMemoryRange(int sIndex, int elements) Return the given memory range
int	getMemoryWidth() Returns the memory width
long	getSize() Returns the memory size
boolean	isNetlistLeaf() A few rare cells are leafCells during netlisting, but not during simulation.
static int	parityWidthFromDataWidth(int width)
void	reset() If you define a behavior, you must also define a reset method for resetting the synchonous part of your model.
void	update()

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagate, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

WRITE_FIRST

public static final int WRITE_FIRST

See Also:

Constant Field Values

READ_FIRST

public static final int READ_FIRST

See Also:

Constant Field Values

implicit_interface

public static CellInterface[] implicit_interface

cell_interface

public static CellInterface[] cell_interface

Constructor Detail

BlockRamViewL

public BlockRamViewL(Node parent,
                     Wire clk,
                     Wire rst,
                     Wire en,
                     Wire din,
                     Wire we,
                     Wire addr,
                     Wire dout,
                     java.lang.String name,
                     long[] contents,
                     long[] contentsP)

BlockRamViewL

public BlockRamViewL(Node parent,
                     Wire clk,
                     Wire rst,
                     Wire en,
                     Wire din,
                     Wire we,
                     Wire addr,
                     Wire dout,
                     java.lang.String name,
                     long[] contents,
                     long[] contentsP,
                     int write_mode)

BlockRamViewL

public BlockRamViewL(Node parent,
                     Wire rst,
                     Wire en,
                     Wire din,
                     Wire we,
                     Wire addr,
                     Wire dout,
                     java.lang.String name,
                     long[] contents,
                     long[] contentsP)

BlockRamViewL

public BlockRamViewL(Node parent,
                     Wire rst,
                     Wire en,
                     Wire din,
                     Wire we,
                     Wire addr,
                     Wire dout,
                     java.lang.String name,
                     long[] contents,
                     long[] contentsP,
                     int write_mode)

BlockRamViewL

public BlockRamViewL(Node parent,
                     Wire rst,
                     Wire en,
                     Wire din,
                     Wire we,
                     Wire addr,
                     Wire dout,
                     java.lang.String name,
                     long[] contents,
                     long[] contentsP,
                     boolean connect_implicit_ports)

BlockRamViewL

public BlockRamViewL(Node parent,
                     Wire rst,
                     Wire en,
                     Wire din,
                     Wire we,
                     Wire addr,
                     Wire dout,
                     java.lang.String name,
                     long[] contents,
                     long[] contentsP,
                     boolean connect_implicit_ports,
                     int write_mode)

Method Detail

isNetlistLeaf

public boolean isNetlistLeaf()

Description copied from class: Cell

A few rare cells are leafCells during netlisting, but not during simulation. Overriding this method should allow that behavior.

Overrides:

isNetlistLeaf in class Cell

Returns:

true is this cell is a leaf during netlisting, false otherwise.

connectImplicitPorts

public void connectImplicitPorts()

Description copied from class: Logic

Connects the implicit ports. Override this if you shadow #implicit_ports. If you used the old version of connect_implicit_ports, this method will use reflection to see that the old version gets called correctly.

Overrides:

connectImplicitPorts in class Logic

cellInterfaceDeterminesUniqueNetlistStructure

public boolean cellInterfaceDeterminesUniqueNetlistStructure()

Description copied from class: Cell

When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. Overriding this method to return true allows JHDL to save memory and netlists to be smaller by sharing the netlist structures that are guaranteed to be identical. NOTE: Do not override this unless every possible condition responsible for structural differences in a class (types and amount of children cells created, and arrangements of wires connected to ports) is included in the cellInterface[] of that class.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

false if not overridden, preventing all memory sharing

addrWidthFromDataWidth

public static int addrWidthFromDataWidth(int width)

parityWidthFromDataWidth

public static int parityWidthFromDataWidth(int width)

defaultSimulationModelIsBehavioral

public boolean defaultSimulationModelIsBehavioral()

Description copied from class: Structural

The default simulation model is structural for Structural cells. If the default should be behavioral, the user will need to overload this method to return true in cases besides TestBenches or leaf cells.

Overrides:

defaultSimulationModelIsBehavioral in class Structural

Returns:

true if TestBench or leafCell, false otherwise.

clock

public void clock()

Description copied from class: Structural

Users define synchronous behavior in this method using standard JHDL constructs. The simulator detects whether clock() has been implemented by calling this function directly and checking for an exception.

Specified by:

clock in interface Clockable

Overrides:

clock in class Structural

update

public void update()

Specified by:

update in interface MemoryUpdatable

reset

public void reset()

Description copied from class: Structural

If you define a behavior, you must also define a reset method for resetting the synchonous part of your model. If the user forgets to implement this, he will be reminded at simulation time.

Specified by:

reset in interface Clockable

Overrides:

reset in class Structural

getMemoryRange

public BV[] getMemoryRange(int sIndex,
                           int elements)

Description copied from interface: MemoryInterface

Return the given memory range

Specified by:

getMemoryRange in interface MemoryInterface

Parameters:

sIndex - the starting index

elements - how many entries to get

Returns:

the modified results

getMemoryElement

public BV getMemoryElement(int addr)

Description copied from interface: MemoryInterface

Return the given memory position

Specified by:

getMemoryElement in interface MemoryInterface

Parameters:

addr - the memory address to get

Returns:

the modified results

getSize

public long getSize()

Description copied from interface: MemoryInterface

Returns the memory size

Specified by:

getSize in interface MemoryInterface

Returns:

the number of addresses

getMemoryWidth

public int getMemoryWidth()

Description copied from interface: MemoryInterface

Returns the memory width

Specified by:

getMemoryWidth in interface MemoryInterface

Returns:

the number of bits per address