byucc.jhdl.Logic.Modules
Class Cordic

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.Logic.Modules.Cordic

All Implemented Interfaces:

BooleanFlags, Clockable, byucc.jhdl.base.Propagateable, TreeListable

public class Cordic

extends Logic

Generic width CORDIC unit which is technology independence. The CORDIC is parameterized with respect to wordsize, number of iterations, pipeline depth, angle type, and CORDIC function. Hardware to extend the domain of the CORDIC to +/-180 degrees can also be generated.

For an introduction to CORDIC processors, see Andraka, Ray. A survey of CORDIC algorithms for FPGA based computers.

Implementation

CORDIC units can have a maximum wordsize of 32 bits, and a maximum number of iterations = 31. All the input x,y,z and output x,y,z must be the same wordsize.

Selecting Cordic function and angle type

The function and angle type of the CORDIC is selected by passing predefined constants from the Cordic class to the constructor. These constants are listed below.

Modes:
• Cordic.UNIFIED: Unified mode CORDIC
• Cordic.ROTATIONAL: Rotational mode CORDIC
• Cordic.VECTOR: Vector mode CORDIC

Angle types:
• Cordic.DEGREE: Degrees
• Cordic.RADIANS: Radians
• Cordic.FRACTIONS: Fractions of rotation. .25 = 90 degrees.

Pipelining

Pipelining is enabled by setting the registered parameter true and selecting a pipe_depth. The pipe_depth of the CORDIC determines how many stages of the CORDIC are paired with a pipeline register.
In order to determine the latency of the pipe, find the number of stages in the CORDIC and divide that number by the pipe_depth. If there is a remainder, add 1. The short pipe stage resulting from a remainder in this computation is always placed at the inputs of the CORDIC.
The number of stages in the CORDIC can be determined by the following method:
First, take the number of iterations.
For UNIFIED and VECTOR mode, add two stages if initial rotations are enabled (see below for explanation of initial rotations).
For ROTATIONAL mode with a degree type other than FRACTION, add two stages if initial rotations is enabled, but small initial rotations is not (see below for explanation of initial rotations).
For ROTATIONAL mode with a degree type of FRACTION add one stage if initial rotations is enabled and small initial rotations is not.
ROTATIONAL mode with a degree type of FRACTIONS and both initial rotations and small initial rotations enabled is identical to a ROTATIONAL CORDIC without any initial rotations, so add 0 in that case.

The registers in the pipe can be stalled using a clk_en signal. clk_en can be passed in null for a perpetually enabled design. An exception will be thrown if clk_en is present when the CORDIC is unregistered.

Initial Rotations

Because the CORDIC algorithm is based on a tangent function, the domain and range of the input and output angles is restricted to +/- 90 degrees. This can be extended by enabling initial rotations hardware. Initial rotations hardware adds 1-2 extra computational stages to the CORDIC to correct inputs and outputs.

There are two types of initial rotations hardware. The first is normal initial rotations, which takes operands in any quadrant of the Cartesian plane and returns the correct outputs. The second is small initial rotations. This mode allows inputs from any quadrant, but restricts the range of input and output angles to +/- 90 degrees. Positions in the left half of the Cartesian plane are represented with a negative magnitude for polar notation (output of VECTOR mode, input of ROTATIONAL mode). Rectangular inputs and outputs are unchanged in their representation.

Operand Format

CORDIC processors have a growth factor of approximately 1.647 associated with their computation on x,y operands. For this reason, all x,y inputs must allow both a sign bit and growth bit at the most significant positions of the input words.

Angles are formatted in fixed point notation according to the following table:

s=sign bit x=normal bit

	FRACTION	DEGREE	RADIAN
Normal	.sxxxx...	sxxxxxxx.xxxx...	sx.xxxx...
Initial Rotations	s.xxxx...	sxxxxxxxx.xxxx...	sxx.xxxx...
Small Initial Rotations	.sxxxx...	sxxxxxxx.xxxx...	sx.xxxx...

Author:

Dan Baker

Field Summary

static CellInterface[]	cell_interface
static int	DEGREE
static int	FRACTION
static int	RADIAN
static int	ROTATIONAL
static int	UNIFIED The default simulation model is behavioral
static int	VECTOR

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, implicit_interface, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

Cordic(Node parent, int cordicmode, int angletype, boolean registered, int num_iter, int pipe_depth, boolean init_rots, boolean small_ir, Wire clk_en, Wire vec, Wire xin, Wire yin, Wire zin, Wire xout, Wire yout, Wire zout)
Constructor for CORDIC unit

Method Summary

boolean	cellInterfaceDeterminesUniqueNetlistStructure() When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.
void	clock() Users define synchronous behavior in this method using standard JHDL constructs.
static int[]	compute(int width, int num_iterations, int cordicmode, int angletype, boolean init_rot, boolean small_rt, int x, int y, int z, int v) Compute implements the behavior of the CORDIC for behavioral modelling of the circuit
void	propagate() Users defined propagatable behavior using standard JHDL constructs.
void	reset() If you define a behavior, you must also define a reset method for resetting the synchonous part of your model.

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, connectImplicitPorts, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, defaultSimulationModelIsBehavioral, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

cell_interface

public static CellInterface[] cell_interface

UNIFIED

public static final int UNIFIED

The default simulation model is behavioral

See Also:

Constant Field Values

ROTATIONAL

public static final int ROTATIONAL

See Also:

Constant Field Values

VECTOR

public static final int VECTOR

See Also:

Constant Field Values

FRACTION

public static final int FRACTION

See Also:

Constant Field Values

DEGREE

public static final int DEGREE

See Also:

Constant Field Values

RADIAN

public static final int RADIAN

See Also:

Constant Field Values

Constructor Detail

Cordic

public Cordic(Node parent,
              int cordicmode,
              int angletype,
              boolean registered,
              int num_iter,
              int pipe_depth,
              boolean init_rots,
              boolean small_ir,
              Wire clk_en,
              Wire vec,
              Wire xin,
              Wire yin,
              Wire zin,
              Wire xout,
              Wire yout,
              Wire zout)

Constructor for CORDIC unit

Parameters:

parent - Parent of this circuit

cordicmode - Cordic.UNIFIED,Cordic.ROTATIONAL, or Cordic.VECTOR. UNIFIED will do both modes of operation, with the control signal passed on the vec wire (1 for vector mode, 0 for rotational mode). Vector mode will do rectangular to polar conversions, Rotational mode does polar to rectangular conversions.

angletype - Cordic.FRACTION, Cordic.DEGREE, or Cordic.RADIAN to select which type of angles to use in the CORDIC

registered - True to add registers to the CORDIC

num_iter - Number of iterations to build. The maximum is wordsize-1

pipe_depth - Number of iterations per pipeline register. 1 for fully pipelined. This parameter has no meaning if registered = false.

init_rots - True to add initial rotation hardware to the CORDIC to extend the domain to +/-180 degrees.

small_ir - True to constrain input and output angles to +/-90 degress when using initial rotations. Points in the left half plane are represented with a negative magnitude.

clk_en - Clock enable wire for the registers.

vec - Control wire for Unified mode CORDIC

xin - X input

yin - Y input

zin - Angle input

xout - X output

yout - Y output

zout - Angle output

Method Detail

cellInterfaceDeterminesUniqueNetlistStructure

public boolean cellInterfaceDeterminesUniqueNetlistStructure()

Description copied from class: Cell

When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. Overriding this method to return true allows JHDL to save memory and netlists to be smaller by sharing the netlist structures that are guaranteed to be identical. NOTE: Do not override this unless every possible condition responsible for structural differences in a class (types and amount of children cells created, and arrangements of wires connected to ports) is included in the cellInterface[] of that class.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

false if not overridden, preventing all memory sharing

reset

public void reset()

Description copied from class: Structural

If you define a behavior, you must also define a reset method for resetting the synchonous part of your model. If the user forgets to implement this, he will be reminded at simulation time.

Specified by:

reset in interface Clockable

Overrides:

reset in class Structural

compute

public static int[] compute(int width,
                            int num_iterations,
                            int cordicmode,
                            int angletype,
                            boolean init_rot,
                            boolean small_rt,
                            int x,
                            int y,
                            int z,
                            int v)

Compute implements the behavior of the CORDIC for behavioral modelling of the circuit

Parameters:

width - Wordsize of the CORDIC

num_iterations - Number of iterations

cordicmode - Cordic.UNIFIED, Cordic.ROTATIONAL, or Cordic.VECTOR. See constructor for details.

angletype - Cordic.FRACTION,Cordic.DEGREE,or Cordic.RADIAN. See constructor for details.

init_rot - True for additional hardware to extend the domain of the circuit to +/-180 degrees.

small_rt - True to constrain input and output angles to the range +/- 90 degrees. Points in the left half plane are represented with a negative magnitude.

x - X input.

y - Y input.

z - Angle input.

v - Control signal for unified mode.

Returns:

Array of integers containing the output x,y, and angle of the CORDIC.

propagate

public void propagate()

Description copied from class: Structural

Users defined propagatable behavior using standard JHDL constructs. The simulator detects whether propagate() has been implemented by calling function directly and checking for an exception.

Specified by:

propagate in interface byucc.jhdl.base.Propagateable

Overrides:

propagate in class Structural

clock

public void clock()

Description copied from class: Structural

Users define synchronous behavior in this method using standard JHDL constructs. The simulator detects whether clock() has been implemented by calling this function directly and checking for an exception.

Specified by:

clock in interface Clockable

Overrides:

clock in class Structural