byucc.jhdl.Xilinx.Virtex.Modules
Class ramrom

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.Xilinx.Virtex.Modules.ramrom

All Implemented Interfaces:

BooleanFlags, Clockable, LargeMemoryInterface, LargeWritableMemory, MemoryInterface, byucc.jhdl.base.Propagateable, TreeListable

public class ramrom

extends Logic

implements MemoryInterface, LargeWritableMemory

Generic Ram or Rom generator

Ramrom generates a synchronous or asynchronous ram, a dual-ported ram, or a rom up to 256X64 in size. The size of the ram or rom with address size "a" and output size "o" is 2^aXo. If it is a ram, the input must be the same size as the output, otherwise an exception is thrown. Passing true for the "synch" parameter gives you a synchronous ram (synchronous write, asynchronous read), otherwise it is asynchronous. The ram or rom can be initialized by passing in an array of longs. The default initialization of the memory cells is all zeros unless an init array is passed. The size of the init array can be no bigger than 2^a, otherwise an exception is thrown. If it is smaller than 2^a, then zeros are filled into the high order rom cells. If any init value represents a value larger than can be stored in the ram or rom, an exception is thrown.

Implementation

All Technologies

If the address size is from 1-5, this module simply instantiates the appropriate ram or rom. If the address size is from 5 (for the dual-ported ram) to 8, it instantiates multiple rams or roms and uses muxes to select the appropriate output. Also, the rams make use of LUTS to generate the appropriate write-enable signal for each of the rams. Any size address that isn't between 1 and 8 causes an exception to be thrown.

Xilinx XC4000

CLB count:

Fill in the fields below and press compute

Bus Width (default 1):

Address Size (Valid values are 1 to 8, default 1):

Type of Cell ROM Single Ported RAM Dual Ported RAM

Number of CLB's required:

Xilinx Virtex

Slice count: The slice count and placement will be about the same as the XC4000 CLB count

Version:

2.0

Author:

Tim Wheeler

Field Summary

static CellInterface[]

cell_interface

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, implicit_interface, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

ramrom(Node parent, Wire a, Wire o, int[] contents)

ramrom(Node parent, Wire a, Wire o, int[] contents, java.lang.String name)

ramrom(Node parent, Wire a, Wire o, long[] contents)

ramrom(Node parent, Wire a, Wire o, long[] contents, java.lang.String name)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire o, boolean synch)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire o, boolean synch, int[] contents)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire o, boolean synch, int[] contents, java.lang.String name)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire o, boolean synch, long[] contents)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire o, boolean synch, long[] contents, java.lang.String name)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire o, boolean synch, java.lang.String name)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire dpra, Wire spo, Wire dpo)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire dpra, Wire spo, Wire dpo, int[] contents)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire dpra, Wire spo, Wire dpo, int[] contents, java.lang.String name)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire dpra, Wire spo, Wire dpo, long[] contents)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire dpra, Wire spo, Wire dpo, long[] contents, java.lang.String name)

ramrom(Node parent, Wire d, Wire we, Wire a, Wire dpra, Wire spo, Wire dpo, java.lang.String name)

Method Summary

static int	compute() No computation necessary in this class, so compute always returns a zero
protected boolean	defaultSimulationModelIsBehavioral() Default simulation model is behavioral
BV	getMemoryElement(int addr) Return the given memory position
BV	getMemoryElement(int addr, BV data) Return the given memory position
BV[]	getMemoryRange(int sIndex, int elements) Return the given memory range
BV[]	getMemoryRange(int sIndex, int elements, BV[] data) Return the given memory range
int	getMemoryWidth() Returns the memory width
long	getSize() Returns the memory size
boolean	loadMemoryFile(java.lang.String filename)
void	reset() Resets the output to zero
void	writeMemoryElement(int addr, BV value)
void	writeMemoryRange(int addr, int elements, BV[] values)

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, connectImplicitPorts, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clock, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagate, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, cellInterfaceDeterminesUniqueNetlistStructure, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

cell_interface

public static CellInterface[] cell_interface

Constructor Detail

ramrom

public ramrom(Node parent,
              Wire a,
              Wire o,
              int[] contents)

ramrom

public ramrom(Node parent,
              Wire a,
              Wire o,
              int[] contents,
              java.lang.String name)

ramrom

public ramrom(Node parent,
              Wire a,
              Wire o,
              long[] contents)

ramrom

public ramrom(Node parent,
              Wire a,
              Wire o,
              long[] contents,
              java.lang.String name)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire o,
              boolean synch)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire o,
              boolean synch,
              java.lang.String name)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire o,
              boolean synch,
              int[] contents)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire o,
              boolean synch,
              int[] contents,
              java.lang.String name)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire o,
              boolean synch,
              long[] contents)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire o,
              boolean synch,
              long[] contents,
              java.lang.String name)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire dpra,
              Wire spo,
              Wire dpo)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire dpra,
              Wire spo,
              Wire dpo,
              java.lang.String name)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire dpra,
              Wire spo,
              Wire dpo,
              int[] contents)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire dpra,
              Wire spo,
              Wire dpo,
              int[] contents,
              java.lang.String name)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire dpra,
              Wire spo,
              Wire dpo,
              long[] contents)

ramrom

public ramrom(Node parent,
              Wire d,
              Wire we,
              Wire a,
              Wire dpra,
              Wire spo,
              Wire dpo,
              long[] contents,
              java.lang.String name)

Method Detail

getMemoryRange

public BV[] getMemoryRange(int sIndex,
                           int elements)

Description copied from interface: MemoryInterface

Return the given memory range

Specified by:

getMemoryRange in interface MemoryInterface

Parameters:

sIndex - the starting index

elements - how many entries to get

Returns:

the modified results

getMemoryElement

public BV getMemoryElement(int addr)

Description copied from interface: MemoryInterface

Return the given memory position

Specified by:

getMemoryElement in interface MemoryInterface

Parameters:

addr - the memory address to get

Returns:

the modified results

getSize

public long getSize()

Description copied from interface: MemoryInterface

Returns the memory size

Specified by:

getSize in interface MemoryInterface

Returns:

the number of addresses

getMemoryWidth

public int getMemoryWidth()

Description copied from interface: MemoryInterface

Returns the memory width

Specified by:

getMemoryWidth in interface MemoryInterface

Returns:

the number of bits per address

getMemoryRange

public BV[] getMemoryRange(int sIndex,
                           int elements,
                           BV[] data)

Description copied from interface: LargeMemoryInterface

Return the given memory range

Specified by:

getMemoryRange in interface LargeMemoryInterface

Parameters:

sIndex - the starting index

elements - how many entries to get

data - where to stick the results

Returns:

the modified results

getMemoryElement

public BV getMemoryElement(int addr,
                           BV data)

Description copied from interface: LargeMemoryInterface

Return the given memory position

Specified by:

getMemoryElement in interface LargeMemoryInterface

Parameters:

addr - the memory address to get

data - where to stick the results

Returns:

the modified results

loadMemoryFile

public boolean loadMemoryFile(java.lang.String filename)

Specified by:

loadMemoryFile in interface LargeWritableMemory

writeMemoryRange

public void writeMemoryRange(int addr,
                             int elements,
                             BV[] values)

Specified by:

writeMemoryRange in interface LargeWritableMemory

writeMemoryElement

public void writeMemoryElement(int addr,
                               BV value)

Specified by:

writeMemoryElement in interface LargeWritableMemory

reset

public void reset()

Resets the output to zero

Specified by:

reset in interface Clockable

Overrides:

reset in class Structural

defaultSimulationModelIsBehavioral

protected boolean defaultSimulationModelIsBehavioral()

Default simulation model is behavioral

Overrides:

defaultSimulationModelIsBehavioral in class Structural

Returns:

true if TestBench or leafCell, false otherwise.

compute

public static int compute()

No computation necessary in this class, so compute always returns a zero