byucc.jhdl.Xilinx
Class XilinxCL

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.Xilinx.XilinxCL

All Implemented Interfaces:

BooleanFlags, Clockable, byucc.jhdl.base.Propagateable, TreeListable

Direct Known Subclasses:

add1, adder, adder, adder, adder, adderSubtractor, adderSubtractor, adderSubtractor, adderSubtractor, adsu1, And_fmap_g, And_fmap_g, And_fmap_g, and2, and2, and2, and2, and2_g, and2_g, and2_g, and2_g, and2b1, and2b1, and2b1, and2b1, and2b2, and2b2, and2b2, and2b2, and3, and3, and3, and3, and3_g, and3_g, and3_g, and3_g, and3b1, and3b1, and3b1, and3b1, and3b2, and3b2, and3b2, and3b2, and3b3, and3b3, and3b3, and3b3, and4, and4, and4, and4, and4_g, and4_g, and4_g, and4_g, and4b1, and4b1, and4b1, and4b1, and4b2, and4b2, and4b2, and4b2, and4b3, and4b3, and4b3, and4b3, and4b4, and4b4, and4b4, and4b4, and5, and5, and5, and5, and5_g, and6, and6, and6, and6, and6_g, and7, and7, and7, and7, and7_g, and8, and8, and8, and8, and8_g, and9, and9, and9, and9, and9_g, andX, andX, andX, andX, andX_g, andX_g, andX_g, buf, buf, buf, buf, buf_g, buf_g, buf_g, buf_g, bufe, bufe, bufe, bufe, bufgdll, bufgs, bufgsr, buft, buft, buft, buft, buft_g, buft_g, buft_g, buft_g, Constant, cy4, cy4_ADD_F_CI, cy4_ADD_FG_CI, cy4_ADD_G_CI, cy4_ADD_G_F1, cy4_ADD_G_F3_, cy4_ADDSUB_F_CI, cy4_ADDSUB_FG_CI, cy4_ADDSUB_G_CI, cy4_ADDSUB_G_F1, cy4_ADDSUB_G_F3_, cy4_DEC_F_CI, cy4_DEC_FG_0, cy4_DEC_FG_CI, cy4_DEC_G_0, cy4_DEC_G_CI, cy4_DEC_G_F1, cy4_DEC_G_F3_, cy4_EXAMINE_CI, cy4_FORCE_0, cy4_FORCE_1, cy4_FORCE_CI, cy4_FORCE_F1, cy4_FORCE_F3_, cy4_INC_F_CI, cy4_INC_FG_1, cy4_INC_FG_CI, cy4_INC_G_1, cy4_INC_G_CI, cy4_INC_G_F1, cy4_INC_G_F3_, cy4_INCDEC_F_CI, cy4_INCDEC_FG_1, cy4_INCDEC_FG_CI, cy4_INCDEC_G_0, cy4_INCDEC_G_CI, cy4_INCDEC_G_F1, cy4_mode, cy4_SUB_F_CI, cy4_SUB_FG_CI, cy4_SUB_G_1, cy4_SUB_G_CI, cy4_SUB_G_F1, cy4_SUB_G_F3_, d3_8e, d3_8e, d3_8e, d3_8e, dcm, fmap_g, gnd, gnd, gnd, gnd, gnd, ibuf_g, ibuf_g, ibuf_g, ibuf_g, icap_virtex2, inv_g, inv_g, inv_g, inv_g, iobuf, iobuf, iobuf_agp, iobuf_agp, iobuf_ctt, iobuf_ctt, iobuf_f_12, iobuf_f_12, iobuf_f_16, iobuf_f_16, iobuf_f_2, iobuf_f_2, iobuf_f_24, iobuf_f_24, iobuf_f_4, iobuf_f_4, iobuf_f_6, iobuf_f_6, iobuf_f_8, iobuf_f_8, iobuf_gtl, iobuf_gtl, iobuf_gtlp, iobuf_gtlp, iobuf_hstl_i, iobuf_hstl_i, iobuf_hstl_iii, iobuf_hstl_iii, iobuf_hstl_iv, iobuf_hstl_iv, iobuf_lvcmos2, iobuf_lvcmos2, iobuf_pci33_3, iobuf_pci33_3, iobuf_pci33_5, iobuf_pci33_5, iobuf_pci66_3, iobuf_pci66_3, iobuf_s_12, iobuf_s_12, iobuf_s_16, iobuf_s_16, iobuf_s_2, iobuf_s_2, iobuf_s_24, iobuf_s_24, iobuf_s_4, iobuf_s_4, iobuf_s_6, iobuf_s_6, iobuf_s_8, iobuf_s_8, iobuf_sstl2_i, iobuf_sstl2_i, iobuf_sstl2_ii, iobuf_sstl2_ii, iobuf_sstl2_ii_dci, iobuf_sstl3_i, iobuf_sstl3_i, iobuf_sstl3_ii, iobuf_sstl3_ii, iobufds, m2_1, m2_1, m2_1, m2_1, m2_1_g, m2_1_g, m2_1_g, m2_1_g, mux41, mux41, mux41, mux81, mux81, mux81, nand2, nand2, nand2, nand2, nand2_g, nand2_g, nand2_g, nand2_g, nand2b1, nand2b1, nand2b1, nand2b1, nand2b2, nand2b2, nand2b2, nand2b2, nand3, nand3, nand3, nand3, nand3_g, nand3_g, nand3_g, nand3_g, nand3b1, nand3b1, nand3b1, nand3b1, nand3b2, nand3b2, nand3b2, nand3b2, nand3b3, nand3b3, nand3b3, nand3b3, nand4, nand4, nand4, nand4, nand4_g, nand4_g, nand4_g, nand4_g, nand4b1, nand4b1, nand4b1, nand4b1, nand4b2, nand4b2, nand4b2, nand4b2, nand4b3, nand4b3, nand4b3, nand4b3, nand4b4, nand4b4, nand4b4, nand4b4, nand5, nand5, nand5, nand5, nand5_g, nand6, nand6, nand6, nand6, nand6_g, nand7, nand7, nand7, nand7, nand7_g, nand8, nand8, nand8, nand8, nand8_g, nand9, nand9, nand9, nand9, nand9_g, nandX, nandX, nandX, nandX, nandX_g, nandX_g, nandX_g, nor2, nor2, nor2, nor2, nor2_g, nor2_g, nor2_g, nor2_g, nor2b1, nor2b1, nor2b1, nor2b1, nor2b2, nor2b2, nor2b2, nor2b2, nor3, nor3, nor3, nor3, nor3_g, nor3_g, nor3_g, nor3_g, nor3b1, nor3b1, nor3b1, nor3b1, nor3b2, nor3b2, nor3b2, nor3b2, nor3b3, nor3b3, nor3b3, nor3b3, nor4, nor4, nor4, nor4, nor4_g, nor4_g, nor4_g, nor4_g, nor4b1, nor4b1, nor4b1, nor4b1, nor4b2, nor4b2, nor4b2, nor4b2, nor4b3, nor4b3, nor4b3, nor4b3, nor4b4, nor4b4, nor4b4, nor4b4, nor5, nor5, nor5, nor5, nor5_g, nor6, nor6, nor6, nor6, nor6_g, nor7, nor7, nor7, nor7, nor7_g, nor8, nor8, nor8, nor8, nor8_g, nor9, nor9, nor9, nor9, nor9_g, norX, norX, norX, norX, norX_g, norX_g, norX_g, obuf_g, obuf_g, obuf_g, obuf_g, obuft, obuft, obuft, obuft, obuft_agp, obuft_agp, obuft_ctt, obuft_ctt, obuft_f_12, obuft_f_12, obuft_f_16, obuft_f_16, obuft_f_2, obuft_f_2, obuft_f_24, obuft_f_24, obuft_f_4, obuft_f_4, obuft_f_6, obuft_f_6, obuft_f_8, obuft_f_8, obuft_g, obuft_g, obuft_g, obuft_g, obuft_gtl, obuft_gtl, obuft_gtlp, obuft_gtlp, obuft_hstl_i, obuft_hstl_i, obuft_hstl_iii, obuft_hstl_iii, obuft_hstl_iv, obuft_hstl_iv, obuft_lvcmos2, obuft_lvcmos2, obuft_pci33_3, obuft_pci33_3, obuft_pci33_5, obuft_pci33_5, obuft_pci66_3, obuft_pci66_3, obuft_s_12, obuft_s_12, obuft_s_16, obuft_s_16, obuft_s_2, obuft_s_2, obuft_s_24, obuft_s_24, obuft_s_4, obuft_s_4, obuft_s_6, obuft_s_6, obuft_s_8, obuft_s_8, obuft_sstl2_i, obuft_sstl2_i, obuft_sstl2_i_dci, obuft_sstl2_ii, obuft_sstl2_ii, obuft_sstl3_i, obuft_sstl3_i, obuft_sstl3_ii, obuft_sstl3_ii, obuftds, or2, or2, or2, or2, or2_g, or2_g, or2_g, or2_g, or2b1, or2b1, or2b1, or2b1, or2b2, or2b2, or2b2, or2b2, or3, or3, or3, or3, or3_g, or3_g, or3_g, or3_g, or3b1, or3b1, or3b1, or3b1, or3b2, or3b2, or3b2, or3b2, or3b3, or3b3, or3b3, or3b3, or4, or4, or4, or4, or4_g, or4_g, or4_g, or4_g, or4b1, or4b1, or4b1, or4b1, or4b2, or4b2, or4b2, or4b2, or4b3, or4b3, or4b3, or4b3, or4b4, or4b4, or4b4, or4b4, or5, or5, or5, or5, or5_g, or6, or6, or6, or6, or6_g, or7, or7, or7, or7, or7_g, or8, or8, or8, or8, or8_g, or9, or9, or9, or9, or9_g, orX, orX, orX, orX, orX_g, orX_g, orX_g, pulldown_g, pulldown_g, pulldown_g, pulldown_g, pullup_g, pullup_g, pullup_g, pullup_g, roc, rocbuf, startbuf_architecture, Subtractor, Subtractor, Subtractor, Subtractor, toc, tocbuf, vcc, vcc, vcc, vcc, vcc, xnor2, xnor2, xnor2, xnor2, xnor2_g, xnor2_g, xnor2_g, xnor2_g, xnor3, xnor3, xnor3, xnor3, xnor3_g, xnor3_g, xnor3_g, xnor3_g, xnor4, xnor4, xnor4, xnor4, xnor4_g, xnor4_g, xnor4_g, xnor4_g, xnor5, xnor5, xnor5, xnor5, xnor5_g, xnor6, xnor6, xnor6, xnor6, xnor6_g, xnor7, xnor7, xnor7, xnor7, xnor7_g, xnor8, xnor8, xnor8, xnor8, xnor8_g, xnor9, xnor9, xnor9, xnor9, xnor9_g, xnorX, xnorX, xnorX, xnorX, xor2, xor2, xor2, xor2, xor2_g, xor2_g, xor2_g, xor2_g, xor3, xor3, xor3, xor3, xor3_g, xor3_g, xor3_g, xor3_g, xor4, xor4, xor4, xor4, xor4_g, xor4_g, xor4_g, xor4_g, xor5, xor5, xor5, xor5, xor5_g, xor6, xor6, xor6, xor6, xor6_g, xor7, xor7, xor7, xor7, xor7_g, xor8, xor8, xor8, xor8, xor8_g, xor9, xor9, xor9, xor9, xor9_g, xorX, xorX, xorX, xorX

public class XilinxCL

extends Logic

Field Summary

static CellInterface[]

implicit_interface

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

XilinxCL(Node parent)

XilinxCL(Node parent, java.lang.String name)

Method Summary

protected void

connectImplicitPorts() Connects the implicit ports.

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clock, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, defaultSimulationModelIsBehavioral, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagate, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, reset, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, cellInterfaceDeterminesUniqueNetlistStructure, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

implicit_interface

public static final CellInterface[] implicit_interface

Constructor Detail

XilinxCL

public XilinxCL(Node parent)

XilinxCL

public XilinxCL(Node parent,
                java.lang.String name)

Method Detail

connectImplicitPorts

protected void connectImplicitPorts()

Description copied from class: Logic

Connects the implicit ports. Override this if you shadow #implicit_ports. If you used the old version of connect_implicit_ports, this method will use reflection to see that the old version gets called correctly.

Overrides:

connectImplicitPorts in class Logic