byucc.jhdl.Xilinx
Class XilinxClockDriver

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.CL
                  byucc.jhdl.base.ClockDriver
                      byucc.jhdl.Xilinx.XilinxClockDriver

All Implemented Interfaces:

BooleanFlags, PreDefinedSchematic, byucc.jhdl.base.Propagateable, TreeListable, UndrivenInputsAllowable, UnmappableCell

public class XilinxClockDriver

extends ClockDriver

implements UnmappableCell, PreDefinedSchematic

Field Summary

static CellInterface[]

cell_interface

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, implicit_interface, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.apps.Viewers.Schematic.PreDefinedSchematic

PreDefinedSchematic_ADD, PreDefinedSchematic_ADDSUB, PreDefinedSchematic_AND, PreDefinedSchematic_BUF, PreDefinedSchematic_CONST, PreDefinedSchematic_GEN, PreDefinedSchematic_GND, PreDefinedSchematic_INC, PreDefinedSchematic_INV, PreDefinedSchematic_MUX, PreDefinedSchematic_NAND, PreDefinedSchematic_NOR, PreDefinedSchematic_OR, PreDefinedSchematic_PULLDOWN, PreDefinedSchematic_PULLUP, PreDefinedSchematic_REG, PreDefinedSchematic_SHL, PreDefinedSchematic_SHR, PreDefinedSchematic_TBUF, PreDefinedSchematic_VCC, PreDefinedSchematic_XNOR, PreDefinedSchematic_XOR

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

XilinxClockDriver(Node parent, ArgBlockList abl)
Constructs a new XilinxClockDriver, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

XilinxClockDriver(Node parent, java.lang.String instanceName, ArgBlockList abl)
Constructs a new XilinxClockDriver, connecting its ports as given by the String-Wire pairs in the ArgBlockList, with the initial String parameter as the instance name.

XilinxClockDriver(Node parent, java.lang.String instanceName, java.lang.String s0, Wire w0)
Constructs a new XilinxClockDriver, connecting each Wire to the port whose name is given by the accompanying String parameter, with the initial String parameter as the instance name.

XilinxClockDriver(Node parent, java.lang.String instanceName, Wire o)
Constructs a new XilinxClockDriver, with the initial String parameter as the instance name.

XilinxClockDriver(Node parent, java.lang.String instanceName, Wire o, java.lang.String schedule)
Constructs a new XilinxClockDriver, with the initial String parameter as the instance name, with a given clock schedule.

XilinxClockDriver(Node parent, Wire o)
Constructs a new XilinxClockDriver.

XilinxClockDriver(Node parent, Wire o, java.lang.String schedule)
Constructs a new XilinxClockDriver with a given clock schedule.

Method Summary

boolean	cellInterfaceDeterminesUniqueNetlistStructure() When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.
protected java.lang.String	determineSchedule() If this clock driver was constructed without a schedule, this method will be called just before simulation begins.
int	type() This method returns one of the predefined schematic constants to identify the type of this cell.

Methods inherited from class byucc.jhdl.base.ClockDriver

getSchedule, getScheduledValue, needsToBeAsynchronouslyScheduled, portMayBeUndriven, preorderCheck, propagate, toString

Methods inherited from class byucc.jhdl.base.CL

behavioralModelIsAvailable, defaultSimulationModelIsBehavioral, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isReadyToBeAsynchronouslyScheduled

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, constructSubCell, constructSubCellNoImplicitPorts, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getSubCellClass, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getDefaultClock, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

cell_interface

public static CellInterface[] cell_interface

Constructor Detail

XilinxClockDriver

public XilinxClockDriver(Node parent,
                         Wire o)

Constructs a new XilinxClockDriver.

Parameters:

parent - The parent Cell to the XilinxClockDriver

o - The Wire to be connected to output port o

XilinxClockDriver

public XilinxClockDriver(Node parent,
                         java.lang.String instanceName,
                         Wire o)

Constructs a new XilinxClockDriver, with the initial String parameter as the instance name.

Parameters:

parent - The parent Cell to the XilinxClockDriver

instanceName - The instance name of the XilinxClockDriver

o - The Wire to be connected to output port o

XilinxClockDriver

public XilinxClockDriver(Node parent,
                         Wire o,
                         java.lang.String schedule)

Constructs a new XilinxClockDriver with a given clock schedule.

Parameters:

parent - The parent Cell to the XilinxClockDriver

o - The Wire to be connected to output port o

schedule - The String describing the schedule of clock port o

XilinxClockDriver

public XilinxClockDriver(Node parent,
                         java.lang.String instanceName,
                         Wire o,
                         java.lang.String schedule)

Constructs a new XilinxClockDriver, with the initial String parameter as the instance name, with a given clock schedule.

Parameters:

parent - The parent Cell to the XilinxClockDriver

instanceName - The instance name of the XilinxClockDriver

o - The Wire to be connected to output port o

schedule - The String describing the schedule of clock port o

XilinxClockDriver

public XilinxClockDriver(Node parent,
                         java.lang.String instanceName,
                         java.lang.String s0,
                         Wire w0)

Constructs a new XilinxClockDriver, connecting each Wire to the port whose name is given by the accompanying String parameter, with the initial String parameter as the instance name.

Parameters:

parent - The parent Cell to the XilinxClockDriver

instanceName - The instance name of the XilinxClockDriver

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

XilinxClockDriver

public XilinxClockDriver(Node parent,
                         ArgBlockList abl)

Constructs a new XilinxClockDriver, connecting its ports as given by the String-Wire pairs in the ArgBlockList. Any generic assignments are made through String-String pairs in the ArgBlockList.

Parameters:

parent - The parent Cell to the XilinxClockDriver

abl - The list of String-Wire pairs for port assignments, and String-String pairs for generic assignments.

XilinxClockDriver

public XilinxClockDriver(Node parent,
                         java.lang.String instanceName,
                         ArgBlockList abl)

Constructs a new XilinxClockDriver, connecting its ports as given by the String-Wire pairs in the ArgBlockList, with the initial String parameter as the instance name. Any generic assignments are made through String-String pairs in the ArgBlockList.

Parameters:

parent - The parent Cell to the XilinxClockDriver

instanceName - The instance name of the XilinxClockDriver

abl - The list of String-Wire pairs for port assignments, and String-String pairs for generic assignments.

Method Detail

cellInterfaceDeterminesUniqueNetlistStructure

public final boolean cellInterfaceDeterminesUniqueNetlistStructure()

Description copied from class: Cell

When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. Overriding this method to return true allows JHDL to save memory and netlists to be smaller by sharing the netlist structures that are guaranteed to be identical. NOTE: Do not override this unless every possible condition responsible for structural differences in a class (types and amount of children cells created, and arrangements of wires connected to ports) is included in the cellInterface[] of that class.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

false if not overridden, preventing all memory sharing

type

public int type()

Description copied from interface: PreDefinedSchematic

This method returns one of the predefined schematic constants to identify the type of this cell.

Specified by:

type in interface PreDefinedSchematic

Returns:

A predefined schematic constant

determineSchedule

protected java.lang.String determineSchedule()

If this clock driver was constructed without a schedule, this method will be called just before simulation begins. At that time, the circuit should be finalized so that it is possible to query "upstream" in the circuit to determine a valid clock schedule. If the clock driver cannot find a schedule upstream, it will use the global default schedule and print a warning message.

Overrides:

determineSchedule in class ClockDriver

Returns:

a valid clock schedule string