byucc.jhdl.Xilinx.XC4000
Class cy4

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.Xilinx.XilinxCL
                                  byucc.jhdl.Xilinx.XC4000.cy4

All Implemented Interfaces:

BooleanFlags, Clockable, byucc.jhdl.base.Propagateable, TreeListable, UndrivenInputsAllowable

public final class cy4

extends XilinxCL

implements UndrivenInputsAllowable

This class implements the carry modes for the XC4000 architecture. The exact carry function computed depends on the value of the carry mode bits on the c port. This class is designed to be used with the cy4_mode class. Refer to the XC4000 documentation for the specifications of the mode values and the corresponding functions. The CY4 computes the two carries resulting from the combination of the a0, a1, b0, b1, and cin inputs, which correspond to a 2-bit sum with carry-in. The CY4 computes the corresponding two carry bits resulting from the sum: a0 + b0 + cin => cout0; a1 + b1 + cout0 => cout. Only the cout signal is accessible outside the CLB in which the carries are computed.

Field Summary

static CellInterface[]	cell_interface The port interface for cy4: a0: in (1) a1: in (1) b0: in (1) b1: in (1) add: in (1) cin: in (1) c0: in (1) c1: in (1) c2: in (1) c3: in (1) c4: in (1) c5: in (1) c6: in (1) c7: in (1) cout0: out (1) cout: out (1)
static java.lang.String	cellname The netlist name for cy4: "CY4"

Fields inherited from class byucc.jhdl.Xilinx.XilinxCL

implicit_interface

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

cy4(Node parent, java.lang.String name, java.lang.String s_a0, Wire p_a0, java.lang.String s_a1, Wire p_a1, java.lang.String s_b0, Wire p_b0, java.lang.String s_b1, Wire p_b1, java.lang.String s_addsub, Wire p_addsub_, java.lang.String s_cin, Wire p_cin, java.lang.String s_cout0, Wire p_cout0, java.lang.String s_cout, Wire p_cout, java.lang.String mode)

cy4(Node parent, java.lang.String name, java.lang.String s_a0, Wire p_a0, java.lang.String s_a1, Wire p_a1, java.lang.String s_b0, Wire p_b0, java.lang.String s_b1, Wire p_b1, java.lang.String s_add, Wire p_addsub_, java.lang.String s_cin, Wire p_cin, java.lang.String s_c0, Wire p_c0, java.lang.String s_c1, Wire p_c1, java.lang.String s_c2, Wire p_c2, java.lang.String s_c3, Wire p_c3, java.lang.String s_c4, Wire p_c4, java.lang.String s_c5, Wire p_c5, java.lang.String s_c6, Wire p_c6, java.lang.String s_c7, Wire p_c7, java.lang.String s_cout0, Wire p_cout0, java.lang.String s_cout, Wire p_cout)

cy4(Node parent, java.lang.String s_a0, Wire p_a0, java.lang.String s_a1, Wire p_a1, java.lang.String s_b0, Wire p_b0, java.lang.String s_b1, Wire p_b1, java.lang.String s_addsub, Wire p_addsub_, java.lang.String s_cin, Wire p_cin, java.lang.String s_cout0, Wire p_cout0, java.lang.String s_cout, Wire p_cout, java.lang.String mode)

cy4(Node parent, java.lang.String s_a0, Wire p_a0, java.lang.String s_a1, Wire p_a1, java.lang.String s_b0, Wire p_b0, java.lang.String s_b1, Wire p_b1, java.lang.String s_add, Wire p_addsub_, java.lang.String s_cin, Wire p_cin, java.lang.String s_c0, Wire p_c0, java.lang.String s_c1, Wire p_c1, java.lang.String s_c2, Wire p_c2, java.lang.String s_c3, Wire p_c3, java.lang.String s_c4, Wire p_c4, java.lang.String s_c5, Wire p_c5, java.lang.String s_c6, Wire p_c6, java.lang.String s_c7, Wire p_c7, java.lang.String s_cout0, Wire p_cout0, java.lang.String s_cout, Wire p_cout)

cy4(Node parent, Wire p_a0, Wire p_a1, Wire p_b0, Wire p_b1, Wire p_addsub_, Wire p_cin, Wire p_cout0, Wire p_cout, java.lang.String mode)

cy4(Node parent, Wire p_a0, Wire p_a1, Wire p_b0, Wire p_b1, Wire p_addsub_, Wire p_cin, Wire p_carry_mode, Wire p_cout0, Wire p_cout)
Creates a new cy4 block.

cy4(Node parent, Wire p_a0, Wire p_a1, Wire p_b0, Wire p_b1, Wire p_addsub_, Wire p_cin, Wire p_c0, Wire p_c1, Wire p_c2, Wire p_c3, Wire p_c4, Wire p_c5, Wire p_c6, Wire p_c7, Wire p_cout0, Wire p_cout)

Method Summary

boolean	cellInterfaceDeterminesUniqueNetlistStructure() When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.
boolean	portMayBeUndriven(java.lang.String portname) This is used to determine which ports may be undriven based on the instance's mode of operation
void	propagate() Performs the asynchronous behavior of the cy4 cell.

Methods inherited from class byucc.jhdl.Xilinx.XilinxCL

connectImplicitPorts

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clock, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, defaultSimulationModelIsBehavioral, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, reset, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

cell_interface

public static CellInterface[] cell_interface

The port interface for cy4: a0: in (1) a1: in (1) b0: in (1) b1: in (1) add: in (1) cin: in (1) c0: in (1) c1: in (1) c2: in (1) c3: in (1) c4: in (1) c5: in (1) c6: in (1) c7: in (1) cout0: out (1) cout: out (1)

cellname

public static final java.lang.String cellname

The netlist name for cy4: "CY4"

See Also:

Constant Field Values

Constructor Detail

cy4

public cy4(Node parent,
           Wire p_a0,
           Wire p_a1,
           Wire p_b0,
           Wire p_b1,
           Wire p_addsub_,
           Wire p_cin,
           Wire p_carry_mode,
           Wire p_cout0,
           Wire p_cout)

Creates a new cy4 block.

Parameters:

parent - The parent Node to be used for the cy4.

p_a0 - The wire connected to the a0 port.

p_a1 - The wire connected to the a1 port.

p_b0 - The wire connected to the b0 port.

p_b1 - The wire connected to the b1 port.

p_addsub_ - The wire connected to the add port.

p_cin - The wire connected to the cin port.

p_carry_mode - The wire connected to the c port. Note that the easiest way to create this wire is by using the carry_mode class's getModeWire method.

p_cout0 - The wire connected to the cout0 intermediate output port.

p_cout - The wire connected to the cout port.

cy4

public cy4(Node parent,
           Wire p_a0,
           Wire p_a1,
           Wire p_b0,
           Wire p_b1,
           Wire p_addsub_,
           Wire p_cin,
           Wire p_c0,
           Wire p_c1,
           Wire p_c2,
           Wire p_c3,
           Wire p_c4,
           Wire p_c5,
           Wire p_c6,
           Wire p_c7,
           Wire p_cout0,
           Wire p_cout)

cy4

public cy4(Node parent,
           java.lang.String s_a0,
           Wire p_a0,
           java.lang.String s_a1,
           Wire p_a1,
           java.lang.String s_b0,
           Wire p_b0,
           java.lang.String s_b1,
           Wire p_b1,
           java.lang.String s_add,
           Wire p_addsub_,
           java.lang.String s_cin,
           Wire p_cin,
           java.lang.String s_c0,
           Wire p_c0,
           java.lang.String s_c1,
           Wire p_c1,
           java.lang.String s_c2,
           Wire p_c2,
           java.lang.String s_c3,
           Wire p_c3,
           java.lang.String s_c4,
           Wire p_c4,
           java.lang.String s_c5,
           Wire p_c5,
           java.lang.String s_c6,
           Wire p_c6,
           java.lang.String s_c7,
           Wire p_c7,
           java.lang.String s_cout0,
           Wire p_cout0,
           java.lang.String s_cout,
           Wire p_cout)

cy4

public cy4(Node parent,
           java.lang.String name,
           java.lang.String s_a0,
           Wire p_a0,
           java.lang.String s_a1,
           Wire p_a1,
           java.lang.String s_b0,
           Wire p_b0,
           java.lang.String s_b1,
           Wire p_b1,
           java.lang.String s_add,
           Wire p_addsub_,
           java.lang.String s_cin,
           Wire p_cin,
           java.lang.String s_c0,
           Wire p_c0,
           java.lang.String s_c1,
           Wire p_c1,
           java.lang.String s_c2,
           Wire p_c2,
           java.lang.String s_c3,
           Wire p_c3,
           java.lang.String s_c4,
           Wire p_c4,
           java.lang.String s_c5,
           Wire p_c5,
           java.lang.String s_c6,
           Wire p_c6,
           java.lang.String s_c7,
           Wire p_c7,
           java.lang.String s_cout0,
           Wire p_cout0,
           java.lang.String s_cout,
           Wire p_cout)

cy4

public cy4(Node parent,
           Wire p_a0,
           Wire p_a1,
           Wire p_b0,
           Wire p_b1,
           Wire p_addsub_,
           Wire p_cin,
           Wire p_cout0,
           Wire p_cout,
           java.lang.String mode)

cy4

public cy4(Node parent,
           java.lang.String s_a0,
           Wire p_a0,
           java.lang.String s_a1,
           Wire p_a1,
           java.lang.String s_b0,
           Wire p_b0,
           java.lang.String s_b1,
           Wire p_b1,
           java.lang.String s_addsub,
           Wire p_addsub_,
           java.lang.String s_cin,
           Wire p_cin,
           java.lang.String s_cout0,
           Wire p_cout0,
           java.lang.String s_cout,
           Wire p_cout,
           java.lang.String mode)

cy4

public cy4(Node parent,
           java.lang.String name,
           java.lang.String s_a0,
           Wire p_a0,
           java.lang.String s_a1,
           Wire p_a1,
           java.lang.String s_b0,
           Wire p_b0,
           java.lang.String s_b1,
           Wire p_b1,
           java.lang.String s_addsub,
           Wire p_addsub_,
           java.lang.String s_cin,
           Wire p_cin,
           java.lang.String s_cout0,
           Wire p_cout0,
           java.lang.String s_cout,
           Wire p_cout,
           java.lang.String mode)

Method Detail

cellInterfaceDeterminesUniqueNetlistStructure

public boolean cellInterfaceDeterminesUniqueNetlistStructure()

Description copied from class: Cell

When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. Overriding this method to return true allows JHDL to save memory and netlists to be smaller by sharing the netlist structures that are guaranteed to be identical. NOTE: Do not override this unless every possible condition responsible for structural differences in a class (types and amount of children cells created, and arrangements of wires connected to ports) is included in the cellInterface[] of that class.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

false if not overridden, preventing all memory sharing

propagate

public final void propagate()

Performs the asynchronous behavior of the cy4 cell. Basically a big switch function based on the carry mode signal c.

Specified by:

propagate in interface byucc.jhdl.base.Propagateable

Overrides:

propagate in class Structural

portMayBeUndriven

public boolean portMayBeUndriven(java.lang.String portname)

This is used to determine which ports may be undriven based on the instance's mode of operation

Specified by:

portMayBeUndriven in interface UndrivenInputsAllowable

Parameters:

portname - the portname to check

Returns:

true if the port may be undriven, because this cy4 will not read it.