|
Class Summary |
| and2 |
This class implements and asynchronous 2-input and gate. |
| and2_g |
This class implements and asynchronous 2-input and gate. |
| and2b1 |
This class implements and asynchronous 2-input and gate. |
| and2b2 |
This class implements and asynchronous 2-input and gate. |
| and3 |
This class implements and asynchronous 3-input and gate. |
| and3_g |
This class implements and asynchronous 3-input and gate. |
| and3b1 |
This class implements and asynchronous 3-input and gate. |
| and3b2 |
This class implements and asynchronous 3-input and gate. |
| and3b3 |
This class implements and asynchronous 3-input and gate. |
| and4 |
This class implements and asynchronous 4-input and gate. |
| and4_g |
This class implements and asynchronous 4-input and gate. |
| and4b1 |
This class implements and asynchronous 4-input and gate. |
| and4b2 |
This class implements and asynchronous 4-input and gate. |
| and4b3 |
This class implements and asynchronous 4-input and gate. |
| and4b4 |
This class implements and asynchronous 4-input and gate. |
| and5 |
This class implements and asynchronous 5-input and gate. |
| and6 |
This class implements and asynchronous 6-input and gate. |
| and7 |
This class implements and asynchronous 7-input and gate. |
| and8 |
This class implements and asynchronous 8-input and gate. |
| and9 |
This class implements and asynchronous 9-input and gate. |
| andX |
This class implements an AND gate with arbitrary number of inputs. |
| bscan |
The BSCAN symbol indicates that boundary scan logic should be
enabled after the programmable logic device (PLD) configuration
is complete. |
| buf |
BUF is a general purpose, non-inverting buffer. |
| buf_g |
The BUF_G is a generic-width non-inverting buffer cell. |
| bufe |
BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple tristate
buffers with inputs I, I3 - I0, I7 - I0, and I15 - I0,
respectively; outputs O, O3 - O0, O7 - O0, and O15 - O0,
respectively; and active-High output enable (E). |
| buffclk |
BUFFCLK (FastCLK buffer) provides the fastest way to bring a clock
into the XC4000X device. |
| bufg |
The BUFG cell is a global buffer which distributes high-fanout
clock signals throughout the device. |
| bufg_ann |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| bufge |
Eight Global Early buffers (BUFGE), two on each corner of the
device, provide an earlier clock access than the potentially
heavily loaded Global Low-Skew buffers (BUFGLS). |
| bufge_ann |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| bufgls |
Each corner of the XC4000X or SpartanXL device has two Global
Low-Skew buffers (BUFGLS). |
| bufgls_ann |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| bufgp |
The BUFG cell is a global buffer which distributes high-fanout
clock signals throughout the device. |
| bufgp_ann |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| bufgs |
BUFGS, a secondary global buffer, distributes high fan-out clock
or control signals throughout a PLD device. |
| bufgs_ann |
Each of the BUF*_ANN classes implements an Annotation-only buffer,
i.e. |
| buft |
BUFT is a 3-state buffer with input I, output O, and active-Low
output enable (T). |
| buft_g |
The BUFT_G is a generic-width tristate buffer cell. |
| cy4 |
This class implements the carry modes for the XC4000 architecture. |
| cy4_mode |
The cy4_mode block is the Annotation wrapper to indicate the exact
carry function being implemented to the back end Xilinx tools. |
| d3_8e |
The d3_8e class implements an enabled 3:8 decoder. |
| fd |
D is a single D-type flip-flop with data input (D) and data output
(Q). |
| fd_1 |
FD_1 is a single D-type flip-flop with data input (D) and data
output (Q). |
| fdc |
Implements an asynchronously clearable register in the XC4000
library. |
| fdc_1 |
FDC_1 is a single D-type flip-flop with data input (D),
asynchronous clear input (CLR), and data output (Q). |
| fdc_1_g |
Implements an asynchronously clearable register in the XC4000
library. |
| fdce |
The FDCE is an asynchronously cleared, enabled D-type flip-flop. |
| fdce_1 |
FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE),
asynchronous clear (CLR) inputs, and data output (Q). |
| fdce_g |
The FDCE_G is a generic-width, asynchronously cleared, enabled
D-type flip-flop. |
| fde |
FDE is a single D-type flip-flop with data input (D), clock enable
(CE), and data output (Q). |
| fde_1 |
FDE_1 is a single D-type flip-flop with data input (D), clock
enable (CE), and data output (Q). |
| fdp |
Implements an asynchronously settable register in the XC4000
library. |
| fdp_1 |
FDP_1 is a single D-type flip-flop with data (D) and asynchronous
preset (PRE) inputs and data output (Q). |
| fdp_1_g |
Implements an asynchronously settable register in the XC4000
library. |
| fdpe |
The FDPE is an asynchronously preset, enabled D-type flip-flop. |
| fdpe_1 |
FDPE_1 is a single D-type flip-flop with data (D), clock enable
(CE), and asynchronous preset (PRE) inputs and data output (Q). |
| fdpe_g |
The FDCE_P is a generic-width, asynchronously preset, enabled
D-type flip-flop. |
| fdr |
FDR is a D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdr_1 |
FDR_1 is a single D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdr_1_g |
FDR is a D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdre |
FDRE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). |
| fdre_1 |
FDRE_1 is a single D-type flip-flop with data (D), clock enable
(CE), and synchronous reset (R) inputs and data output (Q). |
| fdre_1_g |
FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). |
| fdrs |
FDRS is a single D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_1 |
FDRS_1 is a single D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_1_g |
FDRS_1 is a D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_g |
FDRS is a D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrse |
FDRSE is a single D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_1 |
FDRSE_1 is a single D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_1_g |
FDRSE is a D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_g |
FDRSE is a D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fds |
FDS is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fds_1 |
FDS_1 is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fds_1_g |
FDS_1 is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fdse |
FDSE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fdse_1 |
FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fdse_1_g |
FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fmap |
The FMAP symbol is used to control logic partitioning into XC4000
family 4-input function generators. |
| fmap_g |
The fmap_g is a generic_width and generic port count wrapper for all
XC4000 techmapper specific cells. |
| gnd |
This class is the GND cell for the Xilinx tools as well as
for JHDL simulation. |
| hmap |
The HMAP symbol is used to control logic partitioning into XC4000
family 3-input H funciton generators. |
| ibuf |
IBUF is a single input buffer. |
| ibuf_ann |
IBUF is a single input buffer. |
| ibuf_g |
IBUF is a single input buffer. |
| ifd |
The IFD D-type flip-flop is contained in an input/output block
(IOB). |
| ifd_1 |
The IFD_1 D-type flip-flop is contained in an input/output block
(IOB) except for XC5200. |
| ifdi |
The IFDI D-type flip-flop is contained in an input/output block
(IOB). |
| ifdi_1 |
The IFDI_1 D-type flip-flop is contained in an input/output block
(IOB). |
| ifdx |
The IFDX D-type flip-flop is contained in an input/output block
(IOB). |
| ifdxi |
The IFDXI D-type flip-flop is contained in an input/output block
(IOB). |
| ildx_1 |
ILDX_1 is a transparent data latch, which can be used to hold
transient data entering a chip. |
| ildxi_1 |
ILDXI_1 is a transparent data latch, which can hold transient data
entering a chip. |
| ilffx |
ILFFX, an optional latch that drives the input flip-flop, allows
the very fast capture of input data. |
| ilffxi |
ILFFXI, an optional latch that drives the input flip-flop, allows
the very fast capture of input data. |
| ilflx_1 |
ILFLX_1, an optional latch that drives the input latch, allows the
very fast capture of input data. |
| ilflxi_1 |
ILFLXI_1, an optional latch that drives the input latch, allows
the very fast capture of input data. |
| inv |
The INV cell is an asynchronous inverter. |
| inv_g |
The INV_G is a generic-width inverter cell. |
| iopad |
Deprecated. iopads are not necessary. |
| ipad |
Deprecated. ipads are not necessary. |
| ipad_sim |
Deprecated. ipads are not necessary. |
| ldce |
LDCE is a transparent data latch with asynchronous clear and gate
enable. |
| ldce_1 |
LDCE_1 is a transparent data latch with asynchronous clear, gate
enable, and inverted gate. |
| ldpe_1 |
LDPE_1 is a transparent data latch with asynchronous preset, gate
enable, and inverted gated. |
| m2_1 |
The M2_1 multiplexer chooses one data bit from two sources (D1 or
D0) under the control of the select input (S0). |
| m2_1_g |
The M2_1 multiplexer is a generic-width 2:1 multiplexer. |
| md0 |
The MD0 input pad is connected to the Mode 0 (MO) input pin, which
is used to determine the configuration mode on an XC4000
device. |
| md1 |
The MD1 input pad is connected to the Mode 1 (M1) input pin, which
is used to determine the configuration mode on an XC4000
device. |
| md2 |
The MD2 input pad is connected to the Mode 2 (M2) input pin, which
is used to determine the configuration mode on an XC4000
device. |
| nand2 |
This class implements and asynchronous 2-input nand gate. |
| nand2_g |
This class implements and asynchronous 2-input nand gate. |
| nand2b1 |
This class implements and asynchronous 2-input nand gate. |
| nand2b2 |
This class implements and asynchronous 2-input nand gate. |
| nand3 |
This class implements and asynchronous 3-input nand gate. |
| nand3_g |
This class implements and asynchronous 3-input nand gate. |
| nand3b1 |
This class implements and asynchronous 3-input nand gate. |
| nand3b2 |
This class implements and asynchronous 3-input nand gate. |
| nand3b3 |
This class implements and asynchronous 3-input nand gate. |
| nand4 |
This class implements and asynchronous 4-input nand gate. |
| nand4_g |
This class implements and asynchronous 4-input nand gate. |
| nand4b1 |
This class implements and asynchronous 4-input nand gate. |
| nand4b2 |
This class implements and asynchronous 4-input nand gate. |
| nand4b3 |
This class implements and asynchronous 4-input nand gate. |
| nand4b4 |
This class implements and asynchronous 4-input nand gate. |
| nand5 |
This class implements and asynchronous 5-input nand gate. |
| nand6 |
This class implements and asynchronous 6-input nand gate. |
| nand7 |
This class implements and asynchronous 7-input nand gate. |
| nand8 |
This class implements and asynchronous 8-input nand gate. |
| nand9 |
This class implements and asynchronous 9-input nand gate. |
| nandX |
This class implements an NAND gate with arbitrary number of inputs. |
| nor2 |
This class implements and asynchronous 2-input nor gate. |
| nor2_g |
This class implements and asynchronous 2-input nor gate. |
| nor2b1 |
This class implements and asynchronous 2-input nor gate. |
| nor2b2 |
This class implements and asynchronous 2-input nor gate. |
| nor3 |
This class implements and asynchronous 3-input nor gate. |
| nor3_g |
This class implements and asynchronous 3-input nor gate. |
| nor3b1 |
This class implements and asynchronous 3-input nor gate. |
| nor3b2 |
This class implements and asynchronous 3-input nor gate. |
| nor3b3 |
This class implements and asynchronous 3-input nor gate. |
| nor4 |
This class implements and asynchronous 4-input nor gate. |
| nor4_g |
This class implements and asynchronous 4-input nor gate. |
| nor4b1 |
This class implements and asynchronous 4-input nor gate. |
| nor4b2 |
This class implements and asynchronous 4-input nor gate. |
| nor4b3 |
This class implements and asynchronous 4-input nor gate. |
| nor4b4 |
This class implements and asynchronous 4-input nor gate. |
| nor5 |
This class implements and asynchronous 5-input nor gate. |
| nor6 |
This class implements and asynchronous 6-input nor gate. |
| nor7 |
This class implements and asynchronous 7-input nor gate. |
| nor8 |
This class implements and asynchronous 8-input nor gate. |
| nor9 |
This class implements and asynchronous 9-input nor gate. |
| norX |
This class implements an NOR gate with arbitrary number of inputs. |
| oand2 |
OAND2 is a 2-input AND gate that is implemented in the output
multiplexer of the XC4000X IOB. |
| obuf |
OBUF is a single output buffer. |
| obuf_ann |
OBUF is a single output buffer. |
| obuf_g |
OBUF is a single output buffer. |
| obuft |
OBUFT is a single 3-state output buffer with active-low enable. |
| obuft_g |
OBUFT is a single 3-state output buffer with active-low enable. |
| ofd |
OFD, OFD4, OFD8, and OFD16 are single and multiple output D
flip-flops except for XC5200 and XC9000. |
| ofde |
OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops
whose outputs are enabled by tristate buffers. |
| ofdi |
OFDI is contained in an input/output block (IOB). |
| ofdt |
OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops
whose outputs are enabled by a tristate buffers. |
| ofdtx |
OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D
flip-flops whose outputs are enabled by a tristate buffers. |
| ofdtxi |
OFDTXI and its output buffer are contained in an input/output
block (IOB). |
| ofdx |
OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D
flip-flops. |
| ofdxi |
OFDXI is contained in an input/output block (IOB). |
| omux2 |
The OMUX2 multiplexer chooses one data bit from two sources (D1 or
D0) under the control of the select input (S0). |
| onand2 |
ONAND2 is a 2-input NAND gate that is implemented in the output
multiplexer of the XC4000X IOB. |
| onor2 |
ONOR2 is a 2-input NOR gate that is implemented in the output
multiplexer of the XC4000X IOB. |
| oor2 |
OOR2 is a 2-input OR gate that is implemented in the output
multiplexer of the XC4000X IOB. |
| opad |
Deprecated. ipads are not necessary. |
| opad_sim |
Deprecated. ipads are not necessary. |
| or2 |
This class implements and asynchronous 2-input or gate. |
| or2_g |
This class implements and asynchronous 2-input or gate. |
| or2b1 |
This class implements and asynchronous 2-input or gate. |
| or2b2 |
This class implements and asynchronous 2-input or gate. |
| or3 |
This class implements and asynchronous 3-input or gate. |
| or3_g |
This class implements and asynchronous 3-input or gate. |
| or3b1 |
This class implements and asynchronous 3-input or gate. |
| or3b2 |
This class implements and asynchronous 3-input or gate. |
| or3b3 |
This class implements and asynchronous 3-input or gate. |
| or4 |
This class implements and asynchronous 4-input or gate. |
| or4_g |
This class implements and asynchronous 4-input or gate. |
| or4b1 |
This class implements and asynchronous 4-input or gate. |
| or4b2 |
This class implements and asynchronous 4-input or gate. |
| or4b3 |
This class implements and asynchronous 4-input or gate. |
| or4b4 |
This class implements and asynchronous 4-input or gate. |
| or5 |
This class implements and asynchronous 5-input or gate. |
| or6 |
This class implements and asynchronous 6-input or gate. |
| or7 |
This class implements and asynchronous 7-input or gate. |
| or8 |
This class implements and asynchronous 8-input or gate. |
| or9 |
This class implements and asynchronous 9-input or gate. |
| orX |
This class implements an OR gate with arbitrary number of inputs. |
| oxnor2 |
OXNOR2 is a 2-input exclusive NOR gate that is implemented in the
output multiplexer of the XC4000X and SpartanXL IOB. |
| oxor2 |
OXOR2 is a 2-input exclusive OR gate that is implemented in the
output multiplexer of the XC4000X IOB. |
| pulldown |
PULLDOWN resistor elements are available in each XC4000
Input/Output Block (IOB). |
| pulldown_g |
The PULLDOWN_G is a generic-width pulldown resistor cell. |
| pullup |
The pull-up element establishes a High logic level for open-drain
elements and macros (DECODE, WAND, WORAND) or 3-state nodes (TBUF)
when all the drivers are off. |
| pullup_g |
The PULLUP_G is a generic-width pullup resistor cell. |
| ram16x1 |
RAM16X1 is a 16-word by 1-bit static RAM. |
| ram16x1d |
RAM16X1D is a 16-word by 1-bit static dual-ported RAM. |
| ram16x1s |
RAM16X1S is a synchronous 16-word by 1-bit static RAM. |
| ram16x2d |
RAM16X2D is a 16-word by 2-bit static dual-ported RAM. |
| ram16x2s |
RAM16X2S is a synchronous 16-word by 2-bit static RAM. |
| ram16x4d |
RAM16X4D is a 16-word by 4-bit static dual-ported RAM. |
| ram16x4s |
RAM16X4S is a synchronous 16-word by 4-bit static RAM. |
| ram16x8d |
RAM16X8D is a 16-word by 8-bit static dual-ported RAM. |
| ram16x8s |
RAM16X8S is a synchronous 16-word by 8-bit static RAM. |
| ram32x1 |
RAM32X1 is a 32-word by 1-bit static RAM. |
| ram32x1s |
RAM32X1S is a synchronous 32-word by 1-bit static RAM. |
| ram32x2s |
RAM32X2S is a synchronous 32-word by 2-bit static RAM. |
| ram32x4s |
RAM32X4S is a synchronous 32-word by 4-bit static RAM. |
| ram32x8s |
RAM32X8S is a synchronous 32-word by 8-bit static RAM. |
| rom16x1 |
ROM16X1 is a 16-word by 1-bit ROM. |
| rom32x1 |
ROM32X1 is a 32-word by 1-bit ROM. |
| Shifter |
The Shifter class implements a generic wire shift. |
| SimulationBuffer |
This class implements a simulation-only buffer cell. |
| startup |
The STARTUP symbol is used for initializing the Global Set/Reset,
global 3-state control, and the user configuration clock. |
| tb_andX |
|
| tck |
The TCK input pad is connected to the boundary scan test clock,
which shifts the serial data and instructions into and out of the
boundary scan data registers. |
| tdi |
The TDI input pad is connected to the boundary scan TDI input. |
| tdo |
The TDO data output pad is connected to the boundary scan TDO
output. |
| TESTXC4000Library |
This class is the self-test controller for the XC4000 library. |
| tms |
The TMS input pad is connected to the boundary scan TMS input. |
| upad |
A UPAD allows the use of any unbonded IOBs in a device. |
| vcc |
This class is the VCC cell for the Xilinx tools as well as
for JHDL simulation. |
| wand |
WAND1, WAND4, WAND8, and WAND16 are single and multiple open-drain
buffers. |
| wor2and |
WOR2AND is a 2-input (I1 and I2) OR gate/buffer with an open-drain
output (O). |
| XC4000TechMapper |
This is the tech-mapper for the XC4K library. |
| XilinxTechMapper |
Simple extension of TechMapper class. |
| xnor2 |
This class implements and asynchronous 2-input xnor gate. |
| xnor2_g |
This class implements and asynchronous 2-input xnor gate. |
| xnor3 |
This class implements and asynchronous 3-input xnor gate. |
| xnor3_g |
This class implements and asynchronous 3-input xnor gate. |
| xnor4 |
This class implements and asynchronous 4-input xnor gate. |
| xnor4_g |
This class implements and asynchronous 4-input xnor gate. |
| xnor5 |
This class implements and asynchronous 5-input xnor gate. |
| xnor6 |
This class implements and asynchronous 6-input xnor gate. |
| xnor7 |
This class implements and asynchronous 7-input xnor gate. |
| xnor8 |
This class implements and asynchronous 8-input xnor gate. |
| xnor9 |
This class implements and asynchronous 9-input xnor gate. |
| xnorX |
This class implements an XNOR gate with arbitrary number of inputs. |
| xor2 |
This class implements and asynchronous 2-input xor gate. |
| xor2_g |
This class implements and asynchronous 2-input xor gate. |
| xor3 |
This class implements and asynchronous 3-input xor gate. |
| xor3_g |
This class implements and asynchronous 3-input xor gate. |
| xor4 |
This class implements and asynchronous 4-input xor gate. |
| xor4_g |
This class implements and asynchronous 4-input xor gate. |
| xor5 |
This class implements and asynchronous 5-input xor gate. |
| xor6 |
This class implements and asynchronous 6-input xor gate. |
| xor7 |
This class implements and asynchronous 7-input xor gate. |
| xor8 |
This class implements and asynchronous 8-input xor gate. |
| xor9 |
This class implements and asynchronous 9-input xor gate. |
| xorX |
This class implements an XOR gate with arbitrary number of inputs. |
| Xwire |
This class subclasses the class byucc.jhdl.Xilinx.Xwire. |