byucc.jhdl.Xilinx.Virtex
Class ram16x1s_1

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.Xilinx.BasicMemory
                                  byucc.jhdl.Xilinx.Memory
                                      byucc.jhdl.Xilinx.XilinxMemorySynch_1
                                          byucc.jhdl.Xilinx.Virtex.ram16x1s_1

All Implemented Interfaces:

BooleanFlags, Clockable, ExternallyUpdateable, Initializeable, LutRam, MemoryInterface, PreDefinedSchematic, byucc.jhdl.base.Propagateable, TreeListable

public final class ram16x1s_1

extends XilinxMemorySynch_1

implements LutRam, PreDefinedSchematic

RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any negative transition on WCLK loads the data on the data input (D) into the word selected by the 4-bit address (A3 - A0). For predictable performance, address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by the values on the address pins. (Source: XACT Libraries Guide, Chapter 9 RAM16X1S_1, Xilinx Corporation, 1999.)

Field Summary

static CellInterface[]	cell_interface The port interface for: ram16x1s_1 d : sin (1) we : sin (1) a : sain (4) o : aout (1) wclk : implicit (1)
static java.lang.String	cellname The static cellname (netlist reference name) for ram16x1s_1

Fields inherited from class byucc.jhdl.Xilinx.XilinxMemorySynch_1

implicit_interface

Fields inherited from class byucc.jhdl.Xilinx.BasicMemory

bitmasksl, contents

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.apps.Viewers.Schematic.PreDefinedSchematic

PreDefinedSchematic_ADD, PreDefinedSchematic_ADDSUB, PreDefinedSchematic_AND, PreDefinedSchematic_BUF, PreDefinedSchematic_CONST, PreDefinedSchematic_GEN, PreDefinedSchematic_GND, PreDefinedSchematic_INC, PreDefinedSchematic_INV, PreDefinedSchematic_MUX, PreDefinedSchematic_NAND, PreDefinedSchematic_NOR, PreDefinedSchematic_OR, PreDefinedSchematic_PULLDOWN, PreDefinedSchematic_PULLUP, PreDefinedSchematic_REG, PreDefinedSchematic_SHL, PreDefinedSchematic_SHR, PreDefinedSchematic_TBUF, PreDefinedSchematic_VCC, PreDefinedSchematic_XNOR, PreDefinedSchematic_XOR

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

protected	ram16x1s_1(Node parent) Used only by child classes to pass up the parent cell.
	ram16x1s_1(Node parent, ArgBlockList abl) Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.
protected	ram16x1s_1(Node parent, java.lang.String name) Used only by child classes to pass up the parent cell and instance name.
	ram16x1s_1(Node parent, java.lang.String instanceName, ArgBlockList abl) Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.
	ram16x1s_1(Node parent, java.lang.String instanceName, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3) Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.
	ram16x1s_1(Node parent, java.lang.String instanceName, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String INIT) Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.
	ram16x1s_1(Node parent, java.lang.String instanceName, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4) Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.
	ram16x1s_1(Node parent, java.lang.String instanceName, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4, java.lang.String INIT) Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.
	ram16x1s_1(Node parent, java.lang.String name, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4, java.lang.String s5, Wire w5, java.lang.String s6, Wire w6, java.lang.String s7, Wire w7)
	ram16x1s_1(Node parent, java.lang.String name, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4, java.lang.String s5, Wire w5, java.lang.String s6, Wire w6, java.lang.String s7, Wire w7, java.lang.String INIT)
	ram16x1s_1(Node parent, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3) Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter
	ram16x1s_1(Node parent, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String INIT) Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT
	ram16x1s_1(Node parent, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4) Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.
	ram16x1s_1(Node parent, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4, java.lang.String INIT) Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.
	ram16x1s_1(Node parent, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3, java.lang.String s4, Wire w4, java.lang.String s5, Wire w5, java.lang.String s6, Wire w6, java.lang.String s7, Wire w7)
	ram16x1s_1(Node parent, java.lang.String instanceName, Wire d, Wire we, Wire a, Wire o) Constructs a new ram16x1s_1.
	ram16x1s_1(Node parent, java.lang.String instanceName, Wire d, Wire we, Wire a, Wire o, java.lang.String INIT) Constructs a new ram16x1s_1.
	ram16x1s_1(Node parent, java.lang.String instanceName, Wire d, Wire we, Wire a, Wire o, Wire wclk) Constructs a new ram16x1s_1.
	ram16x1s_1(Node parent, java.lang.String instanceName, Wire d, Wire we, Wire a, Wire o, Wire wclk, java.lang.String INIT) Constructs a new ram16x1s_1.
	ram16x1s_1(Node parent, Wire d, Wire we, Wire a, Wire o) Constructs a new ram16x1s_1.
	ram16x1s_1(Node parent, Wire d, Wire we, Wire a, Wire o, java.lang.String INIT) Constructs a new ram16x1s_1.
	ram16x1s_1(Node parent, Wire d, Wire we, Wire a, Wire o, Wire wclk) Constructs a new ram16x1s_1.
	ram16x1s_1(Node parent, Wire d, Wire we, Wire a, Wire o, Wire wclk, java.lang.String INIT) Constructs a new ram16x1s_1.

Method Summary

boolean	cellInterfaceDeterminesUniqueNetlistStructure() When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.
void	clock() Users define synchronous behavior in this method using standard JHDL constructs.
java.lang.String	getCellName() Access the cell name associated with a derived class.
boolean	isAsynchronousSourceSinkResolved()
boolean	isNetlistLeaf() A few rare cells are leafCells during netlisting, but not during simulation.
static void	main(java.lang.String[] argv)
void	propagate() Users defined propagatable behavior using standard JHDL constructs.
void	reset() If you define a behavior, you must also define a reset method for resetting the synchonous part of your model.
static void	test()
int	type() This method returns one of the predefined schematic constants to identify the type of this cell.

Methods inherited from class byucc.jhdl.Xilinx.XilinxMemorySynch_1

connectImplicitPorts, isFallingEdgeTriggered, isRisingEdgeTriggered

Methods inherited from class byucc.jhdl.Xilinx.Memory

externallyUpdated, fetchState, resetExternallyUpdated, updateState

Methods inherited from class byucc.jhdl.Xilinx.BasicMemory

defaultSimulationModelIsBehavioral, getBits, getMemoryElement, getMemoryRange, getMemoryWidth, getSize, hexStr2Long, hexString2bin, init, initialize, padBits, read, readl, reverseBits, shiftl, splitBits, write

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor

Methods inherited from class byucc.jhdl.base.Structural

behavioralModelIsAvailable, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, hasBeenTraced, hasBeenTraced, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isReadyToBeAsynchronouslyScheduled, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, willUseHWUpdate, willUseHWUpdate

Methods inherited from class byucc.jhdl.base.Cell

addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasPort, hasPorts, in, in, inout, inout, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup

Methods inherited from class byucc.jhdl.base.Node

addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock

Methods inherited from class byucc.jhdl.base.Nameable

caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait

Field Detail

cellname

public static final java.lang.String cellname

The static cellname (netlist reference name) for ram16x1s_1

See Also:

Constant Field Values

cell_interface

public static CellInterface[] cell_interface

The port interface for: ram16x1s_1 d : sin (1) we : sin (1) a : sain (4) o : aout (1) wclk : implicit (1)

Constructor Detail

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String s4,
                  Wire w4,
                  java.lang.String s5,
                  Wire w5,
                  java.lang.String s6,
                  Wire w6,
                  java.lang.String s7,
                  Wire w7)

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String name,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String s4,
                  Wire w4,
                  java.lang.String s5,
                  Wire w5,
                  java.lang.String s6,
                  Wire w6,
                  java.lang.String s7,
                  Wire w7,
                  java.lang.String INIT)

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String name,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String s4,
                  Wire w4,
                  java.lang.String s5,
                  Wire w5,
                  java.lang.String s6,
                  Wire w6,
                  java.lang.String s7,
                  Wire w7)

ram16x1s_1

protected ram16x1s_1(Node parent)

Used only by child classes to pass up the parent cell.

Parameters:

parent - Parent cell

ram16x1s_1

protected ram16x1s_1(Node parent,
                     java.lang.String name)

Used only by child classes to pass up the parent cell and instance name.

Parameters:

parent - Parent cell

name - Instance name of the cell

ram16x1s_1

public ram16x1s_1(Node parent,
                  Wire d,
                  Wire we,
                  Wire a,
                  Wire o)

Constructs a new ram16x1s_1.

Parameters:

parent - The parent Cell to the ram16x1s_1

d - The Wire to be connected to input port d

we - The Wire to be connected to input port we

a - The Wire to be connected to input port a

o - The Wire to be connected to output port o

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  Wire d,
                  Wire we,
                  Wire a,
                  Wire o)

Constructs a new ram16x1s_1. The initial String parameter specifies the instance name.

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

d - The Wire to be connected to input port d

we - The Wire to be connected to input port we

a - The Wire to be connected to input port a

o - The Wire to be connected to output port o

ram16x1s_1

public ram16x1s_1(Node parent,
                  Wire d,
                  Wire we,
                  Wire a,
                  Wire o,
                  Wire wclk)

Constructs a new ram16x1s_1.

Parameters:

parent - The parent Cell to the ram16x1s_1

d - The Wire to be connected to input port d

we - The Wire to be connected to input port we

a - The Wire to be connected to input port a

o - The Wire to be connected to output port o

wclk - The Wire to be connected to implicit port wclk

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  Wire d,
                  Wire we,
                  Wire a,
                  Wire o,
                  Wire wclk)

Constructs a new ram16x1s_1. The initial String parameter specifies the instance name.

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

d - The Wire to be connected to input port d

we - The Wire to be connected to input port we

a - The Wire to be connected to input port a

o - The Wire to be connected to output port o

wclk - The Wire to be connected to implicit port wclk

ram16x1s_1

public ram16x1s_1(Node parent,
                  Wire d,
                  Wire we,
                  Wire a,
                  Wire o,
                  java.lang.String INIT)

Constructs a new ram16x1s_1. The final String parameters set the generics , INIT

Parameters:

parent - The parent Cell to the ram16x1s_1

d - The Wire to be connected to input port d

we - The Wire to be connected to input port we

a - The Wire to be connected to input port a

o - The Wire to be connected to output port o

INIT - The String assignment for generic INIT

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  Wire d,
                  Wire we,
                  Wire a,
                  Wire o,
                  java.lang.String INIT)

Constructs a new ram16x1s_1. The initial String parameter specifies the instance name. The final String parameters set the generics , INIT

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

d - The Wire to be connected to input port d

we - The Wire to be connected to input port we

a - The Wire to be connected to input port a

o - The Wire to be connected to output port o

INIT - The String assignment for generic INIT

ram16x1s_1

public ram16x1s_1(Node parent,
                  Wire d,
                  Wire we,
                  Wire a,
                  Wire o,
                  Wire wclk,
                  java.lang.String INIT)

Constructs a new ram16x1s_1. The final String parameters set the generics , INIT

Parameters:

parent - The parent Cell to the ram16x1s_1

d - The Wire to be connected to input port d

we - The Wire to be connected to input port we

a - The Wire to be connected to input port a

o - The Wire to be connected to output port o

wclk - The Wire to be connected to implicit port wclk

INIT - The String assignment for generic INIT

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  Wire d,
                  Wire we,
                  Wire a,
                  Wire o,
                  Wire wclk,
                  java.lang.String INIT)

Constructs a new ram16x1s_1. The initial String parameter specifies the instance name. The final String parameters set the generics , INIT

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

d - The Wire to be connected to input port d

we - The Wire to be connected to input port we

a - The Wire to be connected to input port a

o - The Wire to be connected to output port o

wclk - The Wire to be connected to implicit port wclk

INIT - The String assignment for generic INIT

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3)

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

Parameters:

parent - The parent Cell to the ram16x1s_1

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String INIT)

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

Parameters:

parent - The parent Cell to the ram16x1s_1

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

INIT - The String assignment for generic INIT

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3)

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String INIT)

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name. The final String parameters set the generics , INIT

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

INIT - The String assignment for generic INIT

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String s4,
                  Wire w4)

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

Parameters:

parent - The parent Cell to the ram16x1s_1

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

s4 - The name of the port to which w4 will be connected

w4 - The Wire to be connected to the port specified by s4

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String s4,
                  Wire w4,
                  java.lang.String INIT)

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports. The final String parameters set the generics , INIT

Parameters:

parent - The parent Cell to the ram16x1s_1

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

s4 - The name of the port to which w4 will be connected

w4 - The Wire to be connected to the port specified by s4

INIT - The String assignment for generic INIT

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String s4,
                  Wire w4)

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports. The initial String parameter specifies the instance name.

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

s4 - The name of the port to which w4 will be connected

w4 - The Wire to be connected to the port specified by s4

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  java.lang.String s0,
                  Wire w0,
                  java.lang.String s1,
                  Wire w1,
                  java.lang.String s2,
                  Wire w2,
                  java.lang.String s3,
                  Wire w3,
                  java.lang.String s4,
                  Wire w4,
                  java.lang.String INIT)

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports. The initial String parameter specifies the instance name. The final String parameters set the generics , INIT

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

s0 - The name of the port to which w0 will be connected

w0 - The Wire to be connected to the port specified by s0

s1 - The name of the port to which w1 will be connected

w1 - The Wire to be connected to the port specified by s1

s2 - The name of the port to which w2 will be connected

w2 - The Wire to be connected to the port specified by s2

s3 - The name of the port to which w3 will be connected

w3 - The Wire to be connected to the port specified by s3

s4 - The name of the port to which w4 will be connected

w4 - The Wire to be connected to the port specified by s4

INIT - The String assignment for generic INIT

ram16x1s_1

public ram16x1s_1(Node parent,
                  ArgBlockList abl)

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList. Any generic assignments are made through String-String pairs in the ArgBlockList.

Parameters:

parent - The parent Cell to the ram16x1s_1

abl - The list of String-Wire pairs for port assignments, and String-String pairs for generic assignments.

ram16x1s_1

public ram16x1s_1(Node parent,
                  java.lang.String instanceName,
                  ArgBlockList abl)

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList. Any generic assignments are made through String-String pairs in the ArgBlockList. The initial String parameter is the instance name.

Parameters:

parent - The parent Cell to the ram16x1s_1

instanceName - The instance name of the ram16x1s_1

abl - The list of String-Wire pairs for port assignments, and String-String pairs for generic assignments.

Method Detail

getCellName

public java.lang.String getCellName()

Description copied from class: Cell

Access the cell name associated with a derived class. The cellname field is lazily evaluated on the first call of this method. Can be overriden to make cellname different by instance. If the field does not exist, this defaults to the classname.

Overrides:

getCellName in class Cell

Returns:

the cell name associated with a derived class, null if not declared.

isAsynchronousSourceSinkResolved

public final boolean isAsynchronousSourceSinkResolved()

Overrides:

isAsynchronousSourceSinkResolved in class Cell

cellInterfaceDeterminesUniqueNetlistStructure

public final boolean cellInterfaceDeterminesUniqueNetlistStructure()

Description copied from class: Cell

When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size. Overriding this method to return true allows JHDL to save memory and netlists to be smaller by sharing the netlist structures that are guaranteed to be identical. NOTE: Do not override this unless every possible condition responsible for structural differences in a class (types and amount of children cells created, and arrangements of wires connected to ports) is included in the cellInterface[] of that class.

Overrides:

cellInterfaceDeterminesUniqueNetlistStructure in class Cell

Returns:

false if not overridden, preventing all memory sharing

clock

public final void clock()

Description copied from class: Structural

Users define synchronous behavior in this method using standard JHDL constructs. The simulator detects whether clock() has been implemented by calling this function directly and checking for an exception.

Specified by:

clock in interface Clockable

Overrides:

clock in class Structural

propagate

public final void propagate()

Description copied from class: Structural

Users defined propagatable behavior using standard JHDL constructs. The simulator detects whether propagate() has been implemented by calling function directly and checking for an exception.

Specified by:

propagate in interface byucc.jhdl.base.Propagateable

Overrides:

propagate in class Structural

reset

public void reset()

Description copied from class: Structural

If you define a behavior, you must also define a reset method for resetting the synchonous part of your model. If the user forgets to implement this, he will be reminded at simulation time.

Specified by:

reset in interface Clockable

Overrides:

reset in class BasicMemory

isNetlistLeaf

public boolean isNetlistLeaf()

Description copied from class: Cell

A few rare cells are leafCells during netlisting, but not during simulation. Overriding this method should allow that behavior.

Overrides:

isNetlistLeaf in class Cell

Returns:

true is this cell is a leaf during netlisting, false otherwise.

type

public int type()

Description copied from interface: PreDefinedSchematic

This method returns one of the predefined schematic constants to identify the type of this cell.

Specified by:

type in interface PreDefinedSchematic

Returns:

A predefined schematic constant

main

public static void main(java.lang.String[] argv)

test

public static void test()