byucc.jhdl.Xilinx
Interface LutRam

All Known Implementing Classes:
ram128x1s, ram128x1s_1, ram16x1, ram16x1d, ram16x1d, ram16x1d, ram16x1d_1, ram16x1d_1, ram16x1s, ram16x1s, ram16x1s, ram16x1s_1, ram16x1s_1, ram16x2d, ram16x2d, ram16x2d, ram16x2s, ram16x2s, ram16x2s, ram16x4d, ram16x4d, ram16x4d, ram16x4s, ram16x4s, ram16x4s, ram16x8d, ram16x8d, ram16x8d, ram16x8s, ram16x8s, ram16x8s, ram32x1, ram32x1d, ram32x1d_1, ram32x1s, ram32x1s, ram32x1s, ram32x1s_1, ram32x1s_1, ram32x2s, ram32x2s, ram32x2s, ram32x4s, ram32x4s, ram32x4s, ram32x8s, ram32x8s, ram32x8s, ram64x1d, ram64x1d_1, ram64x1s, ram64x1s_1, ram64x2s

public interface LutRam

This interface is a tag to the XC4000TechMapper that indicates special placement properties. A LutRam cell has some form of RAM, which constrains the kind of routing available to the flip-flops in the same CLB.




Copyright ? 2006 Brigham Young University, Configurable Computing Laboratory. All Rights Reserved.