|
Class Summary |
| add1 |
See the Xilinx Libraries Guide for details. |
| adsu1 |
See the Xilinx Libraries Guide for details. |
| and2 |
This class implements and asynchronous 2-input and gate. |
| and2_g |
This class implements and asynchronous 2-input and gate. |
| and2b1 |
This class implements and asynchronous 2-input and gate. |
| and2b2 |
This class implements and asynchronous 2-input and gate. |
| and3 |
This class implements and asynchronous 3-input and gate. |
| and3_g |
This class implements and asynchronous 3-input and gate. |
| and3b1 |
This class implements and asynchronous 3-input and gate. |
| and3b2 |
This class implements and asynchronous 3-input and gate. |
| and3b3 |
This class implements and asynchronous 3-input and gate. |
| and4 |
This class implements and asynchronous 4-input and gate. |
| and4_g |
This class implements and asynchronous 4-input and gate. |
| and4b1 |
This class implements and asynchronous 4-input and gate. |
| and4b2 |
This class implements and asynchronous 4-input and gate. |
| and4b3 |
This class implements and asynchronous 4-input and gate. |
| and4b4 |
This class implements and asynchronous 4-input and gate. |
| and5 |
This class implements and asynchronous 5-input and gate. |
| and5_g |
This class implements and asynchronous 5-input and gate. |
| and6 |
This class implements and asynchronous 6-input and gate. |
| and6_g |
This class implements and asynchronous 6-input and gate. |
| and7 |
This class implements and asynchronous 7-input and gate. |
| and7_g |
This class implements and asynchronous 7-input and gate. |
| and8 |
This class implements and asynchronous 8-input and gate. |
| and8_g |
This class implements and asynchronous 8-input and gate. |
| and9 |
This class implements and asynchronous 9-input and gate. |
| and9_g |
This class implements and asynchronous 9-input and gate. |
| andX |
This class implements an AND gate with arbitrary number of inputs. |
| andX_g |
|
| buf |
BUF is a general purpose, non-inverting buffer. |
| buf_g |
The BUF_G is a generic-width non-inverting buffer cell. |
| bufe |
BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple tristate
buffers with inputs I, I3 - I0, I7 - I0, and I15 - I0,
respectively; outputs O, O3 - O0, O7 - O0, and O15 - O0,
respectively; and active-High output enable (E). |
| bufg |
The BUFG cell is a global buffer which distributes high-fanout
clock signals throughout the device. |
| bufgp |
The BUFG cell is a global buffer which distributes high-fanout
clock signals throughout the device. |
| bufgsr |
See the Xilinx Libraries guide for details. |
| buft |
BUFT is a 3-state buffer with input I, output O, and active-Low
output enable (T). |
| buft_g |
The BUFT_G is a generic-width tristate buffer cell. |
| CountingLinkedList |
|
| d3_8e |
The d3_8e class implements an enabled 3:8 decoder. |
| fd |
D is a single D-type flip-flop with data input (D) and data output
(Q). |
| fd_1 |
FD_1 is a single D-type flip-flop with data input (D) and data
output (Q). |
| fdc |
FDC is a single D-type flip-flop with data (D) and asynchronous
clear (CLR) inputs and data output (Q). |
| fdc_1 |
FDC_1 is a single D-type flip-flop with data input (D),
asynchronous clear input (CLR), and data output (Q). |
| fdc_1_g |
Implements an asynchronously clearable register in the XC4000
library. |
| fdc_g |
Implements an asynchronously clearable register in the XC4000
library. |
| fdce |
The FDCE is an asynchronously cleared, enabled D-type flip-flop. |
| fdce_1 |
FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE),
asynchronous clear (CLR) inputs, and data output (Q). |
| fdce_g |
The FDCE_G is a generic-width, asynchronously cleared, enabled
D-type flip-flop. |
| fdcp |
FDCP is a single D-type flip-flop with data (D), asynchronous set
(PRE), and asynchronous reset (CLR) inputs and data output (Q). |
| fdcp_g |
Implements an asynchronously settable/clearable register in the XC4000
library. |
| fdcpe |
FDRSE is a single D-type flip-flop with synchronous reset (CLR),
synchronous set (PRE), and clock enable (CE) inputs and data output
(Q). |
| fde |
FDE is a single D-type flip-flop with data input (D), clock enable
(CE), and data output (Q). |
| fde_1 |
FDE_1 is a single D-type flip-flop with data input (D), clock
enable (CE), and data output (Q). |
| fdp |
FDP is a single D-type flip-flop with data (D) and asynchronous
preset (PRE) inputs and data output (Q). |
| fdp_1 |
FDP_1 is a single D-type flip-flop with data (D) and asynchronous
preset (PRE) inputs and data output (Q). |
| fdp_1_g |
Implements an asynchronously settable register in the XC4000
library. |
| fdp_g |
Implements an asynchronously settable register in the XC4000
library. |
| fdpe |
The FDPE is an asynchronously preset, enabled D-type flip-flop. |
| fdpe_1 |
FDPE_1 is a single D-type flip-flop with data (D), clock enable
(CE), and asynchronous preset (PRE) inputs and data output (Q). |
| fdpe_g |
The FDCE_P is a generic-width, asynchronously preset, enabled
D-type flip-flop. |
| fdr |
FDR is a D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdr_1 |
FDR_1 is a single D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdr_1_g |
FDR is a D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdr_g |
FDR is a D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). |
| fdre |
FDRE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). |
| fdre_1 |
FDRE_1 is a single D-type flip-flop with data (D), clock enable
(CE), and synchronous reset (R) inputs and data output (Q). |
| fdre_1_g |
FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). |
| fdre_g |
FDRE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). |
| fdrs |
FDRS is a single D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_1 |
FDRS_1 is a single D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_1_g |
FDRS_1 is a D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrs_g |
FDRS is a D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). |
| fdrse |
FDRSE is a single D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_1 |
FDRSE_1 is a single D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_1_g |
FDRSE is a D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fdrse_g |
FDRSE is a D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output
(Q). |
| fds |
FDS is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fds_1 |
FDS_1 is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fds_1_g |
FDS_1 is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fds_g |
FDS is a D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). |
| fdse |
FDSE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fdse_1 |
FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fdse_1_g |
FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fdse_g |
FDSE is a D-type flip-flop with data (D), clock enable (CE), and
synchronous set (S) inputs and data output (Q). |
| fmap |
The FMAP symbol is used to control logic partitioning into XC4000
family 4-input function generators. |
| ftcp |
Asynchronously presettable/clearable toggle flip-flop. |
| gnd |
This class is the GND cell for the Xilinx tools as well as
for JHDL simulation. |
| ibuf |
IBUF is a single input buffer. |
| ibuf_ann |
IBUF is a single input buffer. |
| ibuf_g |
IBUF is a single input buffer. |
| ibufg |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_agp |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_ctt |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_gtl |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_gtlp |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_hstl_i |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_hstl_iii |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_hstl_iv |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_lvcmos2 |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_pci33_3 |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_pci33_5 |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_pci66_3 |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_sstl2_i |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_sstl2_ii |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_sstl3_i |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ibufg_sstl3_ii |
IBUFG and its variants (listed below) are dedicated input buffers
for connecting to the clock buffer (BUFG) or CLKDLL. |
| ifd |
The IFD D-type flip-flop is contained in an input/output block
(IOB). |
| ifd_1 |
The IFD_1 D-type flip-flop is contained in an input/output block
(IOB) except for XC5200. |
| ifdi |
The IFDI D-type flip-flop is contained in an input/output block
(IOB). |
| ifdi_1 |
The IFDI_1 D-type flip-flop is contained in an input/output block
(IOB). |
| ifdx |
The IFDX D-type flip-flop is contained in an input/output block
(IOB). |
| ifdxi |
The IFDXI D-type flip-flop is contained in an input/output block
(IOB). |
| ildx_1 |
ILDX_1 is a transparent data latch, which can be used to hold
transient data entering a chip. |
| ildxi_1 |
ILDXI_1 is a transparent data latch, which can hold transient data
entering a chip. |
| inv |
The INV cell is an asynchronous inverter. |
| inv_g |
The INV_G is a generic-width inverter cell. |
| iopad |
Deprecated. iopads are not necessary. |
| ipad |
Deprecated. ipads are not necessary. |
| ipad_sim |
Deprecated. ipads are not necessary. |
| ld |
LD is a transparent data latch. |
| m2_1 |
The M2_1 multiplexer chooses one data bit from two sources (D1 or
D0) under the control of the select input (S0). |
| m2_1_g |
The M2_1 multiplexer is a generic-width 2:1 multiplexer. |
| nand2 |
This class implements and asynchronous 2-input nand gate. |
| nand2_g |
This class implements and asynchronous 2-input nand gate. |
| nand2b1 |
This class implements and asynchronous 2-input nand gate. |
| nand2b2 |
This class implements and asynchronous 2-input nand gate. |
| nand3 |
This class implements and asynchronous 3-input nand gate. |
| nand3_g |
This class implements and asynchronous 3-input nand gate. |
| nand3b1 |
This class implements and asynchronous 3-input nand gate. |
| nand3b2 |
This class implements and asynchronous 3-input nand gate. |
| nand3b3 |
This class implements and asynchronous 3-input nand gate. |
| nand4 |
This class implements and asynchronous 4-input nand gate. |
| nand4_g |
This class implements and asynchronous 4-input nand gate. |
| nand4b1 |
This class implements and asynchronous 4-input nand gate. |
| nand4b2 |
This class implements and asynchronous 4-input nand gate. |
| nand4b3 |
This class implements and asynchronous 4-input nand gate. |
| nand4b4 |
This class implements and asynchronous 4-input nand gate. |
| nand5 |
This class implements and asynchronous 5-input nand gate. |
| nand5_g |
This class implements and asynchronous 5-input nand gate. |
| nand6 |
This class implements and asynchronous 6-input nand gate. |
| nand6_g |
This class implements and asynchronous 6-input nand gate. |
| nand7 |
This class implements and asynchronous 7-input nand gate. |
| nand7_g |
This class implements and asynchronous 7-input nand gate. |
| nand8 |
This class implements and asynchronous 8-input nand gate. |
| nand8_g |
This class implements and asynchronous 8-input nand gate. |
| nand9 |
This class implements and asynchronous 9-input nand gate. |
| nand9_g |
This class implements and asynchronous 9-input nand gate. |
| nandX |
This class implements an NAND gate with arbitrary number of inputs. |
| nandX_g |
|
| NetworkWireList |
|
| nor2 |
This class implements and asynchronous 2-input nor gate. |
| nor2_g |
This class implements and asynchronous 2-input nor gate. |
| nor2b1 |
This class implements and asynchronous 2-input nor gate. |
| nor2b2 |
This class implements and asynchronous 2-input nor gate. |
| nor3 |
This class implements and asynchronous 3-input nor gate. |
| nor3_g |
This class implements and asynchronous 3-input nor gate. |
| nor3b1 |
This class implements and asynchronous 3-input nor gate. |
| nor3b2 |
This class implements and asynchronous 3-input nor gate. |
| nor3b3 |
This class implements and asynchronous 3-input nor gate. |
| nor4 |
This class implements and asynchronous 4-input nor gate. |
| nor4_g |
This class implements and asynchronous 4-input nor gate. |
| nor4b1 |
This class implements and asynchronous 4-input nor gate. |
| nor4b2 |
This class implements and asynchronous 4-input nor gate. |
| nor4b3 |
This class implements and asynchronous 4-input nor gate. |
| nor4b4 |
This class implements and asynchronous 4-input nor gate. |
| nor5 |
This class implements and asynchronous 5-input nor gate. |
| nor5_g |
This class implements and asynchronous 5-input nor gate. |
| nor6 |
This class implements and asynchronous 6-input nor gate. |
| nor6_g |
This class implements and asynchronous 6-input nor gate. |
| nor7 |
This class implements and asynchronous 7-input nor gate. |
| nor7_g |
This class implements and asynchronous 7-input nor gate. |
| nor8 |
This class implements and asynchronous 8-input nor gate. |
| nor8_g |
This class implements and asynchronous 8-input nor gate. |
| nor9 |
This class implements and asynchronous 9-input nor gate. |
| nor9_g |
This class implements and asynchronous 9-input nor gate. |
| norX |
This class implements an NOR gate with arbitrary number of inputs. |
| norX_g |
|
| obuf |
OBUF is a single output buffer. |
| obuf_ann |
OBUF is a single output buffer. |
| obuf_g |
OBUF is a single output buffer. |
| obuft |
OBUFT is a single 3-state output buffer with active-low enable. |
| obuft_g |
OBUFT is a single 3-state output buffer with active-low enable. |
| ofd |
OFD, OFD4, OFD8, and OFD16 are single and multiple output D
flip-flops except for XC5200 and XC9000. |
| ofde |
OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops
whose outputs are enabled by tristate buffers. |
| ofdi |
OFDI is contained in an input/output block (IOB). |
| ofdt |
OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops
whose outputs are enabled by a tristate buffers. |
| ofdtx |
OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D
flip-flops whose outputs are enabled by a tristate buffers. |
| ofdtxi |
OFDTXI and its output buffer are contained in an input/output
block (IOB). |
| ofdx |
OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D
flip-flops. |
| ofdxi |
OFDXI is contained in an input/output block (IOB). |
| opad |
Deprecated. ipads are not necessary. |
| opad_sim |
Deprecated. ipads are not necessary. |
| or2 |
This class implements and asynchronous 2-input or gate. |
| or2_g |
This class implements and asynchronous 2-input or gate. |
| or2b1 |
This class implements and asynchronous 2-input or gate. |
| or2b2 |
This class implements and asynchronous 2-input or gate. |
| or3 |
This class implements and asynchronous 3-input or gate. |
| or3_g |
This class implements and asynchronous 3-input or gate. |
| or3b1 |
This class implements and asynchronous 3-input or gate. |
| or3b2 |
This class implements and asynchronous 3-input or gate. |
| or3b3 |
This class implements and asynchronous 3-input or gate. |
| or4 |
This class implements and asynchronous 4-input or gate. |
| or4_g |
This class implements and asynchronous 4-input or gate. |
| or4b1 |
This class implements and asynchronous 4-input or gate. |
| or4b2 |
This class implements and asynchronous 4-input or gate. |
| or4b3 |
This class implements and asynchronous 4-input or gate. |
| or4b4 |
This class implements and asynchronous 4-input or gate. |
| or5 |
This class implements and asynchronous 5-input or gate. |
| or5_g |
This class implements and asynchronous 5-input or gate. |
| or6 |
This class implements and asynchronous 6-input or gate. |
| or6_g |
This class implements and asynchronous 6-input or gate. |
| or7 |
This class implements and asynchronous 7-input or gate. |
| or7_g |
This class implements and asynchronous 7-input or gate. |
| or8 |
This class implements and asynchronous 8-input or gate. |
| or8_g |
This class implements and asynchronous 8-input or gate. |
| or9 |
This class implements and asynchronous 9-input or gate. |
| or9_g |
This class implements and asynchronous 9-input or gate. |
| orX |
This class implements an OR gate with arbitrary number of inputs. |
| orX_g |
|
| pulldown |
PULLDOWN resistor elements are available in each XC4000
Input/Output Block (IOB). |
| pulldown_g |
The PULLDOWN_G is a generic-width pulldown resistor cell. |
| pullup |
The pull-up element establishes a High logic level for open-drain
elements and macros (DECODE, WAND, WORAND) or 3-state nodes (TBUF)
when all the drivers are off. |
| pullup_g |
The PULLUP_G is a generic-width pullup resistor cell. |
| SimulationBuffer |
|
| TESTXC9000Library |
This class is the self-test controller for the XC9000 library. |
| TMCellList |
|
| upad |
A UPAD allows the use of any unbonded IOBs in a device. |
| vcc |
This class is the VCC cell for the Xilinx tools as well as
for JHDL simulation. |
| XC9000PlacementInfo |
|
| XC9000TechMapper |
This is the tech-mapper for the XC9000 library. |
| XilinxTechMapper |
Simple extension of TechMapper class. |
| xnor2 |
This class implements and asynchronous 2-input xnor gate. |
| xnor2_g |
This class implements and asynchronous 2-input xnor gate. |
| xnor3 |
This class implements and asynchronous 3-input xnor gate. |
| xnor3_g |
This class implements and asynchronous 3-input xnor gate. |
| xnor4 |
This class implements and asynchronous 4-input xnor gate. |
| xnor4_g |
This class implements and asynchronous 4-input xnor gate. |
| xnor5 |
This class implements and asynchronous 5-input xnor gate. |
| xnor5_g |
This class implements and asynchronous 5-input xnor gate. |
| xnor6 |
This class implements and asynchronous 6-input xnor gate. |
| xnor6_g |
This class implements and asynchronous 6-input xnor gate. |
| xnor7 |
This class implements and asynchronous 7-input xnor gate. |
| xnor7_g |
This class implements and asynchronous 7-input xnor gate. |
| xnor8 |
This class implements and asynchronous 8-input xnor gate. |
| xnor8_g |
This class implements and asynchronous 8-input xnor gate. |
| xnor9 |
This class implements and asynchronous 9-input xnor gate. |
| xnor9_g |
This class implements and asynchronous 9-input xnor gate. |
| xnorX |
This class implements an XNOR gate with arbitrary number of inputs. |
| xor2 |
This class implements and asynchronous 2-input xor gate. |
| xor2_g |
This class implements and asynchronous 2-input xor gate. |
| xor3 |
This class implements and asynchronous 3-input xor gate. |
| xor3_g |
This class implements and asynchronous 3-input xor gate. |
| xor4 |
This class implements and asynchronous 4-input xor gate. |
| xor4_g |
This class implements and asynchronous 4-input xor gate. |
| xor5 |
This class implements and asynchronous 5-input xor gate. |
| xor5_g |
This class implements and asynchronous 5-input xor gate. |
| xor6 |
This class implements and asynchronous 6-input xor gate. |
| xor6_g |
This class implements and asynchronous 6-input xor gate. |
| xor7 |
This class implements and asynchronous 7-input xor gate. |
| xor7_g |
This class implements and asynchronous 7-input xor gate. |
| xor8 |
This class implements and asynchronous 8-input xor gate. |
| xor8_g |
This class implements and asynchronous 8-input xor gate. |
| xor9 |
This class implements and asynchronous 9-input xor gate. |
| xor9_g |
This class implements and asynchronous 9-input xor gate. |
| xorX |
This class implements an XOR gate with arbitrary number of inputs. |
| Xwire |
This class subclasses the class byucc.jhdl.Xilinx.Xwire. |