Uses of Interface
byucc.jhdl.base.MemoryInterface

Packages that use MemoryInterface

byucc.jhdl.Xilinx
byucc.jhdl.Xilinx.Virtex
byucc.jhdl.Xilinx.Virtex.Modules
byucc.jhdl.Xilinx.Virtex2
byucc.jhdl.Xilinx.Virtex2.RamPack
byucc.jhdl.Xilinx.XC4000
byucc.jhdl.Xilinx.XC4000.Modules

Uses of MemoryInterface in byucc.jhdl.Xilinx

Classes in byucc.jhdl.Xilinx that implement MemoryInterface

class	BasicMemory This layer of memory abstraction does what "Memory" used to, except doesn't implement ExternallyUpdateable.
class	Memory This layer of Memory abstraction extends BasicMemory and simply adds the ExternallyUpdateable interface
class	Memory_1 This layer of Memory abstraction extends BasicMemory and simply adds the ExternallyUpdateable interface
class	XilinxBasicMemoryCL This is exactly the same as XilinxMemoryCL, but it doesn't have ExternallyUpdateable in it's ancestory.
class	XilinxMemoryCL
class	XilinxMemorySynch
class	XilinxMemorySynch_1

Uses of MemoryInterface in byucc.jhdl.Xilinx.Virtex

Classes in byucc.jhdl.Xilinx.Virtex that implement MemoryInterface

class	BlockRamView This class provides the \"storage\" space for the sake of the simulator.
class	lut1 LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
class	lut1_d LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
class	lut1_l LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
class	lut2 LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
class	lut2_d LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
class	lut2_l LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
class	lut3 LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
class	lut3_d LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
class	lut3_l LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
class	lut4 LUT4 is a 4-bit look-up-table (LUT) with general output (O).
class	lut4_d LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
class	lut4_l LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
class	ram16x1d RAM16X1D is a 16-word by 1-bit static dual-ported RAM.
class	ram16x1d_1 RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.
class	ram16x1s RAM16X1S is a synchronous 16-word by 1-bit static RAM.
class	ram16x1s_1 RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.
class	ram16x2d RAM16X2D is a 16-word by 2-bit static dual-ported RAM.
class	ram16x2s RAM16X2S is a synchronous 16-word by 2-bit static RAM.
class	ram16x4d RAM16X4D is a 16-word by 4-bit static dual-ported RAM.
class	ram16x4s RAM16X4S is a synchronous 16-word by 4-bit static RAM.
class	ram16x8d RAM16X8D is a 16-word by 8-bit static dual-ported RAM.
class	ram16x8s RAM16X8S is a synchronous 16-word by 8-bit static RAM.
class	ram32x1s RAM32X1S is a synchronous 32-word by 1-bit static RAM.
class	ram32x1s_1 RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability.
class	ram32x1s_ack
class	ram32x2s RAM32X2S is a synchronous 32-word by 2-bit static RAM.
class	ram32x4s RAM32X4S is a synchronous 32-word by 4-bit static RAM.
class	ram32x8s RAM32X8S is a synchronous 32-word by 8-bit static RAM.
class	rom16x1 ROM16X1 is a 16-word by 1-bit ROM.
class	rom32x1 ROM32X1 is a 32-word by 1-bit ROM.
class	srl16 SRL16 is a shift register look up table (LUT).
class	srl16_1 SRL16_1 is a shift register look up table (LUT).
class	srl16e SRL16E is a shift register look up table (LUT).
class	srl16e_1 SRL16E_1 is a shift register look up table (LUT).

Uses of MemoryInterface in byucc.jhdl.Xilinx.Virtex.Modules

Classes in byucc.jhdl.Xilinx.Virtex.Modules that implement MemoryInterface

class

ramrom Generic Ram or Rom generator

Uses of MemoryInterface in byucc.jhdl.Xilinx.Virtex2

Classes in byucc.jhdl.Xilinx.Virtex2 that implement MemoryInterface

class	BlockRamViewParity Deprecated. Use BlockRamView in RamPack instead.
class	ram128x1s RAM128X1S is a 128-word by 1-bit static random access memory with synchronous write capability.
class	ram128x1s_1 RAM128X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability.
class	ram32x1d RAM32X1D is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.
class	ram32x1d_1 RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
class	ram64x1d RAM64X1D is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.
class	ram64x1d_1 RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
class	ram64x1s RAM64X1S is a 64-word by 1-bit static random access memory with synchronous write capability.
class	ram64x1s_1 RAM64X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability and a negative-edge clock.
class	ram64x2s RAM64X2S is a 64-word by 2-bit static random access memory with synchronous write capability.
class	Rom128x1View This class is for the simulation of block ram's to work correctly.
class	Rom256x1View This class is for the simulation of block ram's to work correctly.
class	Rom64x1View This class is for the simulation of block ram's to work correctly.
class	srlc16 SRLC16 is a shift register look up table (LUT).
class	srlc16_1 SRLC16_1 is a shift register look up table (LUT).
class	srlc16e SRLC16E is a shift register look up table (LUT) with carry, clock enable, and asynchro-nous clear.
class	srlc16e_1 SRLC16E_1 is a shift register look up table (LUT).

Uses of MemoryInterface in byucc.jhdl.Xilinx.Virtex2.RamPack

Classes in byucc.jhdl.Xilinx.Virtex2.RamPack that implement MemoryInterface

class

BlockRamViewL This class is for the simulation of block ram's to work correctly.

Uses of MemoryInterface in byucc.jhdl.Xilinx.XC4000

Classes in byucc.jhdl.Xilinx.XC4000 that implement MemoryInterface

class	ram16x1 RAM16X1 is a 16-word by 1-bit static RAM.
class	ram32x1 RAM32X1 is a 32-word by 1-bit static RAM.

Uses of MemoryInterface in byucc.jhdl.Xilinx.XC4000.Modules

Classes in byucc.jhdl.Xilinx.XC4000.Modules that implement MemoryInterface

class

delay XC4000 Delay Line