Uses of Interface
byucc.jhdl.base.Clockable

Packages that use Clockable

byucc.jhdl.apps.dtb
byucc.jhdl.apps.Stimulator
byucc.jhdl.apps.Tbone
byucc.jhdl.apps.Viewers.cvt
byucc.jhdl.base
byucc.jhdl.contrib.modgen
byucc.jhdl.contrib.modgen.AddSubPack
byucc.jhdl.contrib.modgen.CordicPack
byucc.jhdl.contrib.modgen.IntDividePack
byucc.jhdl.contrib.modgen.MultArrayPack
byucc.jhdl.CSRC
byucc.jhdl.DRC
byucc.jhdl.DRC.Tester
byucc.jhdl.examples
byucc.jhdl.examples.des
byucc.jhdl.examples.editDistance
byucc.jhdl.examples.fsm
byucc.jhdl.examples.shifter
byucc.jhdl.examples.xr16cpu
byucc.jhdl.Fsm
byucc.jhdl.Logic
byucc.jhdl.Logic.Modules
byucc.jhdl.Logic.Modules.CordicPack
byucc.jhdl.Logic.Modules.DigitSerial
byucc.jhdl.Logic.Modules.FloatingPoint
byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2
byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8
byucc.jhdl.Logic.Modules.FloatingPoint.examples
byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack
byucc.jhdl.Logic.Modules.FloatingPoint.helpers
byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack
byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4
byucc.jhdl.Logic.Modules.FloatingPoint.SqPack
byucc.jhdl.Logic.Modules.helpers
byucc.jhdl.Logic.Modules.ShiftRegPack
byucc.jhdl.netlisters.jhdl
byucc.jhdl.platforms.util
byucc.jhdl.platforms.util.multicontext
byucc.jhdl.synth
byucc.jhdl.TERA
byucc.jhdl.Xilinx
byucc.jhdl.Xilinx.Virtex
byucc.jhdl.Xilinx.Virtex.helpers
byucc.jhdl.Xilinx.Virtex.Modules
byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack
byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack
byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack
byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack
byucc.jhdl.Xilinx.Virtex.ramb4_wrapper
byucc.jhdl.Xilinx.Virtex2
byucc.jhdl.Xilinx.Virtex2.Modules
byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint
byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack
byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack
byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack
byucc.jhdl.Xilinx.Virtex2.RamPack
byucc.jhdl.Xilinx.XC4000
byucc.jhdl.Xilinx.XC4000.carryLogic
byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack
byucc.jhdl.Xilinx.XC9000

Uses of Clockable in byucc.jhdl.apps.dtb

Classes in byucc.jhdl.apps.dtb that implement Clockable

class

DynamicTestBench The DynamicTestBench acts as a quick replacement for a full, formal TestBench written by the user.

Uses of Clockable in byucc.jhdl.apps.Stimulator

Classes in byucc.jhdl.apps.Stimulator that implement Clockable

class	Stimulator An interactive stimulator.
class	TriStateStimulator Extends the Stimulator to perform puts on tri-state buses.

Uses of Clockable in byucc.jhdl.apps.Tbone

Classes in byucc.jhdl.apps.Tbone that implement Clockable

class

Tbone Tbone is a generic test bench used to simulate a circuit.

Uses of Clockable in byucc.jhdl.apps.Viewers.cvt

Classes in byucc.jhdl.apps.Viewers.cvt that implement Clockable

class

DesktopTest

Uses of Clockable in byucc.jhdl.base

Classes in byucc.jhdl.base that implement Clockable

class	DefaultSubCell
class	Structural If the node only contains instantiations of other kinds of nodes, this is the container class to use.
class	Synchronous Base class for defining a synchronous circuit element.
class	temp_cell Used by BV for testing

Methods in byucc.jhdl.base with parameters of type Clockable

void	HWSystem.useHWUpdate(Clockable cell, boolean flag) This tells the simulator that you will use HWUpdate mode to update the state of the Clockable cell you pass as the argument.
protected void	CompiledCodeGenerator.generateCodeForClockable(Clockable c)

Uses of Clockable in byucc.jhdl.contrib.modgen

Classes in byucc.jhdl.contrib.modgen that implement Clockable

class	accum Accumulator that allows a generic sized input and output.
class	Add Deprecated. Use Logic add call instead (Add was deprecated since it is XC4000 specific)
class	Adsu Deprecated. Use Logic addsub call instead (AddSub was deprecated since it is XC4000 specific).
class	Cordic Generic width CORDIC unit for Xilinx XC4000.
class	Cordicl Generic width linear CORDIC unit for Xilinx XC4000.
class	CordicRP Generic width CORDIC unit for Xilinx Virtex.
class	eq General Description
class	gt Generic greater-than comparator.
class	IntDivide Variable width integer divider with the option of signed or unsigned multiply and generic pipeline depth.
class	LFSR4 4 bit linear feedback shift register.
class	lt Generic less-than comparator.
class	rounder
class	StageRP
class	Sub Deprecated. Use Logic sub call instead (Sub was deprecated since it is XC4000 specific).

Uses of Clockable in byucc.jhdl.contrib.modgen.AddSubPack

Classes in byucc.jhdl.contrib.modgen.AddSubPack that implement Clockable

class	ADD_F_CI
class	ADD_FG_CI
class	ADD_G_F1
class	ADDSUB_F_CI
class	ADDSUB_FG_CI
class	ADDSUB_G_F1
class	ADDSUB_G_F3_
class	SUB_F_CI
class	SUB_FG_CI
class	SUB_G_1
class	SUB_G_F1

Uses of Clockable in byucc.jhdl.contrib.modgen.CordicPack

Classes in byucc.jhdl.contrib.modgen.CordicPack that implement Clockable

class	Col_reg
class	Cordic_ctrl
class	Cordicl_ctrl
class	End_rot
class	Init_rot
class	Pipe_sigs
class	Stage
class	Stagel
class	Tc_mux
class	Z_Mux

Uses of Clockable in byucc.jhdl.contrib.modgen.IntDividePack

Classes in byucc.jhdl.contrib.modgen.IntDividePack that implement Clockable

class	AddPass
class	AddPassGeneric
class	AddPassVirtex
class	AddPassXC4000
class	tbcomp_IntDivide

Uses of Clockable in byucc.jhdl.contrib.modgen.MultArrayPack

Classes in byucc.jhdl.contrib.modgen.MultArrayPack that implement Clockable

class	MultAddGeneric
class	MultSubGeneric

Uses of Clockable in byucc.jhdl.CSRC

Classes in byucc.jhdl.CSRC that implement Clockable

class	addsubX Generic width adder-subtractor.
class	addX Generic width adder.
class	and2_dp This class implements and asynchronous 2-input and gate.
class	and2_dp_g This class implements and asynchronous 2-input and gate.
class	and3_dp This class implements and asynchronous 3-input and gate.
class	and3_dp_g This class implements and asynchronous 3-input and gate.
class	and4_dp This class implements and asynchronous 4-input and gate.
class	and5_dp This class implements and asynchronous 5-input and gate.
class	and6_dp This class implements and asynchronous 6-input and gate.
class	and7_dp This class implements and asynchronous 7-input and gate.
class	and8_dp This class implements and asynchronous 8-input and gate.
class	and9_dp This class implements and asynchronous 9-input and gate.
class	andX This class implements an AND gate with arbitrary number of inputs.
class	buf Buffer.
class	bufX This cell buffers each input wire.
class	CSRCCL
class	CSRCFD
class	dff_dp The dff_dp is a simple D-flipflop.
class	dff_dpX This instantiates a generic width dff_dp.
class	dffe_dp The dffe_dp is a D-flipflop with a clock enable.
class	dffe_dpX This instantiates a generic width dffe_dp.
class	dffr_dp The dffr_dp is a D-flipflop with a synchronous reset.
class	dffr_dpX This instantiates a generic width dffs_dp.
class	dffre_dp The dffre_dp is a D-flipflop with a synchronous reset and a clock enable.
class	dffre_dpX This instantiates a generic width dffre_dp.
class	dffs_dp The dffs_dp is a D-flipflop with a synchronous set.
class	dffs_dpX This instantiates a generic width dffr_dp.
class	dffse_dp The dffse_dp is a D-flipflop with a synchronous set and a clock enable.
class	dffse_dpX This instantiates a generic width dffse_dp.
class	gndX This instantiates a generic width vcc.
class	IB This is an input buffer.
class	IBX Generic width output buffer.
class	maj3 3-input majority gate.
class	mux_dpX Generic width 2-1 Mux.
class	mux3_dp 2-1 Mux.
class	nand2_dp This class implements and asynchronous 2-input nand gate.
class	nand2_dp_g This class implements and asynchronous 2-input nand gate.
class	nand3_dp This class implements and asynchronous 3-input nand gate.
class	nand3_dp_g This class implements and asynchronous 3-input nand gate.
class	nand4_dp This class implements and asynchronous 4-input nand gate.
class	nand5_dp This class implements and asynchronous 5-input nand gate.
class	nand6_dp This class implements and asynchronous 6-input nand gate.
class	nand7_dp This class implements and asynchronous 7-input nand gate.
class	nand8_dp This class implements and asynchronous 8-input nand gate.
class	nand9_dp This class implements and asynchronous 9-input nand gate.
class	nandX This class implements an NAND gate with arbitrary number of inputs.
class	nor2_dp This class implements and asynchronous 2-input nor gate.
class	nor2_dp_g This class implements and asynchronous 2-input nor gate.
class	nor3_dp This class implements and asynchronous 3-input nor gate.
class	nor3_dp_g This class implements and asynchronous 3-input nor gate.
class	nor4_dp This class implements and asynchronous 4-input nor gate.
class	nor5_dp This class implements and asynchronous 5-input nor gate.
class	nor6_dp This class implements and asynchronous 6-input nor gate.
class	nor7_dp This class implements and asynchronous 7-input nor gate.
class	nor8_dp This class implements and asynchronous 8-input nor gate.
class	nor9_dp This class implements and asynchronous 9-input nor gate.
class	norX This class implements an NOR gate with arbitrary number of inputs.
class	not_dp Inverter.
class	notX This cell inverts each input wire.
class	OB This is an output buffer.
class	OBT This is an output buffer with a (high?) asserted output enable.
class	OBTX Generic width output buffer.
class	OBX Generic width output buffer.
class	or2_dp This class implements and asynchronous 2-input or gate.
class	or2_dp_g This class implements and asynchronous 2-input or gate.
class	or3_dp This class implements and asynchronous 3-input or gate.
class	or3_dp_g This class implements and asynchronous 3-input or gate.
class	or4_dp This class implements and asynchronous 4-input or gate.
class	or5_dp This class implements and asynchronous 5-input or gate.
class	or6_dp This class implements and asynchronous 6-input or gate.
class	or7_dp This class implements and asynchronous 7-input or gate.
class	or8_dp This class implements and asynchronous 8-input or gate.
class	or9_dp This class implements and asynchronous 9-input or gate.
class	orX This class implements an OR gate with arbitrary number of inputs.
class	subX Generic width subtractor.
class	TESTCSRCLibrary This class is the self-test controller for the CSRC library.
class	vccX This instantiates a generic width vcc.
class	xnor2_dp This class implements and asynchronous 2-input xnor gate.
class	xnor2_dp_g This class implements and asynchronous 2-input xnor gate.
class	xnor3_dp This class implements and asynchronous 3-input xnor gate.
class	xnor3_dp_g This class implements and asynchronous 3-input xnor gate.
class	xnor4_dp This class implements and asynchronous 4-input xnor gate.
class	xnor5_dp This class implements and asynchronous 5-input xnor gate.
class	xnor6_dp This class implements and asynchronous 6-input xnor gate.
class	xnor7_dp This class implements and asynchronous 7-input xnor gate.
class	xnor8_dp This class implements and asynchronous 8-input xnor gate.
class	xnor9_dp This class implements and asynchronous 9-input xnor gate.
class	xnorX This class implements an XNOR gate with arbitrary number of inputs.
class	xor2_dp This class implements and asynchronous 2-input xor gate.
class	xor2_dp_g This class implements and asynchronous 2-input xor gate.
class	xor3_dp This class implements and asynchronous 3-input xor gate.
class	xor3_dp_g This class implements and asynchronous 3-input xor gate.
class	xor4_dp This class implements and asynchronous 4-input xor gate.
class	xor5_dp This class implements and asynchronous 5-input xor gate.
class	xor6_dp This class implements and asynchronous 6-input xor gate.
class	xor7_dp This class implements and asynchronous 7-input xor gate.
class	xor8_dp This class implements and asynchronous 8-input xor gate.
class	xor9_dp This class implements and asynchronous 9-input xor gate.
class	xorX This class implements an XOR gate with arbitrary number of inputs.

Uses of Clockable in byucc.jhdl.DRC

Classes in byucc.jhdl.DRC that implement Clockable

class	DBone A skeleton TBone-like class for checking circuits against design rules.
class	Toggler

Uses of Clockable in byucc.jhdl.DRC.Tester

Classes in byucc.jhdl.DRC.Tester that implement Clockable

class	DesignRuleCheckerTester
class	LogicMisplacement This design targets the Digilab XC4000 Spartan architecture.
class	MultiplePuts This design targets the Digilab XC4000 Spartan architecture.
class	NoBufg This design violates the rule of not running an explicit clock wire through a bufg

Uses of Clockable in byucc.jhdl.examples

Classes in byucc.jhdl.examples that implement Clockable

class	Calculator
class	FullAdder
class	NBitAdder

Uses of Clockable in byucc.jhdl.examples.des

Classes in byucc.jhdl.examples.des that implement Clockable

class	DES
class	DESLogic
class	DESRoundC
class	SBoxes

Uses of Clockable in byucc.jhdl.examples.editDistance

Classes in byucc.jhdl.examples.editDistance that implement Clockable

class	char_fsm2
class	char_slice2
class	charcomp2
class	edistance2 This is the top level code for finding the evolutionary distance between a target string which is compiled into the hardware, and a source string which is passed through the linear systolic array of character comparitors.
class	left_edge2
class	mod4count2
class	upDownCounter Counter counts up if up_down is a 1, down if up_down is a 0.

Uses of Clockable in byucc.jhdl.examples.fsm

Classes in byucc.jhdl.examples.fsm that implement Clockable

class	fsmMemCtl
class	parity

Uses of Clockable in byucc.jhdl.examples.shifter

Classes in byucc.jhdl.examples.shifter that implement Clockable

class	ShiftMuxR Right shifter mux.
class	VarShiftR Right shifter module generator This module will create an variable width right shifter with that can either do logical or arithmetic shifts

Uses of Clockable in byucc.jhdl.examples.xr16cpu

Classes in byucc.jhdl.examples.xr16cpu that implement Clockable

class	adsuovf1
class	adsuovf16
class	bram_1k
class	bram_4k
class	brir
class	control
class	datapath
class	dec16
class	lcdoutport
class	logicops
class	parinport
class	paroutport
class	regfile
class	sport
class	timerefs
class	uar
class	uat
class	xr16vx_1k
class	xr16vx_4k
class	xr16vxcpu

Uses of Clockable in byucc.jhdl.Fsm

Classes in byucc.jhdl.Fsm that implement Clockable

class	Fsm
class	SynthesizedFsm for automatic FSM Synthesis (temporarily modified from Fsm.java by navanee) main Distinction from Fsm.java is that the csWire can be seen outside and that is the only FSM output.

Uses of Clockable in byucc.jhdl.Logic

Classes in byucc.jhdl.Logic that implement Clockable

class	LibrarySelfTester This class aids in testing components of a library.
class	Logic The Logic class provides a platform-independent interface into FPGA circuit design.
class	LogicGates This class only exists to split Logic into two files so that it's easier to deal with it.
class	LogicStatic This class only exists to split Logic into two files so that it's easier to deal with it.
class	LogicSubCell This class allows calls to pushHierarchy to create a Logic cell, instead of a feature-less default.

Uses of Clockable in byucc.jhdl.Logic.Modules

Classes in byucc.jhdl.Logic.Modules that implement Clockable

class	COMPARATORS General Description
class	CORDICS General Description
class	COUNTERS General Description
class	Decoder implements an arbitrary-width decoder out of standard (wide) AND gates.
class	decoder1_2 General Description
class	decoder2_4 General Description
class	decoder3_8 General Description
class	decoder4_16 General Description
class	decoder5_32 General Description
class	decoder6_64 General Description
class	decoder7_128 General Description
class	decoder8_256 General Description
class	DECODERS General Description
class	DIVIDERS General Description
class	Duplicate simply takes the one bit input wire and replicates it for every bit of the output.
class	Encoder encodes the one-hot input value.
class	FreeRunTimer a free-running timer that triggers (times out) at a user-defined interval.
class	LogShiftL implements a barrel shifter by cascading a series of muxes.
class	LogShiftR implements a barrel shifter by cascading a series of muxes.
class	MULTIPLIERS General Description
class	OTHERS General Description
class	ParallelLeftShiftReg ParallelLeftShiftReg.java Created: Jan 03
class	ParallelRightShiftReg ParallelRightShiftReg.java Created: Jan 03
class	Reverse Completely reverses (mirrors) the bit order of the input, so that LSB becomes MSB, etc...
class	toggle General Description
class	UpDownCount General Description

Uses of Clockable in byucc.jhdl.Logic.Modules.CordicPack

Classes in byucc.jhdl.Logic.Modules.CordicPack that implement Clockable

class

carryLogic

Uses of Clockable in byucc.jhdl.Logic.Modules.DigitSerial

Classes in byucc.jhdl.Logic.Modules.DigitSerial that implement Clockable

class	DPSR
class	DS_FIR
class	DS_FIR_module
class	DSadder
class	DScontrol
class	DScross
class	DSmult_module
class	DSmult_module_last
class	DSmultiplier
class	DSPR
class	PSR
class	SPR
class	tb_DS_FIR

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint

Classes in byucc.jhdl.Logic.Modules.FloatingPoint that implement Clockable

class	FLOATINGPOINT General Description
class	FPCompare Floating-point comparator.
class	Pipe_SquareRoot General Description
class	SquareRoot General Description
class	toFixed Under construction - This module is not yet finished.
class	toFloat Fixed-point to floating-point converter (or integer to floating-point).

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2

Classes in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2 that implement Clockable

class	FPDiv_radix2
class	tb_FPDiv_radix2

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8

Classes in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8 that implement Clockable

class	FPDiv_radix8
class	tb_FPDiv_radix8

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint.examples

Classes in byucc.jhdl.Logic.Modules.FloatingPoint.examples that implement Clockable

class

toFloatExample A minimal example of toFloat.

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack

Classes in byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack that implement Clockable

class

UIntDivide This class may be moved, modified, or deprecated. A simple unsigned integer divider.

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint.helpers

Classes in byucc.jhdl.Logic.Modules.FloatingPoint.helpers that implement Clockable

class	FPPack General Description
class	FPUnpack General Description

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack

Classes in byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack that implement Clockable

class	Pipe_algorithm General Description
class	Pipe_Algorithm_Stage General Description
class	Pipe_Frac General Description
class	Pipe_Reg_e General Description
class	Pipe_Reg_f General Description
class	Pipe_Remainder General Description
class	Pipe_Scale General Description
class	Pipe_Scale_back General Description
class	Pipe_Square_root General Description
class	Pipe_Stage General Description
class	Pipe_Stages General Description

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4

Classes in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4 that implement Clockable

class	FPDiv_radix4
class	scale
class	scale_back
class	specialHandler
class	stage
class	stages
class	table
class	tb_FPDiv_radix4

Uses of Clockable in byucc.jhdl.Logic.Modules.FloatingPoint.SqPack

Classes in byucc.jhdl.Logic.Modules.FloatingPoint.SqPack that implement Clockable

class	Algorithm General Description
class	counter General Description
class	Exponent General Description
class	Frac General Description
class	Remainder General Description
class	Scale General Description
class	Scale_back General Description
class	Square_root General Description
class	Valid General Description

Uses of Clockable in byucc.jhdl.Logic.Modules.helpers

Classes in byucc.jhdl.Logic.Modules.helpers that implement Clockable

class

tb_Template Generic superclass for Module testbenches.

Uses of Clockable in byucc.jhdl.Logic.Modules.ShiftRegPack

Classes in byucc.jhdl.Logic.Modules.ShiftRegPack that implement Clockable

class

ShiftRegBit ShiftRegBit.java Created: Jan 03

Uses of Clockable in byucc.jhdl.netlisters.jhdl

Classes in byucc.jhdl.netlisters.jhdl that implement Clockable

class

BuildJHDL

Uses of Clockable in byucc.jhdl.platforms.util

Classes in byucc.jhdl.platforms.util that implement Clockable

class	GenericBoard Class designed for making the board-level of board models easier to create.
class	GenericInterfaceCell
class	GenericProcessingElement
class	GenericUserCore Base class to be used for creating wrappers for user designs.
class	Virtex_IOB This class is used to create IOBs for the Xilinx Virtex series parts.
class	XC4000_IOB

Uses of Clockable in byucc.jhdl.platforms.util.multicontext

Classes in byucc.jhdl.platforms.util.multicontext that implement Clockable

class

MultiContextTestBench

Uses of Clockable in byucc.jhdl.synth

Classes in byucc.jhdl.synth that implement Clockable

class

GraphTestBench

Uses of Clockable in byucc.jhdl.TERA

Classes in byucc.jhdl.TERA that implement Clockable

class	Constant This class is a structural cell which drives a constant value on to its output wire.
class	FD
class	muxX Generic width 2-1 Mux.
class	regX This instantiates a generic width dff.
class	tera_and2 This class implements and asynchronous 2-input and gate.
class	tera_and2_g This class implements and asynchronous 2-input and gate.
class	tera_and3 This class implements and asynchronous 3-input and gate.
class	tera_and3_g This class implements and asynchronous 3-input and gate.
class	tera_and4 This class implements and asynchronous 4-input and gate.
class	tera_and4_g This class implements and asynchronous 4-input and gate.
class	tera_and5 This class implements and asynchronous 5-input and gate.
class	tera_and5_g This class implements and asynchronous 5-input and gate.
class	tera_and6 This class implements and asynchronous 6-input and gate.
class	tera_and6_g This class implements and asynchronous 6-input and gate.
class	tera_and7 This class implements and asynchronous 7-input and gate.
class	tera_and7_g This class implements and asynchronous 7-input and gate.
class	tera_and8 This class implements and asynchronous 8-input and gate.
class	tera_and8_g This class implements and asynchronous 8-input and gate.
class	tera_dff The tera_dff is a simple D-flipflop.
class	tera_inv Inverter.
class	tera_mem Buffer.
class	tera_mux2 Mux2
class	tera_mux4 Mux4
class	tera_nand2 This class implements and asynchronous 2-input nand gate.
class	tera_nand2_g This class implements and asynchronous 2-input nand gate.
class	tera_nand3 This class implements and asynchronous 3-input nand gate.
class	tera_nand3_g This class implements and asynchronous 3-input nand gate.
class	tera_nand4 This class implements and asynchronous 4-input nand gate.
class	tera_nand4_g This class implements and asynchronous 4-input nand gate.
class	tera_nand5 This class implements and asynchronous 5-input nand gate.
class	tera_nand5_g This class implements and asynchronous 5-input nand gate.
class	tera_nand6 This class implements and asynchronous 6-input nand gate.
class	tera_nand6_g This class implements and asynchronous 6-input nand gate.
class	tera_nand7 This class implements and asynchronous 7-input nand gate.
class	tera_nand7_g This class implements and asynchronous 7-input nand gate.
class	tera_nand8 This class implements and asynchronous 8-input nand gate.
class	tera_nand8_g This class implements and asynchronous 8-input nand gate.
class	tera_nor2 This class implements and asynchronous 2-input nor gate.
class	tera_nor2_g This class implements and asynchronous 2-input nor gate.
class	tera_nor3 This class implements and asynchronous 3-input nor gate.
class	tera_nor3_g This class implements and asynchronous 3-input nor gate.
class	tera_nor4 This class implements and asynchronous 4-input nor gate.
class	tera_nor4_g This class implements and asynchronous 4-input nor gate.
class	tera_nor5 This class implements and asynchronous 5-input nor gate.
class	tera_nor5_g This class implements and asynchronous 5-input nor gate.
class	tera_nor6 This class implements and asynchronous 6-input nor gate.
class	tera_nor6_g This class implements and asynchronous 6-input nor gate.
class	tera_nor7 This class implements and asynchronous 7-input nor gate.
class	tera_nor7_g This class implements and asynchronous 7-input nor gate.
class	tera_nor8 This class implements and asynchronous 8-input nor gate.
class	tera_nor8_g This class implements and asynchronous 8-input nor gate.
class	tera_or2 This class implements and asynchronous 2-input or gate.
class	tera_or2_g This class implements and asynchronous 2-input or gate.
class	tera_or3 This class implements and asynchronous 3-input or gate.
class	tera_or3_g This class implements and asynchronous 3-input or gate.
class	tera_or4 This class implements and asynchronous 4-input or gate.
class	tera_or4_g This class implements and asynchronous 4-input or gate.
class	tera_or5 This class implements and asynchronous 5-input or gate.
class	tera_or5_g This class implements and asynchronous 5-input or gate.
class	tera_or6 This class implements and asynchronous 6-input or gate.
class	tera_or6_g This class implements and asynchronous 6-input or gate.
class	tera_or7 This class implements and asynchronous 7-input or gate.
class	tera_or7_g This class implements and asynchronous 7-input or gate.
class	tera_or8 This class implements and asynchronous 8-input or gate.
class	tera_or8_g This class implements and asynchronous 8-input or gate.
class	tera_xnor2 This class implements and asynchronous 2-input xnor gate.
class	tera_xnor2_g This class implements and asynchronous 2-input xnor gate.
class	tera_xnor3 This class implements and asynchronous 3-input xnor gate.
class	tera_xnor3_g This class implements and asynchronous 3-input xnor gate.
class	tera_xnor4 This class implements and asynchronous 4-input xnor gate.
class	tera_xnor4_g This class implements and asynchronous 4-input xnor gate.
class	tera_xnor5 This class implements and asynchronous 5-input xnor gate.
class	tera_xnor5_g This class implements and asynchronous 5-input xnor gate.
class	tera_xnor6 This class implements and asynchronous 6-input xnor gate.
class	tera_xnor6_g This class implements and asynchronous 6-input xnor gate.
class	tera_xnor7 This class implements and asynchronous 7-input xnor gate.
class	tera_xnor7_g This class implements and asynchronous 7-input xnor gate.
class	tera_xnor8 This class implements and asynchronous 8-input xnor gate.
class	tera_xnor8_g This class implements and asynchronous 8-input xnor gate.
class	tera_xor2 This class implements and asynchronous 2-input xor gate.
class	tera_xor2_g This class implements and asynchronous 2-input xor gate.
class	tera_xor3 This class implements and asynchronous 3-input xor gate.
class	tera_xor3_g This class implements and asynchronous 3-input xor gate.
class	tera_xor4 This class implements and asynchronous 4-input xor gate.
class	tera_xor4_g This class implements and asynchronous 4-input xor gate.
class	tera_xor5 This class implements and asynchronous 5-input xor gate.
class	tera_xor5_g This class implements and asynchronous 5-input xor gate.
class	tera_xor6 This class implements and asynchronous 6-input xor gate.
class	tera_xor6_g This class implements and asynchronous 6-input xor gate.
class	tera_xor7 This class implements and asynchronous 7-input xor gate.
class	tera_xor7_g This class implements and asynchronous 7-input xor gate.
class	tera_xor8 This class implements and asynchronous 8-input xor gate.
class	tera_xor8_g This class implements and asynchronous 8-input xor gate.
class	TERACL
class	TESTTERALibrary This class is the self-test controller for the TERA library.

Uses of Clockable in byucc.jhdl.Xilinx

Classes in byucc.jhdl.Xilinx that implement Clockable

class	BasicMemory This layer of memory abstraction does what "Memory" used to, except doesn't implement ExternallyUpdateable.
class	gnd This class is the GND cell for the Xilinx tools as well as for JHDL simulation.
class	Memory This layer of Memory abstraction extends BasicMemory and simply adds the ExternallyUpdateable interface
class	Memory_1 This layer of Memory abstraction extends BasicMemory and simply adds the ExternallyUpdateable interface
class	ram_base A simple wrapper class that provides an implicit clock port for ram's
class	ram_prop Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.
class	ram_prop_1 Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.
class	ram_synch Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.
class	ram_synch_1 Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.
class	ram_synch_shift Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.
class	ramd_prop Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.
class	ramd_prop_1 Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.
class	TESTXilinxLibrary This class is the self-test controller for the Xilinx library.
class	vcc This class is the VCC cell for the Xilinx tools as well as for JHDL simulation.
class	XilinxBasicMemoryCL This is exactly the same as XilinxMemoryCL, but it doesn't have ExternallyUpdateable in it's ancestory.
class	XilinxCL
class	XilinxFD
class	XilinxFD_1
class	XilinxLatch
class	XilinxLatch_1
class	XilinxMemoryCL
class	XilinxMemorySynch
class	XilinxMemorySynch_1

Uses of Clockable in byucc.jhdl.Xilinx.Virtex

Classes in byucc.jhdl.Xilinx.Virtex that implement Clockable

class	and2 This class implements and asynchronous 2-input and gate.
class	and2_g This class implements and asynchronous 2-input and gate.
class	and2b1 This class implements and asynchronous 2-input and gate.
class	and2b2 This class implements and asynchronous 2-input and gate.
class	and3 This class implements and asynchronous 3-input and gate.
class	and3_g This class implements and asynchronous 3-input and gate.
class	and3b1 This class implements and asynchronous 3-input and gate.
class	and3b2 This class implements and asynchronous 3-input and gate.
class	and3b3 This class implements and asynchronous 3-input and gate.
class	and4 This class implements and asynchronous 4-input and gate.
class	and4_g This class implements and asynchronous 4-input and gate.
class	and4b1 This class implements and asynchronous 4-input and gate.
class	and4b2 This class implements and asynchronous 4-input and gate.
class	and4b3 This class implements and asynchronous 4-input and gate.
class	and4b4 This class implements and asynchronous 4-input and gate.
class	and5 This class implements and asynchronous 5-input and gate.
class	and6 This class implements and asynchronous 6-input and gate.
class	and7 This class implements and asynchronous 7-input and gate.
class	and8 This class implements and asynchronous 8-input and gate.
class	and9 This class implements and asynchronous 9-input and gate.
class	andX_g
class	BlockRam Deprecated. See byucc.jhdl.Xilinx.Virtex.RAMB4Single and byucc.jhdl.Xilinx.Virtex.RAMB4Dual
class	BlockRamView This class provides the \"storage\" space for the sake of the simulator.
class	buf_g The BUF_G is a generic-width non-inverting buffer cell.
class	bufe BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple tristate buffers with inputs I, I3 - I0, I7 - I0, and I15 - I0, respectively; outputs O, O3 - O0, O7 - O0, and O15 - O0, respectively; and active-High output enable (E).
class	buft BUFT is a 3-state buffer with input I, output O, and active-Low output enable (T).
class	buft_g The BUFT_G is a generic-width tristate buffer cell.
class	clkdll CLKDLL is a clock delay locked loop used to minimize clock skew.
class	clkdllhf CLKDLLHF is a high frequency clock delay locked loop used to minimize clock skew.
class	d3_8e The d3_8e class implements an enabled 3:8 decoder.
class	fd D is a single D-type flip-flop with data input (D) and data output (Q).
class	fd_1 FD_1 is a single D-type flip-flop with data input (D) and data output (Q).
class	fdc FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q).
class	fdc_1 FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q).
class	fdc_1_g Implements an asynchronously clearable register in the XC4000 library.
class	fdc_g Implements an asynchronously clearable register in the XC4000 library.
class	fdce The FDCE is an asynchronously cleared, enabled D-type flip-flop.
class	fdce_1 FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs, and data output (Q).
class	fdce_g The FDCE_G is a generic-width, asynchronously cleared, enabled D-type flip-flop.
class	fdcp FDCP is a single D-type flip-flop with data (D), asynchronous set (PRE), and asynchronous reset (CLR) inputs and data output (Q).
class	fdcp_1 FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q).
class	fdcpe FDRSE is a single D-type flip-flop with synchronous reset (CLR), synchronous set (PRE), and clock enable (CE) inputs and data output (Q).
class	fdcpe_1 FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q).
class	fde FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
class	fde_1 FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
class	fdp FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
class	fdp_1 FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
class	fdp_1_g Implements an asynchronously settable register in the XC4000 library.
class	fdp_g Implements an asynchronously settable register in the XC4000 library.
class	fdpe The FDPE is an asynchronously preset, enabled D-type flip-flop.
class	fdpe_1 FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q).
class	fdpe_g The FDCE_P is a generic-width, asynchronously preset, enabled D-type flip-flop.
class	fdr FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdr_1 FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdr_1_g FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdr_g FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdre FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdre_1 FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdre_1_g FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdre_g FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdrs FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrs_1 FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrs_1_g FDRS_1 is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrs_g FDRS is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrse FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fdrse_1 FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fdrse_1_g FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fdrse_g FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fds FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fds_1 FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fds_1_g FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fds_g FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fdse FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fdse_1 FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fdse_1_g FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fdse_g FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fmap_g The fmap_g is a generic_width and generic port count wrapper for all XC4000 techmapper specific cells.
class	ibuf_g IBUF is a single input buffer.
class	ifd The IFD D-type flip-flop is contained in an input/output block (IOB).
class	ifd_1 The IFD_1 D-type flip-flop is contained in an input/output block (IOB) except for XC5200.
class	ifdi The IFDI D-type flip-flop is contained in an input/output block (IOB).
class	ifdi_1 The IFDI_1 D-type flip-flop is contained in an input/output block (IOB).
class	ifdx The IFDX D-type flip-flop is contained in an input/output block (IOB).
class	ifdxi The IFDXI D-type flip-flop is contained in an input/output block (IOB).
class	ildx_1 ILDX_1 is a transparent data latch, which can be used to hold transient data entering a chip.
class	ildxi_1 ILDXI_1 is a transparent data latch, which can hold transient data entering a chip.
class	inv_g The INV_G is a generic-width inverter cell.
class	iobuf IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_agp IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_ctt IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_f_12 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_f_16 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_f_2 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_f_24 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_f_4 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_f_6 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_f_8 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_gtl IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_gtlp IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_hstl_i IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_hstl_iii IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_hstl_iv IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_lvcmos2 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_pci33_3 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_pci33_5 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_pci66_3 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_s_12 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_s_16 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_s_2 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_s_24 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_s_4 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_s_6 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_s_8 IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_sstl2_i IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_sstl2_ii IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_sstl3_i IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobuf_sstl3_ii IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	ld LD is a transparent data latch.
class	ld_1 LD_1 is a transparent data latch with an inverted gate.
class	ldc LDC is a transparent data latch with asynchronous clear.
class	ldc_1 LDC_1 is a transparent data latch with asynchronous clear and inverted gate.
class	ldce LDCE is a transparent data latch with asynchronous clear and gate enable.
class	ldce_1 LDCE_1 is a transparent data latch with asynchronous clear, gate enable, and inverted gate.
class	ldcp LDCP is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs.
class	ldcp_1 LDCP_1 is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs.
class	ldcpe LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), and gate enable (GE).
class	ldcpe_1 LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), and gate enable (GE).
class	lde LDE is a transparent data latch with data (D) and gate enable (GE) inputs.
class	lde_1 LDE_1 is a transparent data latch with data (D) and gate enable (GE) inputs.
class	ldp LDP is a transparent data latch with asynchronous preset (PRE).
class	ldp_1 LDP_1 is a transparent data latch with asynchronous preset (PRE).
class	ldpe LDPE is a transparent data latch with asynchronous preset and gate enable.
class	ldpe_1 LDPE_1 is a transparent data latch with asynchronous preset, gate enable, and inverted gated.
class	lut1 LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
class	lut1_d LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
class	lut1_l LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
class	lut2 LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
class	lut2_d LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
class	lut2_l LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
class	lut3 LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
class	lut3_d LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
class	lut3_l LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
class	lut4 LUT4 is a 4-bit look-up-table (LUT) with general output (O).
class	lut4_d LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
class	lut4_l LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
class	m2_1 The M2_1 multiplexer chooses one data bit from two sources (D1 or D0) under the control of the select input (S0).
class	m2_1_g The M2_1 multiplexer is a generic-width 2:1 multiplexer.
class	nand2 This class implements and asynchronous 2-input nand gate.
class	nand2_g This class implements and asynchronous 2-input nand gate.
class	nand2b1 This class implements and asynchronous 2-input nand gate.
class	nand2b2 This class implements and asynchronous 2-input nand gate.
class	nand3 This class implements and asynchronous 3-input nand gate.
class	nand3_g This class implements and asynchronous 3-input nand gate.
class	nand3b1 This class implements and asynchronous 3-input nand gate.
class	nand3b2 This class implements and asynchronous 3-input nand gate.
class	nand3b3 This class implements and asynchronous 3-input nand gate.
class	nand4 This class implements and asynchronous 4-input nand gate.
class	nand4_g This class implements and asynchronous 4-input nand gate.
class	nand4b1 This class implements and asynchronous 4-input nand gate.
class	nand4b2 This class implements and asynchronous 4-input nand gate.
class	nand4b3 This class implements and asynchronous 4-input nand gate.
class	nand4b4 This class implements and asynchronous 4-input nand gate.
class	nand5 This class implements and asynchronous 5-input nand gate.
class	nand6 This class implements and asynchronous 6-input nand gate.
class	nand7 This class implements and asynchronous 7-input nand gate.
class	nand8 This class implements and asynchronous 8-input nand gate.
class	nand9 This class implements and asynchronous 9-input nand gate.
class	nandX_g
class	nor2 This class implements and asynchronous 2-input nor gate.
class	nor2_g This class implements and asynchronous 2-input nor gate.
class	nor2b1 This class implements and asynchronous 2-input nor gate.
class	nor2b2 This class implements and asynchronous 2-input nor gate.
class	nor3 This class implements and asynchronous 3-input nor gate.
class	nor3_g This class implements and asynchronous 3-input nor gate.
class	nor3b1 This class implements and asynchronous 3-input nor gate.
class	nor3b2 This class implements and asynchronous 3-input nor gate.
class	nor3b3 This class implements and asynchronous 3-input nor gate.
class	nor4 This class implements and asynchronous 4-input nor gate.
class	nor4_g This class implements and asynchronous 4-input nor gate.
class	nor4b1 This class implements and asynchronous 4-input nor gate.
class	nor4b2 This class implements and asynchronous 4-input nor gate.
class	nor4b3 This class implements and asynchronous 4-input nor gate.
class	nor4b4 This class implements and asynchronous 4-input nor gate.
class	nor5 This class implements and asynchronous 5-input nor gate.
class	nor6 This class implements and asynchronous 6-input nor gate.
class	nor7 This class implements and asynchronous 7-input nor gate.
class	nor8 This class implements and asynchronous 8-input nor gate.
class	nor9 This class implements and asynchronous 9-input nor gate.
class	norX_g
class	obuf_g OBUF is a single output buffer.
class	obuft OBUFT is a single 3-state output buffer with active-low enable.
class	obuft_agp OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_ctt OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_f_12 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_f_16 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_f_2 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_f_24 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_f_4 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_f_6 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_f_8 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_g OBUFT is a single 3-state output buffer with active-low enable.
class	obuft_gtl OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_gtlp OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_hstl_i OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_hstl_iii OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_hstl_iv OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_lvcmos2 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_pci33_3 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_pci33_5 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_pci66_3 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_s_12 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_s_16 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_s_2 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_s_24 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_s_4 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_s_6 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_s_8 OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_sstl2_i OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_sstl2_ii OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_sstl3_i OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuft_sstl3_ii OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	ofd OFD, OFD4, OFD8, and OFD16 are single and multiple output D flip-flops except for XC5200 and XC9000.
class	ofde OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops whose outputs are enabled by tristate buffers.
class	ofdi OFDI is contained in an input/output block (IOB).
class	ofdt OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers.
class	ofdtx OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers.
class	ofdtxi OFDTXI and its output buffer are contained in an input/output block (IOB).
class	ofdx OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops.
class	ofdxi OFDXI is contained in an input/output block (IOB).
class	or2 This class implements and asynchronous 2-input or gate.
class	or2_g This class implements and asynchronous 2-input or gate.
class	or2b1 This class implements and asynchronous 2-input or gate.
class	or2b2 This class implements and asynchronous 2-input or gate.
class	or3 This class implements and asynchronous 3-input or gate.
class	or3_g This class implements and asynchronous 3-input or gate.
class	or3b1 This class implements and asynchronous 3-input or gate.
class	or3b2 This class implements and asynchronous 3-input or gate.
class	or3b3 This class implements and asynchronous 3-input or gate.
class	or4 This class implements and asynchronous 4-input or gate.
class	or4_g This class implements and asynchronous 4-input or gate.
class	or4b1 This class implements and asynchronous 4-input or gate.
class	or4b2 This class implements and asynchronous 4-input or gate.
class	or4b3 This class implements and asynchronous 4-input or gate.
class	or4b4 This class implements and asynchronous 4-input or gate.
class	or5 This class implements and asynchronous 5-input or gate.
class	or6 This class implements and asynchronous 6-input or gate.
class	or7 This class implements and asynchronous 7-input or gate.
class	or8 This class implements and asynchronous 8-input or gate.
class	or9 This class implements and asynchronous 9-input or gate.
class	orX_g
class	pulldown_g The PULLDOWN_G is a generic-width pulldown resistor cell.
class	pullup_g The PULLUP_G is a generic-width pullup resistor cell.
class	ram16x1d RAM16X1D is a 16-word by 1-bit static dual-ported RAM.
class	ram16x1d_1 RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.
class	ram16x1s RAM16X1S is a synchronous 16-word by 1-bit static RAM.
class	ram16x1s_1 RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.
class	ram16x2d RAM16X2D is a 16-word by 2-bit static dual-ported RAM.
class	ram16x2s RAM16X2S is a synchronous 16-word by 2-bit static RAM.
class	ram16x4d RAM16X4D is a 16-word by 4-bit static dual-ported RAM.
class	ram16x4s RAM16X4S is a synchronous 16-word by 4-bit static RAM.
class	ram16x8d RAM16X8D is a 16-word by 8-bit static dual-ported RAM.
class	ram16x8s RAM16X8S is a synchronous 16-word by 8-bit static RAM.
class	ram32x1s RAM32X1S is a synchronous 32-word by 1-bit static RAM.
class	ram32x1s_1 RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability.
class	ram32x1s_ack
class	ram32x2s RAM32X2S is a synchronous 32-word by 2-bit static RAM.
class	ram32x4s RAM32X4S is a synchronous 32-word by 4-bit static RAM.
class	ram32x8s RAM32X8S is a synchronous 32-word by 8-bit static RAM.
(package private) class	byucc.jhdl.Xilinx.Virtex.RAMB4 This class provides the functionality of the RAMB4 Virtex library elements.
class	RAMB4Dual This class provides the functionality of the RAMB4_Sn_Sn Virtex library elements.
class	RAMB4Dual_rb
class	RAMB4Single This class provides the functionality of the RAMB4_Sn Virtex library elements.
class	RAMB4Single_rb
class	rom16x1 ROM16X1 is a 16-word by 1-bit ROM.
class	rom32x1 ROM32X1 is a 32-word by 1-bit ROM.
class	srl16 SRL16 is a shift register look up table (LUT).
class	srl16_1 SRL16_1 is a shift register look up table (LUT).
class	srl16e SRL16E is a shift register look up table (LUT).
class	srl16e_1 SRL16E_1 is a shift register look up table (LUT).
class	tb_BlockRam This class is used by the development team to test the block ram's.
class	TESTVirtexLibrary This class is the self-test controller for the Virtex library.
class	xnor2 This class implements and asynchronous 2-input xnor gate.
class	xnor2_g This class implements and asynchronous 2-input xnor gate.
class	xnor3 This class implements and asynchronous 3-input xnor gate.
class	xnor3_g This class implements and asynchronous 3-input xnor gate.
class	xnor4 This class implements and asynchronous 4-input xnor gate.
class	xnor4_g This class implements and asynchronous 4-input xnor gate.
class	xnor5 This class implements and asynchronous 5-input xnor gate.
class	xnor6 This class implements and asynchronous 6-input xnor gate.
class	xnor7 This class implements and asynchronous 7-input xnor gate.
class	xnor8 This class implements and asynchronous 8-input xnor gate.
class	xnor9 This class implements and asynchronous 9-input xnor gate.
class	xor2 This class implements and asynchronous 2-input xor gate.
class	xor2_g This class implements and asynchronous 2-input xor gate.
class	xor3 This class implements and asynchronous 3-input xor gate.
class	xor3_g This class implements and asynchronous 3-input xor gate.
class	xor4 This class implements and asynchronous 4-input xor gate.
class	xor4_g This class implements and asynchronous 4-input xor gate.
class	xor5 This class implements and asynchronous 5-input xor gate.
class	xor6 This class implements and asynchronous 6-input xor gate.
class	xor7 This class implements and asynchronous 7-input xor gate.
class	xor8 This class implements and asynchronous 8-input xor gate.
class	xor9 This class implements and asynchronous 9-input xor gate.

Uses of Clockable in byucc.jhdl.Xilinx.Virtex.helpers

Classes in byucc.jhdl.Xilinx.Virtex.helpers that implement Clockable

class	adder Class used by the TechMapper.
class	adderSubtractor Class used by the TechMapper.
class	Subtractor Class used by the TechMapper.
class	tb_adder Class used by the development team.

Uses of Clockable in byucc.jhdl.Xilinx.Virtex.Modules

Classes in byucc.jhdl.Xilinx.Virtex.Modules that implement Clockable

class	arrayMult Variable width array multiplier with the option of signed or unsigned multiply and generic pipeline depth.
class	booth General Description
class	delay Generic Delay Line
class	downcnt A generic sized down counter
class	DS2Pconv DS2Pconv.java Created: 3/2002
class	DSMult DSMult.java Created: 1/2002
class	Equals Parameterizable module for creating a bit-wise comparator.
class	KCMMult KCMMult.java Created: 12/2000
class	Mux implements and arbitrary -width and -height mux, optimized to use all of the Virtex internal mux primitives.
class	mux41 Class used by the TechMapper.
class	mux81 Class used by the TechMapper.
class	P2DSconv P2DSconv.java Created: 3/2002
class	ParellelDSMult ParellelDSMult.java Created: 1/2002
class	Priority Outputs only the most significant '1' of the input.
class	PriorityEncoder encodes the input value, prioritizing the bits by MSB has highest priority.
class	ramrom Generic Ram or Rom generator
class	ReversePriorityEncoder encodes the input value, prioritizing the bits by LSB has highest priority.
class	S2Pconv S2Pconv.java Created: 3/2002
class	Shifter Class used by the TechMapper.
class	srl_array Deprecated. use SRLArray
class	SRLArray General Description
class	SRLFifo arbitrary-width, arbitrary depth FIFO based on shift registers (SRL16).
class	upcnt General Description

Uses of Clockable in byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack

Classes in byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack that implement Clockable

class	MultCell MultCell.java Created: 1/2002
class	MultRow MultRow.java Created: 1/2002

Uses of Clockable in byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack

Classes in byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack that implement Clockable

class	KCM_ROM KCM_ROM.java Created: 12/2000
class	KCMRom_Adder KCMRom_Adder.java This is a complete KCMRom_Adder stage.
class	KCMRom_AdderBit KCMRom_AdderBit.java A single bit of a KCM_ROMAddr.
class	tb_VirtexKCMMultiplier tb_VirtexKCMMultiplier.java Created: 12/2000

Uses of Clockable in byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack

Classes in byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack that implement Clockable

class	And_fmap_g
class	EXAMINE_CI_Virtex
class	MultAdd
class	MultAddVirtex
class	multCol
class	MultSub
class	MultSubVirtex

Uses of Clockable in byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack

Classes in byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack that implement Clockable

class	RightShiftReg RightShiftReg.java Created: 3/2002
class	ShiftBit ShiftBit.java Created: 3/2002

Uses of Clockable in byucc.jhdl.Xilinx.Virtex.ramb4_wrapper

Classes in byucc.jhdl.Xilinx.Virtex.ramb4_wrapper that implement Clockable

class	RAMB4_Dual This class provides the functionality of the RAMB4_Sn_Sn Virtex library elements for EDIF parsing only.
class	ramb4_s1 This class provides the functionality of the RAMB4_S1 Virtex library element for EDIF netlisting only.
class	ramb4_s1_s1 This class provides the functionality of the RAMB4_S1_S1 Virtex library element for EDIF netlisting only.
class	ramb4_s1_s16 This class provides the functionality of the RAMB4_S1_S16 Virtex library element for EDIF netlisting only.
class	ramb4_s1_s2 This class provides the functionality of the RAMB4_S1_S2 Virtex library element for EDIF netlisting only.
class	ramb4_s1_s4 This class provides the functionality of the RAMB4_S1_S4 Virtex library element for EDIF netlisting only.
class	ramb4_s1_s8 This class provides the functionality of the RAMB4_S1_S8 Virtex library element for EDIF netlisting only.
class	ramb4_s16 This class provides the functionality of the RAMB4_S16 Virtex library element for EDIF netlisting only.
class	ramb4_s16_s16 This class provides the functionality of the RAMB4_S16_S16 Virtex library element for EDIF netlisting only.
class	ramb4_s2 This class provides the functionality of the RAMB4_S2 Virtex library element for EDIF netlisting only.
class	ramb4_s2_s16 This class provides the functionality of the RAMB4_S2_S16 Virtex library element for EDIF netlisting only.
class	ramb4_s2_s2 This class provides the functionality of the RAMB4_S2_S2 Virtex library element for EDIF netlisting only.
class	ramb4_s2_s4 This class provides the functionality of the RAMB4_S2_S4 Virtex library element for EDIF netlisting only.
class	ramb4_s2_s8 This class provides the functionality of the RAMB4_S2_S8 Virtex library element for EDIF netlisting only.
class	ramb4_s4 This class provides the functionality of the RAMB4_S4 Virtex library element for EDIF netlisting only.
class	ramb4_s4_s16 This class provides the functionality of the RAMB4_S4_S16 Virtex library element for EDIF netlisting only.
class	ramb4_s4_s4 This class provides the functionality of the RAMB4_S4_S4 Virtex library element for EDIF netlisting only.
class	ramb4_s4_s8 This class provides the functionality of the RAMB4_S4_S8 Virtex library element for EDIF netlisting only.
class	ramb4_s8 This class provides the functionality of the RAMB4_S8 Virtex library element for EDIF netlisting only.
class	ramb4_s8_s16 This class provides the functionality of the RAMB4_S8_S16 Virtex library element for EDIF netlisting only.
class	ramb4_s8_s8 This class provides the functionality of the RAMB4_S8_S8 Virtex library element for EDIF netlisting only.
class	RAMB4_Single This class provides the functionality of the RAMB4_Sn Virtex library elements for EDIF parsing only.

Uses of Clockable in byucc.jhdl.Xilinx.Virtex2

Classes in byucc.jhdl.Xilinx.Virtex2 that implement Clockable

class	BlockRamViewParity Deprecated. Use BlockRamView in RamPack instead.
class	bscan_virtex2 The BSCAN_VIRTEX2 symbol is used to create internal boundary scan chains in a Virtex2 or Virtex2- E device.
class	bufgce BUFGCE is a multiplexed global clock buffer with a single gated input.
class	bufgce_1 BUFGCE_1 is a multiplexed global clock buffer with a single gated input.
class	bufgdll Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
class	bufgs Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
class	dcm DCM is a digital clock manager that provides multiple functions.
class	fddrcpe FDDRCPE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1).
class	fddrrse FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1).
class	icap_virtex2
class	ifddrcpe IFDDRCPE is a dual data rate (DDR) input D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR).
class	ifddrrse FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1).
class	iobuf_sstl2_ii_dci IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
class	iobufds
class	mult18x18s MULT18X18S is a signed 18-bit by 18-bit multiplier with output registered.
class	obuft_sstl2_i_dci OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
class	obuftds OBUFTDS is a single 3-state, differential signaling output buffer with active Low enable and a selectIO interface.
class	ofddrcpe OFDDRCPE is a dual data rate (DDR) output D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR).
class	ofddrrse OFDDRRSE is a dual data rate (DDR) output D flip-flop with synchronous reset (R) and set (S) and clock enable (CE).
class	ofddrtcpe OFDDRTCPE is a dual data rate (DDR) D flip-flop with clock enable (CE) and asynchronous preset and clear whose output is enabled by a 3-state buffer.
class	ofddrtrse OFDDRTRSE is a dual data rate (DDR) D flip-flop with clock enable (CE) and synchronous reset and set whose output is enabled by a 3-state buffer.
class	ram128x1s RAM128X1S is a 128-word by 1-bit static random access memory with synchronous write capability.
class	ram128x1s_1 RAM128X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability.
class	ram32x1d RAM32X1D is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.
class	ram32x1d_1 RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
class	ram64x1d RAM64X1D is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.
class	ram64x1d_1 RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
class	ram64x1s RAM64X1S is a 64-word by 1-bit static random access memory with synchronous write capability.
class	ram64x1s_1 RAM64X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability and a negative-edge clock.
class	ram64x2s RAM64X2S is a 64-word by 2-bit static random access memory with synchronous write capability.
class	RAMB16_S This class provides the functionality of the RAMB16_Sn Virtex2 library elements - The Single-ported BlockRams.
class	RAMB16_S_S This class provides the functionality of the RAMB16_Sn_Sn Virtex2 library elements - The Dual-ported BlockRams.
class	RAMB16DualNoParity Deprecated. Use RAMB16_S_S instead.
class	RAMB16DualParity Deprecated. Use RAMB16_S_S instead.
class	RAMB16DualParityB Deprecated. Use RAMB16_S_S instead.
class	RAMB16SingleNoParity Deprecated. Use RAMB16_S instead.
class	RAMB16SingleParity Deprecated. Use RAMB16_S instead.
class	roc
class	rocbuf
class	rom128x1 ROM128X1 is a 128-word by 1-bit ROM.
class	Rom128x1View This class is for the simulation of block ram's to work correctly.
class	rom256x1 ROM256X1 is a 256-word by 1-bit ROM.
class	Rom256x1View This class is for the simulation of block ram's to work correctly.
class	rom64x1 ROM64X1 is a 64-word by 1-bit ROM.
class	Rom64x1View This class is for the simulation of block ram's to work correctly.
class	srlc16 SRLC16 is a shift register look up table (LUT).
class	srlc16_1 SRLC16_1 is a shift register look up table (LUT).
class	srlc16e SRLC16E is a shift register look up table (LUT) with carry, clock enable, and asynchro-nous clear.
class	srlc16e_1 SRLC16E_1 is a shift register look up table (LUT).
class	startbuf_architecture
class	TESTVirtex2Library This class is the self-test controller for the Virtex2 library.
class	toc
class	tocbuf
class	Virtex2LibrarySelfTester This class is the self-test controller for the Virtex2 library.

Uses of Clockable in byucc.jhdl.Xilinx.Virtex2.Modules

Classes in byucc.jhdl.Xilinx.Virtex2.Modules that implement Clockable

class	EmbeddedMultiplier Constructs an arbitrary-width unsigned multiplier using Virtex2 embedded multipliers.
class	MultiplierBlock Basic block for constructing a parameterizeable multiplier based on the Virtex 2 architecture's 18x18 embedded multipliers.
class	MultiplierBlockSigned Basic block for constructing a parameterizeable multiplier based on the Virtex 2 architecture's 18x18 embedded multipliers.

Uses of Clockable in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint

Classes in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint that implement Clockable

class	FPAddSub General Description
class	FPDivide Floating-point divider.
class	FPMult Floating-point multiplier.

Uses of Clockable in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack

Classes in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack that implement Clockable

class	BarrelShiftL
class	BarrelShiftR
class	FP_ALU
class	FPExponentMatch
class	Maximum
class	Normalize
class	NormalizePE
class	Round
class	ShifterTable
class	TestOverflow

Uses of Clockable in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack

Classes in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack that implement Clockable

class	DelayS Generic Delay Line
class	FPMantissaDivide
class	LookupTableBlockRAM

Uses of Clockable in byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack

Classes in byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack that implement Clockable

class	EXAMINE_CI_Virtex2
class	MultAddVirtex2
class	MultSubVirtex2

Uses of Clockable in byucc.jhdl.Xilinx.Virtex2.RamPack

Classes in byucc.jhdl.Xilinx.Virtex2.RamPack that implement Clockable

class	BlockRamViewL This class is for the simulation of block ram's to work correctly.
class	RAMB16 This class provides the functionality of the RAMB16 Virtex2 library elements.

Uses of Clockable in byucc.jhdl.Xilinx.XC4000

Classes in byucc.jhdl.Xilinx.XC4000 that implement Clockable

class	cy4 This class implements the carry modes for the XC4000 architecture.
class	cy4_mode The cy4_mode block is the Annotation wrapper to indicate the exact carry function being implemented to the back end Xilinx tools.
class	ilffx ILFFX, an optional latch that drives the input flip-flop, allows the very fast capture of input data.
class	ilffxi ILFFXI, an optional latch that drives the input flip-flop, allows the very fast capture of input data.
class	ilflx_1 ILFLX_1, an optional latch that drives the input latch, allows the very fast capture of input data.
class	ilflxi_1 ILFLXI_1, an optional latch that drives the input latch, allows the very fast capture of input data.
class	ram16x1 RAM16X1 is a 16-word by 1-bit static RAM.
class	ram32x1 RAM32X1 is a 32-word by 1-bit static RAM.
class	tb_andX
class	TESTXC4000Library This class is the self-test controller for the XC4000 library.

Uses of Clockable in byucc.jhdl.Xilinx.XC4000.carryLogic

Classes in byucc.jhdl.Xilinx.XC4000.carryLogic that implement Clockable

class	cy4_ADD_F_CI Carrylogic to be used with a half adder (3-input xor gate) in the F LUT
class	cy4_ADD_FG_CI Carrylogic to be used with half adders (3-input xor gates) in the F and G LUTS
class	cy4_ADD_G_CI Carrylogic to be used with a half adder (3-input xor gate) in the G LUT
class	cy4_ADD_G_F1
class	cy4_ADD_G_F3_
class	cy4_ADDSUB_F_CI
class	cy4_ADDSUB_FG_CI
class	cy4_ADDSUB_G_CI
class	cy4_ADDSUB_G_F1
class	cy4_ADDSUB_G_F3_
class	cy4_DEC_F_CI
class	cy4_DEC_FG_0
class	cy4_DEC_FG_CI
class	cy4_DEC_G_0
class	cy4_DEC_G_CI
class	cy4_DEC_G_F1
class	cy4_DEC_G_F3_
class	cy4_EXAMINE_CI
class	cy4_FORCE_0
class	cy4_FORCE_1
class	cy4_FORCE_CI
class	cy4_FORCE_F1
class	cy4_FORCE_F3_
class	cy4_INC_F_CI
class	cy4_INC_FG_1
class	cy4_INC_FG_CI
class	cy4_INC_G_1
class	cy4_INC_G_CI
class	cy4_INC_G_F1
class	cy4_INC_G_F3_
class	cy4_INCDEC_F_CI
class	cy4_INCDEC_FG_1
class	cy4_INCDEC_FG_CI
class	cy4_INCDEC_G_0
class	cy4_INCDEC_G_CI
class	cy4_INCDEC_G_F1
class	cy4_SUB_F_CI
class	cy4_SUB_FG_CI
class	cy4_SUB_G_1
class	cy4_SUB_G_CI
class	cy4_SUB_G_F1
class	cy4_SUB_G_F3_

Uses of Clockable in byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack

Classes in byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack that implement Clockable

class	MultAddXC4000
class	MultSubXC4000

Uses of Clockable in byucc.jhdl.Xilinx.XC9000

Classes in byucc.jhdl.Xilinx.XC9000 that implement Clockable

class	add1 See the Xilinx Libraries Guide for details.
class	adsu1 See the Xilinx Libraries Guide for details.
class	and5_g This class implements and asynchronous 5-input and gate.
class	and6_g This class implements and asynchronous 6-input and gate.
class	and7_g This class implements and asynchronous 7-input and gate.
class	and8_g This class implements and asynchronous 8-input and gate.
class	and9_g This class implements and asynchronous 9-input and gate.
class	bufgsr See the Xilinx Libraries guide for details.
class	fdcp_g Implements an asynchronously settable/clearable register in the XC4000 library.
class	ftcp Asynchronously presettable/clearable toggle flip-flop.
class	nand5_g This class implements and asynchronous 5-input nand gate.
class	nand6_g This class implements and asynchronous 6-input nand gate.
class	nand7_g This class implements and asynchronous 7-input nand gate.
class	nand8_g This class implements and asynchronous 8-input nand gate.
class	nand9_g This class implements and asynchronous 9-input nand gate.
class	nor5_g This class implements and asynchronous 5-input nor gate.
class	nor6_g This class implements and asynchronous 6-input nor gate.
class	nor7_g This class implements and asynchronous 7-input nor gate.
class	nor8_g This class implements and asynchronous 8-input nor gate.
class	nor9_g This class implements and asynchronous 9-input nor gate.
class	or5_g This class implements and asynchronous 5-input or gate.
class	or6_g This class implements and asynchronous 6-input or gate.
class	or7_g This class implements and asynchronous 7-input or gate.
class	or8_g This class implements and asynchronous 8-input or gate.
class	or9_g This class implements and asynchronous 9-input or gate.
class	TESTXC9000Library This class is the self-test controller for the XC9000 library.
class	xnor5_g This class implements and asynchronous 5-input xnor gate.
class	xnor6_g This class implements and asynchronous 6-input xnor gate.
class	xnor7_g This class implements and asynchronous 7-input xnor gate.
class	xnor8_g This class implements and asynchronous 8-input xnor gate.
class	xnor9_g This class implements and asynchronous 9-input xnor gate.
class	xor5_g This class implements and asynchronous 5-input xor gate.
class	xor6_g This class implements and asynchronous 6-input xor gate.
class	xor7_g This class implements and asynchronous 7-input xor gate.
class	xor8_g This class implements and asynchronous 8-input xor gate.
class	xor9_g This class implements and asynchronous 9-input xor gate.