Package byucc.jhdl.DRC.Tester

Class Summary
DesignRuleCheckerTester  
LogicMisplacement This design targets the Digilab XC4000 Spartan architecture.
MultiplePuts This design targets the Digilab XC4000 Spartan architecture.
NoBufg This design violates the rule of not running an explicit clock wire through a bufg
 



Copyright ? 2006 Brigham Young University, Configurable Computing Laboratory. All Rights Reserved.