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| Uses of Cell in byucc.jhdl.apps.Broker |
| Methods in byucc.jhdl.apps.Broker with parameters of type Cell | |
void |
InternalBroker.newSchematicView(Cell c)
|
void |
InternalBroker.newMemoryViewerFrame(Cell c)
|
boolean |
Broker.behavModel(Cell cell,
boolean enable,
boolean force)
turn on or off behavioral model of a cell. |
void |
Broker.newSchematicView(Cell c)
|
void |
Broker.print(Cell cell)
|
void |
Broker.newMemoryViewerFrame(Cell c)
|
| Uses of Cell in byucc.jhdl.apps.dtb |
| Subclasses of Cell in byucc.jhdl.apps.dtb | |
class |
DynamicTestBench
The DynamicTestBench acts as a quick replacement for a full, formal TestBench written by the user. |
| Methods in byucc.jhdl.apps.dtb with parameters of type Cell | |
void |
DynamicTestBench.setSelectedCell(Cell selected)
Sets the currently selected cell to the given value |
| Uses of Cell in byucc.jhdl.apps.dtb.cli |
| Methods in byucc.jhdl.apps.dtb.cli with parameters of type Cell | |
void |
ParamGUI.dtbDesignBuilt(Cell design)
Implementation of the BuildListener interface to find out when the cell is built. |
| Uses of Cell in byucc.jhdl.apps.dtb.listener |
| Methods in byucc.jhdl.apps.dtb.listener with parameters of type Cell | |
void |
BuildListener.dtbDesignBuilt(Cell design)
When the DynamicTestBench builds its child design, it informs registered BuildListeners with this method. |
| Uses of Cell in byucc.jhdl.apps.Jab |
| Methods in byucc.jhdl.apps.Jab that return Cell | |
Cell |
BrowserCore.getSelectedCell()
Deprecated. |
Cell |
BrowserCore.getSelectedCell(boolean display_dialogs)
Deprecated. |
| Methods in byucc.jhdl.apps.Jab with parameters of type Cell | |
int |
BrowserHardwareInterface.getCellHardwareValue(Cell cell)
|
long |
BrowserHardwareInterface.getLongCellHardwareValue(Cell cell)
|
boolean |
BrowserCore.addCircuitView(Cell cCell)
Deprecated. |
void |
BrowserCore.removeCircuitView(Cell c)
Deprecated. |
| Constructors in byucc.jhdl.apps.Jab with parameters of type Cell | |
CellInfo(Cell currCell,
BrowserCore bCore,
boolean getChildWires)
|
|
| Uses of Cell in byucc.jhdl.apps.Stimulator |
| Subclasses of Cell in byucc.jhdl.apps.Stimulator | |
class |
Stimulator
An interactive stimulator. |
class |
TriStateStimulator
Extends the Stimulator to perform puts on tri-state buses. |
| Uses of Cell in byucc.jhdl.apps.Tbone |
| Subclasses of Cell in byucc.jhdl.apps.Tbone | |
class |
Tbone
Tbone is a generic test bench used to simulate a circuit. |
| Uses of Cell in byucc.jhdl.apps.Viewers |
| Methods in byucc.jhdl.apps.Viewers that return Cell | |
Cell |
ViewInterface.getSelectedCell()
|
| Methods in byucc.jhdl.apps.Viewers with parameters of type Cell | |
boolean |
ViewManager.addCircuitView(Cell cCell,
int locx,
int locy,
int sizex,
int sizey)
|
boolean |
ViewManager.addCircuitView(Cell cCell)
addCircuitView, create a new circuit view and register it |
void |
ViewManager.removeCircuitView(Cell cell)
removeCircuitView, unregister circuit view |
boolean |
ViewManager.addLayoutView(Cell c)
|
void |
ViewManager.removeLayoutView(Cell c)
|
| Uses of Cell in byucc.jhdl.apps.Viewers.BrowserMainFrame |
| Methods in byucc.jhdl.apps.Viewers.BrowserMainFrame that return Cell | |
Cell |
BrowserMainFrame.getSelectedCell(boolean debug)
|
Cell |
BrowserTreeNode.getCell()
|
| Methods in byucc.jhdl.apps.Viewers.BrowserMainFrame with parameters of type Cell | |
void |
BrowserTree.loadClass(Cell rNode)
|
void |
BrowserTree.addSelectedCell(Cell cell)
|
void |
BrowserTree.removeSelectedCell(Cell cell)
|
| Constructors in byucc.jhdl.apps.Viewers.BrowserMainFrame with parameters of type Cell | |
BrowserTreeNode(BrowserTree btParent,
BrowserTreeNode parent,
Cell cell)
|
|
| Uses of Cell in byucc.jhdl.apps.Viewers.cvt |
| Subclasses of Cell in byucc.jhdl.apps.Viewers.cvt | |
class |
DesktopTest
|
| Methods in byucc.jhdl.apps.Viewers.cvt that return Cell | |
Cell |
cvtPanel.rootCell()
|
Cell |
cvtPanel.getRootCell()
|
Cell |
cvtFrame.rootCell()
|
| Methods in byucc.jhdl.apps.Viewers.cvt with parameters of type Cell | |
javax.swing.JInternalFrame |
cvtDesktop.addTreeViewToDesktop(Cell cell)
|
void |
cvtDesktop.newCell(Cell newDesign)
Used, especially by DynamicTestBench, to target another cell. |
protected javax.swing.JPanel |
cvtDesktop.createSidePanel(Cell tree_view_topcell)
Create a collapsable side panel for misc. |
void |
cvtPanel.newCell(Cell newDesign)
Used, especially by DynamicTestBench, to target another cell. |
void |
cvtInternalFrame.newCell(Cell newDesign)
Used, especially by DynamicTestBench, to target another cell. |
void |
cvtFrame.newCell(Cell newDesign)
Used, especially by DynamicTestBench, to target another cell. |
| Constructors in byucc.jhdl.apps.Viewers.cvt with parameters of type Cell | |
cvtDesktop(Cell c)
|
|
cvtDesktop(Cell c,
CLInterpreter interpreter,
InternalBroker userBroker)
|
|
cvtPanel(Cell c)
|
|
cvtPanel(Cell c,
CLInterpreter interpreter)
|
|
cvtPanel(Cell c,
Broker userBroker)
|
|
cvtPanel(Cell c,
CLInterpreter interpreter,
Broker userBroker)
|
|
cvtPanel(Cell c,
CLInterpreter interpreter,
Broker userBroker,
cvtFrame cf)
|
|
cvtInternalFrame(Cell c)
|
|
cvtInternalFrame(Cell c,
javax.swing.JDesktopPane desktop)
|
|
cvtInternalFrame(Cell c,
CLInterpreter interpreter,
javax.swing.JDesktopPane desktop)
|
|
cvtInternalFrame(Cell c,
Broker userBroker,
javax.swing.JDesktopPane desktop)
|
|
cvtInternalFrame(Cell c,
CLInterpreter interpreter,
Broker userBroker,
javax.swing.JDesktopPane desktop)
|
|
cvtFrame(Cell c)
|
|
cvtFrame(Cell c,
CLInterpreter interpreter)
|
|
cvtFrame(Cell c,
Broker userBroker)
|
|
cvtFrame(Cell c,
CLInterpreter interpreter,
Broker userBroker)
|
|
| Uses of Cell in byucc.jhdl.apps.Viewers.Event |
| Methods in byucc.jhdl.apps.Viewers.Event that return Cell | |
abstract Cell |
JHDLAbstractHostPanel.getRootCell()
Accessor method. |
Cell |
JHDLHostWidgetInterface.getRootCell()
Accessor method. |
Cell |
JHDLMouseEvent.getCell()
|
| Uses of Cell in byucc.jhdl.apps.Viewers.FloorPlan |
| Methods in byucc.jhdl.apps.Viewers.FloorPlan that return Cell | |
Cell |
FloorPlanRecord.getRepCell()
|
Cell |
LayoutView.getSelectedCell()
|
| Methods in byucc.jhdl.apps.Viewers.FloorPlan with parameters of type Cell | |
void |
FloorPlanRecord.setRepCell(Cell c)
|
java.lang.String |
FloorPlanModule.getCellName(Cell c)
|
void |
FloorPlanModule.init(javax.swing.JPanel frame,
Cell top)
|
FloorPlanRecord |
LayoutView.getFloorPlanRecord(Cell cell)
|
void |
LayoutViewListener.removeLayoutView(Cell c)
|
boolean |
LayoutViewListener.addLayoutView(Cell c)
|
| Constructors in byucc.jhdl.apps.Viewers.FloorPlan with parameters of type Cell | |
LayoutView(ViewManager listener,
Cell myCell)
|
|
LayoutView(ViewManager listener,
Cell myCell,
java.lang.String title)
|
|
| Uses of Cell in byucc.jhdl.apps.Viewers.JL |
| Constructors in byucc.jhdl.apps.Viewers.JL with parameters of type Cell | |
CLIJL(Cell c)
Deprecated. Please use byucc.jhdl.apps.Viewers.cvtFrame instead |
|
CLIJL(Cell c,
CLInterpreter interpreter)
Deprecated. Please use byucc.jhdl.apps.Viewers.cvtFrame instead |
|
| Uses of Cell in byucc.jhdl.apps.Viewers.NewTreeBrowser |
| Methods in byucc.jhdl.apps.Viewers.NewTreeBrowser that return Cell | |
Cell |
TreeBrowserNode.getCell()
Casts the encapsulated object as a Cell. |
Cell |
TreeBrowserPanel.getSelectedCell()
|
| Constructors in byucc.jhdl.apps.Viewers.NewTreeBrowser with parameters of type Cell | |
TreeBrowserPanel(Cell rNode)
Deprecated. |
|
| Uses of Cell in byucc.jhdl.apps.Viewers.Schematic |
| Fields in byucc.jhdl.apps.Viewers.Schematic declared as Cell | |
protected Cell |
SchematicCanvas.circuit
Pointer to the Cell that is currently being drawn. |
protected Cell |
SchematicNode.schematicCell
The jhdl Cell associated with this Node. |
| Methods in byucc.jhdl.apps.Viewers.Schematic that return Cell | |
Cell |
SchematicCanvas.getCell()
This method provides access to the Cell for which this SchematicCanvas displays. |
Cell |
SchematicActionEvent.getCell()
Deprecated. |
Cell |
SchematicNode.getCell()
|
| Methods in byucc.jhdl.apps.Viewers.Schematic with parameters of type Cell | |
void |
CircuitViewListener.removeCircuitView(Cell c)
|
boolean |
CircuitViewListener.addCircuitView(Cell c)
|
void |
SmartSchematicFrame.newSchematicPane(Cell c)
|
void |
DefaultSchematicActionListener.cellDoubleClicked(Cell c)
|
void |
DefaultSchematicActionListener.cellSingleClicked(Cell c)
|
void |
SchematicCanvas.constructAndPlace(Cell p,
Netlist nl)
|
int |
SchematicCanvas.placeInputs(SchematicNode currNode,
Cell p,
int currLevel)
|
boolean |
SchematicCanvas.isInPort(Cell c,
java.lang.String pName)
|
boolean |
SchematicCanvas.isOutPort(Cell c,
java.lang.String pName)
|
void |
SchematicCanvas.setCellSelected(Cell cell,
boolean b)
|
protected SchematicNode |
SchematicCanvas.getSchematicNode(Cell cell)
|
static SchematicNode |
SchematicNode.getNode(Cell p,
SchematicCanvas parent)
|
static SchematicNode |
SchematicNode.getNode(Cell p,
java.lang.String portName,
SchematicCanvas parent)
|
void |
CircuitView.doubleClickCell(Cell p)
Callback function that is called when the user double clicks on a cell in the SchematicCanvas. |
void |
CircuitView.setCellSelected(Cell cell,
boolean b)
|
| Constructors in byucc.jhdl.apps.Viewers.Schematic with parameters of type Cell | |
OutNode(java.lang.String portName,
Cell p,
SchematicCanvas parent)
|
|
XorNode(Cell p,
SchematicCanvas parent,
boolean invOut,
int invIn)
|
|
AndNode(Cell p,
SchematicCanvas parent,
boolean invOut,
int invIn)
|
|
SchematicScrollPane(Cell p)
Deprecated. |
|
SchematicScrollPane(Cell p,
JHDLHostWidgetInterface hwi)
Constructs a new SchematicScrollPane--New constructor, so that this panel can pass the JHDLHostWidgetInterface to its parent to get the call chain ready to be initialized. |
|
OrNode(Cell p,
SchematicCanvas parent,
boolean invOut,
int invIn)
|
|
SmartSchematicFrame(Cell c)
Deprecated. |
|
SmartSchematicFrame(Cell c,
JHDLHostWidgetInterface hwi)
Constructs a new SmartSchematicFrame--New constructor, so that this panel can pass the JHDLHostWidgetInterface to its parent to get the call chain ready to be initialized. |
|
InOutNode(java.lang.String portName,
Cell p,
SchematicCanvas parent)
|
|
InvNode(Cell p,
SchematicCanvas parent)
|
|
SchematicViewerFrame(Cell c)
Deprecated. |
|
SchematicViewerFrame(Cell c,
JHDLHostWidgetInterface hwi)
Constructs a new SchematicViewerFrame--New constructor, so that this panel can pass the JHDLHostWidgetInterface to its parent to get the call chain ready to be initialized. |
|
SchematicViewerInternalFrame(Cell c)
Deprecated. |
|
SchematicViewerInternalFrame(Cell c,
JHDLHostWidgetInterface hwi)
Constructs a new SchematicViewerInternalFrame--New constructor, so that this panel can pass the JHDLHostWidgetInterface to its parent to get the call chain ready to be initialized. |
|
InNode(java.lang.String portName,
Cell p,
SchematicCanvas parent)
|
|
ConstNode(Cell p,
SchematicCanvas parent)
|
|
GenericNode(Cell p,
SchematicCanvas parent)
|
|
IncNode(Cell p,
SchematicCanvas parent)
|
|
SchematicViewerPanel(Cell c)
Deprecated. |
|
SchematicViewerPanel(Cell c,
JHDLHostWidgetInterface hwi)
Constructs a new SchematicViewerPanel--New constructor, so that this panel can pass the JHDLHostWidgetInterface to its parent to get the call chain ready to be initialized. |
|
SchematicCanvas(Cell p,
javax.swing.JViewport vp)
Deprecated. |
|
SchematicCanvas(Cell p,
javax.swing.JViewport vp,
JHDLHostWidgetInterface hwi)
Constructs a new SchematicCanvas--New constructor, so that this panel can pass the JHDLHostWidgetInterface to its parent to get the call chain ready to be initialized. |
|
UDNImplementation(Cell p,
SchematicCanvas parent)
|
|
VCCNode(Cell p,
SchematicCanvas parent)
|
|
SchematicActionEvent(java.lang.Object source,
int id,
java.lang.String command,
Cell c)
Deprecated. |
|
BufNode(Cell p,
SchematicCanvas parent)
|
|
GNDNode(Cell p,
SchematicCanvas parent)
|
|
MuxNode(Cell p,
SchematicCanvas parent)
|
|
AddSubNode(Cell p,
SchematicCanvas parent)
|
|
SchematicNode(Cell p,
SchematicCanvas parent)
Default Constructor. |
|
ShiftNode(Cell p,
SchematicCanvas parent,
char shdir,
int shamt)
|
|
CircuitView(ViewManager vMan,
Cell myCell,
int locx,
int locy,
int sizex,
int sizey)
Constructors |
|
CircuitView(ViewManager vMan,
Cell myCell,
int locx,
int locy,
int sizex,
int sizey,
Wire selWire)
|
|
CircuitView(ViewManager vMan,
CLInterpreter interp,
Cell myCell,
int locx,
int locy,
int sizex,
int sizey)
|
|
CircuitView(ViewManager vMan,
Cell myCell)
|
|
CircuitView(ViewManager vMan,
CLInterpreter interp,
Cell myCell)
|
|
CircuitView(ViewManager vMan,
Cell myCell,
java.lang.String title)
|
|
CircuitView(ViewManager vMan,
CLInterpreter interp,
Cell myCell,
java.lang.String title)
|
|
RegNode(Cell p,
SchematicCanvas parent,
int invertedClock)
|
|
AddNode(Cell p,
SchematicCanvas parent)
|
|
| Uses of Cell in byucc.jhdl.apps.Viewers.TreeBrowser |
| Methods in byucc.jhdl.apps.Viewers.TreeBrowser that return Cell | |
Cell |
TreeBrowserPanel.getSelectedCell()
|
Cell |
TreeBrowserActionEvent.getCell()
Deprecated. |
| Methods in byucc.jhdl.apps.Viewers.TreeBrowser with parameters of type Cell | |
void |
TreeBrowserPanel.loadClass(Cell rNode)
Sets the given Cell as the root node of the tree to view |
| Constructors in byucc.jhdl.apps.Viewers.TreeBrowser with parameters of type Cell | |
TreeBrowserPanel(Cell rNode,
JHDLHostWidgetInterface hwi)
Constructs a new TreeBrowserPanel--New constructor, so that this panel can pass the JHDLHostWidgetInterface to its parent to get the call chain ready to be initialized. |
|
TreeBrowserPanel(Cell rNode)
Deprecated. |
|
TreeBrowserActionEvent(java.lang.Object source,
int id,
java.lang.String command,
Cell c)
Deprecated. |
|
TreeBrowserFrame(Cell cell)
Deprecated. |
|
TreeBrowserFrame(Cell cell,
JHDLHostWidgetInterface hwi)
New constructor added, so that the JHDLHostWidgetInterface can be passed in and sent to the TreeBrowserPanel. |
|
| Uses of Cell in byucc.jhdl.apps.Viewers.WiresTable |
| Methods in byucc.jhdl.apps.Viewers.WiresTable with parameters of type Cell | |
void |
WiresTablePanel.rebuildTable(Cell c)
|
| Constructors in byucc.jhdl.apps.Viewers.WiresTable with parameters of type Cell | |
WiresTableFrame(Cell cell)
Deprecated. |
|
WiresTableFrame(Cell cell,
JHDLHostWidgetInterface hwi)
|
|
WiresTablePanel(Cell ci)
Deprecated. |
|
WiresTablePanel(Cell c,
JHDLHostWidgetInterface hwi)
Constructs a new WiresTablePanel--New constructor, so that this panel can pass the JHDLHostWidgetInterface to its parent to get the call chain ready to be initialized. |
|
WiresTableInternalFrame(Cell cell)
Deprecated. |
|
WiresTableInternalFrame(Cell cell,
JHDLHostWidgetInterface hwi)
|
|
| Uses of Cell in byucc.jhdl.base |
| Subclasses of Cell in byucc.jhdl.base | |
class |
Annotation
This class provides a Cell class that cannot be simulated. |
class |
CL
This can be used as a super-class for a cell that is purely combinational. |
class |
ClockDriver
Class used to create clock drivers. |
class |
DefaultSubCell
|
class |
DynamicClockDriver
Class used to create clock drivers. |
class |
HWProcess
This file contains the code that comprises most of the javaHDL simulation kernel. |
class |
PullUpDown
|
class |
Structural
If the node only contains instantiations of other kinds of nodes, this is the container class to use. |
class |
Synchronous
Base class for defining a synchronous circuit element. |
class |
temp_cell
Used by BV for testing |
class |
VisibleAnnotation
This class provides a Cell class that cannot be simulated It can only be used to annotate the circuit and was provided primarily for use by the techmapper. |
| Fields in byucc.jhdl.base declared as Cell | |
protected Cell |
Connection.cell
The cell that is connected to |
| Methods in byucc.jhdl.base that return Cell | |
Cell |
Cell.replaceProperty(java.lang.String name,
java.lang.String value)
Used to replace a string property of a Cell. |
Cell |
Cell.replaceProperty(Property p)
Used to replace a property of a Cell. |
Cell |
Cell.addProperty(java.lang.String name,
java.lang.Object value)
Used to add an arbitrary property to a Cell. |
Cell |
Cell.addProperty(java.lang.String name,
java.lang.Object value,
boolean isVisible)
|
Cell |
Cell.addProperty(java.lang.String name,
java.lang.String value)
Used to add a string property to a Cell. |
Cell |
Cell.addProperty(Property p)
Used to add a Property object to the Cell. |
Cell |
Cell.pushHierarchyNoImplicitPorts(CellInterface[] cell_interface,
java.lang.String cellname,
boolean unique_structure)
This call begins the creation of a subcell with no implicit ports inherited from any parent cell. |
Cell |
Cell.pushHierarchyNoImplicitPorts(CellInterface[] cell_interface,
java.lang.String cellname,
boolean unique_structure,
java.lang.String instance_name)
This call begins the creation of a subcell with no implicit ports inherited from any parent cell. |
Cell |
Cell.pushHierarchy(CellInterface[] cell_interface,
java.lang.String cellname)
This allows multiple levels of hierarchy within one class file |
Cell |
Cell.pushHierarchy(CellInterface[] cell_interface,
java.lang.String cellname,
boolean unique_structure)
This allows multiple levels of hierarchy within one class file |
Cell |
Cell.pushHierarchy(CellInterface[] cell_interface,
java.lang.String cellname,
java.lang.String instance_name)
This allows multiple levels of hierarchy within one class file |
Cell |
Cell.pushHierarchy(CellInterface[] cell_interface,
java.lang.String cellname,
boolean unique_structure,
java.lang.String instance_name)
This allows multiple levels of hierarchy within one class file, works in tandem with popHierarchy(). |
Cell |
HWSystem.getTestBench()
A HWSystem should have only one child and it should be a test bench, based on constructors. |
static Cell |
HelperLibrary.getTopCell(Wire w)
|
Cell |
NodeList.getCell()
Returns the node pointed to by the current pointer as a Cell, if possible. |
Cell |
Wire.getParentCell()
Simple accessor to get the parent of the wire, without casting |
Cell |
Wire.getSinkCell()
|
Cell |
Wire.getSourceCell()
|
Cell |
Node.getParentCell()
Returns the parent of this Node, cast as a Cell if possible |
Cell |
CellList.getCell()
Returns the cell at the current position. |
Cell |
CellList.getSingleCell()
Returns the first element in the list, or null if none |
Cell |
Connection.getCell()
Returns the connected cell |
| Methods in byucc.jhdl.base with parameters of type Cell | |
long |
HWSystem.printTransitionCounts(java.io.OutputStream os,
Cell c)
This will print out all of the transition counts for every wire in the target Cell and it's children. |
static boolean |
HelperLibrary.isInnerWire(Wire wire,
Cell cell)
Determines if this is an inner wire in the context of the passed in cell. |
static java.util.HashMap |
HelperLibrary.createVPtoWiresMapping(Cell top)
Creates a HashMap object whose Keys are ValuePropagater Objects, and whose Values are ArrayList Objects of Wires. |
void |
Wire.put(Cell source,
int val)
Values are placed on a wire using this method. |
void |
Wire.putB(Cell source,
boolean val)
Boolean version of put. |
void |
Wire.putBV(Cell source,
BV val)
Values are placed on a wire using this method. |
void |
Wire.putL(Cell source,
long val)
Long version of put. |
void |
Wire.putA(Cell source,
int[] val)
int[] version of put. |
void |
Wire.putTriState(Cell source,
int val)
Values are placed on a wire using this method. |
void |
Wire.putTriStateBV(Cell source,
BV val)
BV version of putTriState. |
void |
Wire.putTriStateL(Cell source,
long val)
Long version of putTriState. |
void |
Wire.putTriStateA(Cell source,
int[] val)
int[] version of putTriState. |
int |
Wire.get(Cell sink)
Values are read from wires using this method. |
int |
Wire.getZ(Cell sink)
Mask of floating values are from wires using this method. |
int |
Wire.getX(Cell sink)
Mask of multiple puts are from wires using this method. |
boolean |
Wire.getB(Cell sink)
Boolean version of get. |
boolean |
Wire.getZB(Cell sink)
Boolean version of getZ. |
boolean |
Wire.getXB(Cell sink)
Boolean version of getX. |
BV |
Wire.getBV(Cell sink)
BV version of get. |
BV |
Wire.getZBV(Cell sink)
BV version of getZ. |
BV |
Wire.getXBV(Cell sink)
BV version of getX. |
BV |
Wire.getBV(Cell sink,
BV out)
BV version of get. |
BV |
Wire.getZBV(Cell sink,
BV out)
BV version of getZ. |
BV |
Wire.getXBV(Cell sink,
BV out)
BV version of getX. |
long |
Wire.getL(Cell sink)
Long version of get. |
long |
Wire.getZL(Cell sink)
Long version of getZ. |
long |
Wire.getXL(Cell sink)
Long version of getX. |
int[] |
Wire.getA(Cell sink)
int[] version of get. |
int[] |
Wire.getZA(Cell sink)
|
int[] |
Wire.getXA(Cell sink)
|
protected boolean |
Wire.validSourceCell(Cell source)
Checks to see if source is allowed to put values onto this wire. |
protected boolean |
Wire.validSinkCell(Cell sink)
Checks to see if sink is allowed to get values from this wire. |
Wire |
Wire.createAlias(Cell parent,
java.lang.String name)
This creates an alias of an existing wire. |
Wire |
Wire.createAlias(Cell parent)
This creates an alias of an existing wire. |
Wire |
Wire.range(Cell parent,
int upper_bound,
int lower_bound,
java.lang.String name)
This returns a new wire that contains only the prescribed range in BITS. |
Wire |
Wire.range(Cell parent,
int upper_bound,
int lower_bound)
This returns a new wire that contains only the prescribed range. |
protected Wire |
Wire.newWire(Cell parent,
java.lang.String name)
This creates an alias of this wire, using the clone mechanism. |
Wire |
Wire.getWire(Cell parent,
int i)
This returns the ith atomic wire. |
Wire |
Wire.getWire(Cell parent,
int i,
java.lang.String name)
This returns the ith atomic wire. |
Wire |
Wire.gw(Cell parent,
int i)
Shorthand for Wire.getWire(Cell, int). |
Wire |
Wire.gw(Cell parent,
int i,
java.lang.String name)
Shorthand for Wire.getWire(Cell, int, String). |
Wire |
Wire.getAliasForScope(Cell parent)
Returns an alias of the wire with the given scope. |
void |
Wire.addProperty(Cell parent,
java.lang.String name,
java.lang.String value)
Used to add a string property to a Wire, within the scope of the given Cell. |
void |
Wire.addProperty(Cell parent,
java.lang.String name,
java.lang.Object value,
boolean isVisible)
|
Property |
Wire.setProperty(Cell parent,
java.lang.String name,
java.lang.Object value,
boolean isVisible)
|
void |
Wire.addProperty(Cell parent,
Property p)
Used to add a Property object to a Wire, within the scope of the given Cell. |
PropertyList |
Wire.getProperties(Cell parent)
Used to get the property list from the wire from the scope of the given cell. |
Property |
Wire.getProperty(Cell parent,
java.lang.String name)
|
java.lang.Object |
Wire.getPropertyValue(Cell parent,
java.lang.String name)
|
boolean |
Wire.hasProperties(Cell parent)
Used to determine if this wire has properties, at the scope of the given cell. |
void |
Wire.replaceProperty(Cell parent,
java.lang.String name,
java.lang.String value)
Used to replace a string property of a Wire. |
void |
Wire.replaceProperty(Cell parent,
Property p)
Used to replace a property of a Wire. |
boolean |
Wire.removeProperty(Cell parent,
java.lang.String name)
Used to remove a named property of a Wire at the scope of the given cell. |
void |
Wire.addProperties(Cell parent,
PropertyList plist)
Used to add a list of properties to the Wire, within the scope of the given cell. |
void |
Wire.addProperties(Cell parent,
PropertyList plist,
boolean warn_duplicates)
Used to add a list of properties to the Wire, withing the scope of the given cell. |
java.lang.String |
PlacementInfo.getTransformation(Cell c)
Return the transformation |
void |
CellList.insert(Cell c)
Controls what can be put in the list |
| Constructors in byucc.jhdl.base with parameters of type Cell | |
Netlist(Cell parent)
Simple constructor only needs the parent cell. |
|
Wire(Cell parent,
java.lang.String name)
This creates a new Wire that is empty so that its contents can be filled in later. |
|
Wire(Cell parent,
int num_of_wires,
int wire_width,
java.lang.String name)
Deprecated. Use Wire(parent, num_of_wires, name). |
|
Wire(Cell parent,
int num_of_wires,
java.lang.String name)
Base constructor. |
|
Wire(Cell parent,
WireList wl,
java.lang.String name)
Deprecated. Use Wire.Wire(Cell, Wire[], String), which has most significant bits in slot 0 |
|
Wire(Cell parent,
Wire[] wa,
java.lang.String name)
This builds a wire from an array of wires that is passed in. |
|
Connection(Cell cell,
int port_name_index,
boolean is_atomic_port)
Construct a connection |
|
| Uses of Cell in byucc.jhdl.contrib.modgen |
| Subclasses of Cell in byucc.jhdl.contrib.modgen | |
class |
accum
Accumulator that allows a generic sized input and output. |
class |
Add
Deprecated. Use Logic add call instead (Add was deprecated since it is XC4000 specific) |
class |
Adsu
Deprecated. Use Logic addsub call instead (AddSub was deprecated since it is XC4000 specific). |
class |
Cordic
Generic width CORDIC unit for Xilinx XC4000. |
class |
Cordicl
Generic width linear CORDIC unit for Xilinx XC4000. |
class |
CordicRP
Generic width CORDIC unit for Xilinx Virtex. |
class |
eq
General Description |
class |
gt
Generic greater-than comparator. |
class |
IntDivide
Variable width integer divider with the option of signed or unsigned multiply and generic pipeline depth. |
class |
LFSR4
4 bit linear feedback shift register. |
class |
lt
Generic less-than comparator. |
class |
rounder
|
class |
StageRP
|
class |
Sub
Deprecated. Use Logic sub call instead (Sub was deprecated since it is XC4000 specific). |
| Uses of Cell in byucc.jhdl.contrib.modgen.AddSubPack |
| Subclasses of Cell in byucc.jhdl.contrib.modgen.AddSubPack | |
class |
ADD_F_CI
|
class |
ADD_FG_CI
|
class |
ADD_G_F1
|
class |
ADDSUB_F_CI
|
class |
ADDSUB_FG_CI
|
class |
ADDSUB_G_F1
|
class |
ADDSUB_G_F3_
|
class |
SUB_F_CI
|
class |
SUB_FG_CI
|
class |
SUB_G_1
|
class |
SUB_G_F1
|
| Uses of Cell in byucc.jhdl.contrib.modgen.CordicPack |
| Subclasses of Cell in byucc.jhdl.contrib.modgen.CordicPack | |
class |
Col_reg
|
class |
Cordic_ctrl
|
class |
Cordicl_ctrl
|
class |
End_rot
|
class |
Init_rot
|
class |
Pipe_sigs
|
class |
Stage
|
class |
Stagel
|
class |
Tc_mux
|
class |
Z_Mux
|
| Uses of Cell in byucc.jhdl.contrib.modgen.IntDividePack |
| Subclasses of Cell in byucc.jhdl.contrib.modgen.IntDividePack | |
class |
AddPass
|
class |
AddPassGeneric
|
class |
AddPassVirtex
|
class |
AddPassXC4000
|
class |
tbcomp_IntDivide
|
| Uses of Cell in byucc.jhdl.contrib.modgen.MultArrayPack |
| Subclasses of Cell in byucc.jhdl.contrib.modgen.MultArrayPack | |
class |
MultAddGeneric
|
class |
MultSubGeneric
|
| Methods in byucc.jhdl.contrib.modgen.MultArrayPack that return Cell | |
static Cell |
And_fmap_g.and_map(Node parent,
Wire a,
Wire b,
Wire out)
|
| Uses of Cell in byucc.jhdl.CSRC |
| Subclasses of Cell in byucc.jhdl.CSRC | |
class |
addsubX
Generic width adder-subtractor. |
class |
addX
Generic width adder. |
class |
and2_dp
This class implements and asynchronous 2-input and gate. |
class |
and2_dp_g
This class implements and asynchronous 2-input and gate. |
class |
and3_dp
This class implements and asynchronous 3-input and gate. |
class |
and3_dp_g
This class implements and asynchronous 3-input and gate. |
class |
and4_dp
This class implements and asynchronous 4-input and gate. |
class |
and5_dp
This class implements and asynchronous 5-input and gate. |
class |
and6_dp
This class implements and asynchronous 6-input and gate. |
class |
and7_dp
This class implements and asynchronous 7-input and gate. |
class |
and8_dp
This class implements and asynchronous 8-input and gate. |
class |
and9_dp
This class implements and asynchronous 9-input and gate. |
class |
andX
This class implements an AND gate with arbitrary number of inputs. |
class |
buf
Buffer. |
class |
bufX
This cell buffers each input wire. |
class |
CSRCCL
|
class |
CSRCClockDriver
|
class |
CSRCFD
|
class |
dff_dp
The dff_dp is a simple D-flipflop. |
class |
dff_dpX
This instantiates a generic width dff_dp. |
class |
dffe_dp
The dffe_dp is a D-flipflop with a clock enable. |
class |
dffe_dpX
This instantiates a generic width dffe_dp. |
class |
dffr_dp
The dffr_dp is a D-flipflop with a synchronous reset. |
class |
dffr_dpX
This instantiates a generic width dffs_dp. |
class |
dffre_dp
The dffre_dp is a D-flipflop with a synchronous reset and a clock enable. |
class |
dffre_dpX
This instantiates a generic width dffre_dp. |
class |
dffs_dp
The dffs_dp is a D-flipflop with a synchronous set. |
class |
dffs_dpX
This instantiates a generic width dffr_dp. |
class |
dffse_dp
The dffse_dp is a D-flipflop with a synchronous set and a clock enable. |
class |
dffse_dpX
This instantiates a generic width dffse_dp. |
class |
DL_ONE
Returns a logic one. |
class |
DL_ZERO
Returns a logic zero. |
class |
gndX
This instantiates a generic width vcc. |
class |
IB
This is an input buffer. |
class |
IBX
Generic width output buffer. |
class |
maj3
3-input majority gate. |
class |
mux_dpX
Generic width 2-1 Mux. |
class |
mux3_dp
2-1 Mux. |
class |
nand2_dp
This class implements and asynchronous 2-input nand gate. |
class |
nand2_dp_g
This class implements and asynchronous 2-input nand gate. |
class |
nand3_dp
This class implements and asynchronous 3-input nand gate. |
class |
nand3_dp_g
This class implements and asynchronous 3-input nand gate. |
class |
nand4_dp
This class implements and asynchronous 4-input nand gate. |
class |
nand5_dp
This class implements and asynchronous 5-input nand gate. |
class |
nand6_dp
This class implements and asynchronous 6-input nand gate. |
class |
nand7_dp
This class implements and asynchronous 7-input nand gate. |
class |
nand8_dp
This class implements and asynchronous 8-input nand gate. |
class |
nand9_dp
This class implements and asynchronous 9-input nand gate. |
class |
nandX
This class implements an NAND gate with arbitrary number of inputs. |
class |
nor2_dp
This class implements and asynchronous 2-input nor gate. |
class |
nor2_dp_g
This class implements and asynchronous 2-input nor gate. |
class |
nor3_dp
This class implements and asynchronous 3-input nor gate. |
class |
nor3_dp_g
This class implements and asynchronous 3-input nor gate. |
class |
nor4_dp
This class implements and asynchronous 4-input nor gate. |
class |
nor5_dp
This class implements and asynchronous 5-input nor gate. |
class |
nor6_dp
This class implements and asynchronous 6-input nor gate. |
class |
nor7_dp
This class implements and asynchronous 7-input nor gate. |
class |
nor8_dp
This class implements and asynchronous 8-input nor gate. |
class |
nor9_dp
This class implements and asynchronous 9-input nor gate. |
class |
norX
This class implements an NOR gate with arbitrary number of inputs. |
class |
not_dp
Inverter. |
class |
notX
This cell inverts each input wire. |
class |
OB
This is an output buffer. |
class |
OBT
This is an output buffer with a (high?) asserted output enable. |
class |
OBTX
Generic width output buffer. |
class |
OBX
Generic width output buffer. |
class |
or2_dp
This class implements and asynchronous 2-input or gate. |
class |
or2_dp_g
This class implements and asynchronous 2-input or gate. |
class |
or3_dp
This class implements and asynchronous 3-input or gate. |
class |
or3_dp_g
This class implements and asynchronous 3-input or gate. |
class |
or4_dp
This class implements and asynchronous 4-input or gate. |
class |
or5_dp
This class implements and asynchronous 5-input or gate. |
class |
or6_dp
This class implements and asynchronous 6-input or gate. |
class |
or7_dp
This class implements and asynchronous 7-input or gate. |
class |
or8_dp
This class implements and asynchronous 8-input or gate. |
class |
or9_dp
This class implements and asynchronous 9-input or gate. |
class |
orX
This class implements an OR gate with arbitrary number of inputs. |
class |
subX
Generic width subtractor. |
class |
TESTCSRCLibrary
This class is the self-test controller for the CSRC library. |
class |
vccX
This instantiates a generic width vcc. |
class |
xnor2_dp
This class implements and asynchronous 2-input xnor gate. |
class |
xnor2_dp_g
This class implements and asynchronous 2-input xnor gate. |
class |
xnor3_dp
This class implements and asynchronous 3-input xnor gate. |
class |
xnor3_dp_g
This class implements and asynchronous 3-input xnor gate. |
class |
xnor4_dp
This class implements and asynchronous 4-input xnor gate. |
class |
xnor5_dp
This class implements and asynchronous 5-input xnor gate. |
class |
xnor6_dp
This class implements and asynchronous 6-input xnor gate. |
class |
xnor7_dp
This class implements and asynchronous 7-input xnor gate. |
class |
xnor8_dp
This class implements and asynchronous 8-input xnor gate. |
class |
xnor9_dp
This class implements and asynchronous 9-input xnor gate. |
class |
xnorX
This class implements an XNOR gate with arbitrary number of inputs. |
class |
xor2_dp
This class implements and asynchronous 2-input xor gate. |
class |
xor2_dp_g
This class implements and asynchronous 2-input xor gate. |
class |
xor3_dp
This class implements and asynchronous 3-input xor gate. |
class |
xor3_dp_g
This class implements and asynchronous 3-input xor gate. |
class |
xor4_dp
This class implements and asynchronous 4-input xor gate. |
class |
xor5_dp
This class implements and asynchronous 5-input xor gate. |
class |
xor6_dp
This class implements and asynchronous 6-input xor gate. |
class |
xor7_dp
This class implements and asynchronous 7-input xor gate. |
class |
xor8_dp
This class implements and asynchronous 8-input xor gate. |
class |
xor9_dp
This class implements and asynchronous 9-input xor gate. |
class |
xorX
This class implements an XOR gate with arbitrary number of inputs. |
| Methods in byucc.jhdl.CSRC that return Cell | |
Cell |
CSRCTechMapper.map(Logic parent,
Wire[] in,
Wire out,
java.lang.String hints)
|
Cell |
CSRCTechMapper.source(Logic parent,
Wire w1)
Deprecated. use getSourcePlaceable, getSourcePlaceableLeaf, or getSourceLeafCell |
Cell |
CSRCTechMapper.sink(Logic parent,
Wire w1,
Cell c)
Deprecated. use getSinkLeafCell |
Cell |
CSRCTechMapper.getSourcePlaceable(Cell parent,
Wire w1)
|
Cell |
CSRCTechMapper.getSourcePlaceableLeaf(Cell parent,
Wire w1)
|
Cell |
CSRCTechMapper.getSourceLeafCell(Logic parent,
Wire w1)
|
Cell |
CSRCTechMapper.getSinkLeafCell(Logic parent,
Cell c,
Wire w1)
|
| Methods in byucc.jhdl.CSRC with parameters of type Cell | |
protected void |
CSRCTechMapper.insertTechMapHints(Cell c)
|
void |
CSRCTechMapper.place(Logic parent,
Cell c1,
int x,
int y,
java.lang.String hints)
|
Cell |
CSRCTechMapper.sink(Logic parent,
Wire w1,
Cell c)
Deprecated. use getSinkLeafCell |
Cell |
CSRCTechMapper.getSourcePlaceable(Cell parent,
Wire w1)
|
Cell |
CSRCTechMapper.getSourcePlaceableLeaf(Cell parent,
Wire w1)
|
Cell |
CSRCTechMapper.getSinkLeafCell(Logic parent,
Cell c,
Wire w1)
|
PlacementInfo |
CSRCTechMapper.createPlacementInfo(Cell c)
|
java.lang.String |
CSRCTechMapper.getTechMapHint(Logic parent,
Cell c)
|
void |
CSRCTechMapper.clockDriver(Cell parent,
Wire clock_in,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
void |
CSRCTechMapper.clockDriver(Cell parent,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
void |
CSRCTechMapper.buf(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.tbuf(Cell parent,
Wire in,
Wire en,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.pullup(Cell parent,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.pulldown(Cell parent,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.not(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.vcc(Cell parent,
Wire o,
java.lang.String name)
|
void |
CSRCTechMapper.gnd(Cell parent,
Wire o,
java.lang.String name)
|
Wire |
CSRCTechMapper.vcc(Cell parent,
int width,
java.lang.String name)
|
Wire |
CSRCTechMapper.gnd(Cell parent,
int width,
java.lang.String name)
|
void |
CSRCTechMapper.reg(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regc(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regce(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regp(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regpe(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regr(Cell parent,
Wire clk,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regre(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regs(Cell parent,
Wire clk,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regse(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.reg(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regc(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regce(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regp(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regpe(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regr(Cell parent,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regre(Cell parent,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regs(Cell parent,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.regse(Cell parent,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.add(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
CSRCTechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
CSRCTechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
Wire co,
java.lang.String name)
|
void |
CSRCTechMapper.add(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
CSRCTechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
CSRCTechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
java.lang.String name)
|
Wire |
CSRCTechMapper.wire(Cell p,
java.lang.String name)
|
Wire |
CSRCTechMapper.wire(Cell p,
int width,
java.lang.String name)
|
Wire |
CSRCTechMapper.concat(Cell parent,
Wire[] wa,
java.lang.String name)
|
Wire |
CSRCTechMapper.concat(Cell parent,
WireList wl,
java.lang.String name)
|
void |
CSRCTechMapper.mux(Cell parent,
Wire d0,
Wire d1,
Wire sel,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.mux(Cell parent,
Wire d0,
Wire d1,
Wire d2,
Wire d3,
Wire sel,
Wire out,
java.lang.String name)
|
void |
CSRCTechMapper.mux(Cell parent,
Wire d0,
Wire d1,
Wire d2,
Wire d3,
Wire d4,
Wire d5,
Wire d6,
Wire d7,
Wire sel,
Wire out,
java.lang.String name)
|
Wire |
CSRCTechMapper.range(Cell parent,
Wire src,
int hi,
int lo)
|
void |
CSRCTechMapper.constant(Cell parent,
Wire out,
int value,
java.lang.String name)
|
void |
CSRCTechMapper.constant(Cell parent,
Wire out,
long value,
java.lang.String name)
|
void |
CSRCTechMapper.constant(Cell parent,
Wire out,
int[] value,
java.lang.String name)
|
void |
CSRCTechMapper.constant(Cell parent,
Wire out,
BV value,
java.lang.String name)
|
Wire |
CSRCTechMapper.ashiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
CSRCTechMapper.shiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
CSRCTechMapper.shiftl(Cell parent,
Wire in,
int shift,
Wire out)
|
void |
CSRCTechMapper.rom(Cell parent,
Wire addr,
Wire data,
long[] init,
java.lang.String name)
|
void |
CSRCTechMapper.ram(Cell parent,
Wire din,
Wire we,
Wire addr,
Wire dout,
long[] init,
java.lang.String name)
|
void |
CSRCTechMapper.rams(Cell parent,
Wire din,
Wire we,
Wire addr,
Wire dout,
long[] init,
java.lang.String name)
|
void |
CSRCTechMapper.ramd(Cell parent,
Wire din,
Wire we,
Wire addrA,
Wire addrB,
Wire outA,
Wire outB,
long[] init,
java.lang.String name)
|
void |
CSRCTechMapper.padClock(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
CSRCTechMapper.padOut(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
CSRCTechMapper.padIn(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
CSRCTechMapper.padInout(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
CSRCTechMapper.padOutT(Cell parent,
boolean clocked,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
| Constructors in byucc.jhdl.CSRC with parameters of type Cell | |
CSRCClockDriver(Cell parent,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
|
CSRCClockDriver(Cell parent,
Wire clock_in,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
|
CSRCWire(Cell parent,
int width)
|
|
CSRCWire(Cell parent,
int width,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
java.lang.String name)
|
|
CSRCWire(Cell parent,
WireList wl)
|
|
CSRCWire(Cell parent,
WireList wl,
java.lang.String name)
|
|
CSRCWire(Cell parent,
Wire[] wa)
|
|
CSRCWire(Cell parent,
Wire[] wa,
java.lang.String name)
|
|
| Uses of Cell in byucc.jhdl.DRC |
| Subclasses of Cell in byucc.jhdl.DRC | |
class |
DBone
A skeleton TBone-like class for checking circuits against design rules. |
class |
Toggler
|
| Fields in byucc.jhdl.DRC declared as Cell | |
protected Cell |
DesignRuleChecker.topCell
topCell is the Cell to be checked; all descendents of this cell are (generally) checked also. |
| Methods in byucc.jhdl.DRC that return Cell | |
Cell |
DBone.getTopCell()
Returns the top cell in the circuit. |
Cell |
DesignRuleChecker.getTopCell()
Returns a reference to the top-level cell which this DesignRuleChecker is checking |
| Methods in byucc.jhdl.DRC with parameters of type Cell | |
void |
DesignRuleChecker.initDRC(Cell topCell)
Common constructor code for initialization. |
boolean |
DesignRuleChecker.doCheck(Cell newCell)
Initiates the design rule check on a new topCell |
protected void |
DesignRuleChecker.addToCellList(CellList list,
Cell cl)
I wasn't sure it would be a good idea to make the insert method of the CellList class public. |
void |
DesignRuleChecker.setCell(Cell newCell)
Set the topCell to the new cell specified |
static boolean |
DesignRuleChecker.checkRule(Cell parent,
Cell toCheck,
DesignRule rule)
A static utility methods to check one rule against a component set. |
static boolean |
DesignRuleChecker.checkRule(Cell parent,
Cell toCheck,
DesignRule rule,
DesignRuleBrowser drb)
A static utility methods to check one rule against a component set. |
static boolean |
DesignRuleChecker.checkRule(Cell parent,
Cell toCheck,
DesignRule rule,
boolean drbFlag)
A static utility methods to check one rule against a component set. |
static boolean |
DesignRuleChecker.checkRules(Cell parent,
Cell toCheck,
DesignRule[] rules)
A static utility methods to check a set of rules against a component set. |
static boolean |
DesignRuleChecker.checkRules(Cell parent,
Cell toCheck,
java.util.Vector rules)
A static utility methods to check a set of rules against a component set. |
static boolean |
DesignRuleChecker.checkRules(Cell parent,
Cell toCheck,
java.util.Vector rules,
boolean useBrowser)
A static utility methods to check a set of rules against a component set. |
static boolean |
DesignRuleChecker.checkRules(Cell parent,
Cell toCheck,
DesignRule rule,
boolean useBrowser)
A static utility methods to check a set of rules against a component set. |
static boolean |
DesignRuleChecker.runTest(Cell parent,
Cell toCheck,
java.util.Vector rules)
A static utility methods to check a set of rules against a component set for the purpose of checking the integrity of this class. |
DesignRuleViolation[] |
DesignRuleChecker.getDesignRuleViolationsForCells(Cell[] cells)
Returns the set of design rule violations associated with a specific set of cells. |
void |
DesignRuleChecker.addViolatingCell(Cell cell)
Adds a violating cell to the internal list of violating cells. |
protected abstract void |
DesignRule.sortCell(Cell cl)
To be implemented by subclasses so they may sort cells into appropriate containers. |
protected static void |
DesignRule.addToCellList(CellList list,
Cell cl)
I wasn't sure it would be a good idea to make the insert method of the CellList class public. |
protected void |
DesignRule.addToCellList(Cell cl)
|
protected void |
DesignRule.addViolatingCell(Cell vCell)
Adds a violating cell to the violatingCells Vector. |
| Constructors in byucc.jhdl.DRC with parameters of type Cell | |
DesignRuleChecker(Cell topCell)
Initializes the DesignRuleChecker to check the Cell topCell. |
|
DesignRuleChecker(Cell parentCell,
Cell topCell)
|
|
DesignRuleViolation(int drcvId,
DesignRule violatedRule,
Cell vCell,
int severityLevel)
|
|
DesignRuleViolation(int drcvId,
DesignRule violatedRule,
Cell vCell)
|
|
| Uses of Cell in byucc.jhdl.DRC.Rules |
| Fields in byucc.jhdl.DRC.Rules declared as Cell | |
protected Cell |
IBufsAndOBufs.topCell
The top-level Cell being checked |
| Methods in byucc.jhdl.DRC.Rules with parameters of type Cell | |
protected abstract boolean |
MultipleDrivers.isTriStateBuffer(Cell cell)
Must be implemented for each architecture. |
void |
MultipleDrivers.sortCell(Cell cell)
Grabs all the input wires for all the cells. |
void |
Template.sortCell(Cell cl)
|
void |
Bufg.sortCell(Cell cell)
|
protected abstract boolean |
Bufg.isBufg(Cell cell)
|
protected void |
ClockWires.sortCell(Cell cl)
This method is called by the DesignRuleChecker for each descendant of the top-level cell. |
protected void |
IBufsAndOBufs.sortCell(Cell cl)
Sorts Cells according to type. |
protected abstract boolean |
IBufsAndOBufs.isOBuf(Cell cl)
Returns true if cl is an instance of an obuf-type cell. |
protected abstract boolean |
IBufsAndOBufs.isIBuf(Cell cl)
Returns true if cl is an instance of an ibuf-type cell. |
protected abstract boolean |
IBufsAndOBufs.isOPad(Cell cell)
|
protected abstract boolean |
IBufsAndOBufs.isOPad_sim(Cell cell)
|
protected abstract boolean |
IBufsAndOBufs.isIOPad(Cell cell)
|
protected abstract boolean |
IBufsAndOBufs.isIPad(Cell cell)
|
protected abstract boolean |
IBufsAndOBufs.isIPad_sim(Cell cell)
|
protected boolean |
IBufsAndOBufs.checkPadCell(Cell cl)
|
void |
DeadHardware.sortCell(Cell cl)
|
void |
AddPropertyMissing.sortCell(Cell cl)
|
void |
NoConnect.sortCell(Cell cl)
|
protected void |
IOBufs.sortCell(Cell cl)
Sorts Cells according to type. |
abstract boolean |
IOBufs.isIOBuf(Cell cl)
Returns true if cl is an instance of a platform-specific iobuf-type cell. |
protected boolean |
IOBufs.isIOPad(Cell sourceCell)
|
| Uses of Cell in byucc.jhdl.DRC.Rules.Virtex |
| Methods in byucc.jhdl.DRC.Rules.Virtex with parameters of type Cell | |
protected boolean |
BufgVirtex.isBufg(Cell cell)
|
protected boolean |
IBufsAndOBufsVirtex.isOBuf(Cell cl)
Returns true if cl is an instance of a Xilinx obuf-type cell or a Virtex obuf-type cell. |
protected boolean |
IBufsAndOBufsVirtex.isIBuf(Cell cl)
Returns true if cl is an instance of a Xilinx ibuf-type cell or a Virtex ibuf-type cell. |
boolean |
IBufsAndOBufsVirtex.isOPad(Cell cell)
|
protected boolean |
IBufsAndOBufsVirtex.isOPad_sim(Cell cell)
|
protected boolean |
IBufsAndOBufsVirtex.isIOPad(Cell cell)
|
protected boolean |
IBufsAndOBufsVirtex.isIPad(Cell cell)
|
protected boolean |
IBufsAndOBufsVirtex.isIPad_sim(Cell cell)
|
boolean |
IOBufsVirtex.isIOBuf(Cell cl)
|
| Uses of Cell in byucc.jhdl.DRC.Rules.XC4000 |
| Methods in byucc.jhdl.DRC.Rules.XC4000 with parameters of type Cell | |
protected boolean |
MultipleDriversXC4000.isTriStateBuffer(Cell cell)
|
protected boolean |
BufgXC4000.isBufg(Cell cell)
|
protected boolean |
IBufsAndOBufsXC4000.isOBuf(Cell cl)
Returns true if cl is an instance of an XC4000 obuf-type cell |
protected boolean |
IBufsAndOBufsXC4000.isIBuf(Cell cl)
Returns true if cl is an instance of an XC4000 ibuf-type cell |
boolean |
IBufsAndOBufsXC4000.isOPad(Cell cell)
|
protected boolean |
IBufsAndOBufsXC4000.isOPad_sim(Cell cell)
|
protected boolean |
IBufsAndOBufsXC4000.isIOPad(Cell cell)
|
protected boolean |
IBufsAndOBufsXC4000.isIPad(Cell cell)
|
protected boolean |
IBufsAndOBufsXC4000.isIPad_sim(Cell cell)
|
boolean |
IOBufsXC4000.isIOBuf(Cell cl)
|
| Uses of Cell in byucc.jhdl.DRC.Tester |
| Subclasses of Cell in byucc.jhdl.DRC.Tester | |
class |
DesignRuleCheckerTester
|
class |
LogicMisplacement
This design targets the Digilab XC4000 Spartan architecture. |
class |
MultiplePuts
This design targets the Digilab XC4000 Spartan architecture. |
class |
NoBufg
This design violates the rule of not running an explicit clock wire through a bufg |
| Uses of Cell in byucc.jhdl.examples |
| Subclasses of Cell in byucc.jhdl.examples | |
class |
Calculator
|
class |
FullAdder
|
class |
NBitAdder
|
| Uses of Cell in byucc.jhdl.examples.des |
| Subclasses of Cell in byucc.jhdl.examples.des | |
class |
DES
|
class |
DESLogic
|
class |
DESRoundC
|
class |
SBoxes
|
| Uses of Cell in byucc.jhdl.examples.editDistance |
| Subclasses of Cell in byucc.jhdl.examples.editDistance | |
class |
char_fsm2
|
class |
char_slice2
|
class |
charcomp2
|
class |
edistance2
This is the top level code for finding the evolutionary distance between a target string which is compiled into the hardware, and a source string which is passed through the linear systolic array of character comparitors. |
class |
left_edge2
|
class |
mod4count2
|
class |
upDownCounter
Counter counts up if up_down is a 1, down if up_down is a 0. |
| Uses of Cell in byucc.jhdl.examples.fsm |
| Subclasses of Cell in byucc.jhdl.examples.fsm | |
class |
fsmMemCtl
|
class |
parity
|
| Uses of Cell in byucc.jhdl.examples.shifter |
| Subclasses of Cell in byucc.jhdl.examples.shifter | |
class |
ShiftMuxR
Right shifter mux. |
class |
VarShiftR
Right shifter module generator This module will create an variable width right shifter with that can either do logical or arithmetic shifts |
| Uses of Cell in byucc.jhdl.examples.xr16cpu |
| Subclasses of Cell in byucc.jhdl.examples.xr16cpu | |
class |
adsuovf1
|
class |
adsuovf16
|
class |
bram_1k
|
class |
bram_4k
|
class |
brir
|
class |
control
|
class |
datapath
|
class |
dec16
|
class |
lcdoutport
|
class |
logicops
|
class |
parinport
|
class |
paroutport
|
class |
regfile
|
class |
sport
|
class |
timerefs
|
class |
uar
|
class |
uat
|
class |
xr16vx_1k
|
class |
xr16vx_4k
|
class |
xr16vxcpu
|
| Uses of Cell in byucc.jhdl.Fsm |
| Subclasses of Cell in byucc.jhdl.Fsm | |
class |
Fsm
|
class |
SynthesizedFsm
for automatic FSM Synthesis (temporarily modified from Fsm.java by navanee) main Distinction from Fsm.java is that the csWire can be seen outside and that is the only FSM output. |
| Constructors in byucc.jhdl.Fsm with parameters of type Cell | |
Logsim(Cell parent,
java.io.OutputStream ostream)
|
|
| Uses of Cell in byucc.jhdl.Logic |
| Subclasses of Cell in byucc.jhdl.Logic | |
class |
LibrarySelfTester
This class aids in testing components of a library. |
class |
Logic
The Logic class provides a platform-independent interface into FPGA circuit design. |
class |
LogicGates
This class only exists to split Logic into two files so that it's easier to deal with it. |
class |
LogicStatic
This class only exists to split Logic into two files so that it's easier to deal with it. |
class |
LogicSubCell
This class allows calls to pushHierarchy to create a Logic cell, instead of a feature-less default. |
| Methods in byucc.jhdl.Logic that return Cell | |
Cell |
TechMapper.map(Logic parent,
Wire[] in,
Wire out,
java.lang.String hints)
|
Cell |
TechMapper.getSourcePlaceable(Cell parent,
Wire w1)
|
Cell |
TechMapper.getSourcePlaceableLeaf(Cell parent,
Wire w1)
|
Cell |
TechMapper.getSourceLeafCell(Logic parent,
Wire w1)
|
Cell |
TechMapper.getSinkLeafCell(Logic parent,
Cell c,
Wire w1)
|
Cell |
Logic.map(Wire i1,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire i6,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire i6,
Wire i7,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire i6,
Wire i7,
Wire i8,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire i6,
Wire i7,
Wire i8,
Wire i9,
Wire o)
Attempts to map given wires to a single architectural "primitive" in the target device. |
Cell |
Logic.map(Wire i1,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire i6,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire i6,
Wire i7,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire i6,
Wire i7,
Wire i8,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
Cell |
Logic.map(Wire i1,
Wire i2,
Wire i3,
Wire i4,
Wire i5,
Wire i6,
Wire i7,
Wire i8,
Wire i9,
Wire o,
java.lang.String hints)
Attempts to map given wires to a single architectural "primitive" in the target device, with String
hints. |
protected Cell |
Logic.map(Wire[] warray,
Wire o,
java.lang.String hints)
|
Cell |
Logic.translate(Wire w,
int dx,
int dy)
Translate the source of wire w by dx in the x direction and dy in the y direction. |
Cell |
Logic.translate(Cell c,
int dx,
int dy)
Translates the specified cell by dx in the x direction and dy in the y direction. |
Cell |
Logic.rotate(Wire w,
int degrees)
Rotates the source of the specified wire by the specifed number of degrees in a counter-clockwise direction. |
Cell |
Logic.rotate(Cell c,
int degrees)
Rotates the specified cell by the specifed number of degrees in a counter-clockwise direction. |
Cell |
Logic.scale(Wire w,
int xFact,
int yFact)
Scales the source of the specified wire by the specifed amount in the x direction and by the specified amount in the y direction. |
Cell |
Logic.scale(Cell c,
int xFact,
int yFact)
Scales the specified cell by the specifed amount in the x direction and by the specified amount in the y direction. |
Cell |
Logic.source(Wire w)
Deprecated. Use getSourceCell(Wire w), getSourceLeaf(Wire w), or getSourcePlaceable(Wire w), getSourcePlaceableLeaf(Wire w) |
Cell |
Logic.getSourceCell(Wire w)
Finds the hierarchical/simulation source of the wire parameter. |
static Cell |
Logic.getSourceCell(Cell parent,
Wire w)
Finds the hierarchical/simulation source of the wire parameter. |
static Cell |
Logic.getSourceLeaf(Wire w)
Finds the leaf source of the wire parameter. |
Cell |
Logic.getSourcePlaceable(Wire w)
Finds the placeable hierarchical source of the wire parameter. |
Cell |
Logic.getSourcePlaceableLeaf(Wire w)
Finds the placeable leaf source of the wire parameter. |
Cell |
Logic.sink(Wire w,
Cell c)
|
static Cell |
Logic.getSinkCell(Wire w)
Finds the simulation sink of the wire parameter. |
| Methods in byucc.jhdl.Logic with parameters of type Cell | |
void |
BasicTechMapper.netlist(Cell cell)
Netlists the given cell downward hierarchically into the given file, using the netlister's choice of default filename. |
void |
BasicTechMapper.netlist(Cell cell,
java.lang.String filename)
Netlists the given cell downward hierarchically into the given file. |
void |
BasicTechMapper.netlist(Cell cell,
boolean flat)
Netlists the given cell downward hierarchically into the given file, using the netlister's choice of default filename. |
void |
BasicTechMapper.netlist(Cell cell,
boolean flat,
java.lang.String filename)
Netlists the given cell downward hierarchically into the given file. |
void |
BasicTechMapper.netlist(Cell cell,
boolean flat,
NetlistWriter nw)
Netlists the given cell downward hierarchically into the given file. |
void |
BasicTechMapper.clockDriver(Cell parent,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
void |
BasicTechMapper.buf(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.tbuf(Cell parent,
Wire in,
Wire en,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.pullup(Cell parent,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.pulldown(Cell parent,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.and(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.or(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.mux(Cell parent,
Wire[] d,
Wire sel,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.xor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.nand(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.nor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.xnor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.not(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.reg(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.reg(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
BasicTechMapper.vcc(Cell parent,
Wire o,
java.lang.String name)
|
void |
BasicTechMapper.gnd(Cell parent,
Wire o,
java.lang.String name)
|
void |
BasicTechMapper.add(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
BasicTechMapper.add(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
BasicTechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
BasicTechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
BasicTechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
Wire co,
java.lang.String name)
|
void |
BasicTechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
java.lang.String name)
|
Wire |
BasicTechMapper.wire(Cell parent,
java.lang.String name)
|
Wire |
BasicTechMapper.wire(Cell parent,
int width,
java.lang.String name)
|
Wire |
BasicTechMapper.concat(Cell parent,
WireList wl,
java.lang.String name)
|
Wire |
BasicTechMapper.concat(Cell parent,
Wire[] list,
java.lang.String name)
|
Wire |
BasicTechMapper.range(Cell parent,
Wire in,
int hi,
int lo)
|
Wire |
BasicTechMapper.ashiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
BasicTechMapper.shiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
BasicTechMapper.shiftl(Cell parent,
Wire in,
int shift,
Wire out)
|
void |
BasicTechMapper.constant(Cell parent,
Wire out,
int value,
java.lang.String name)
|
void |
BasicTechMapper.constant(Cell parent,
Wire out,
BV value,
java.lang.String name)
|
void |
BasicTechMapper.padClock(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
BasicTechMapper.padIn(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
BasicTechMapper.padInout(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
BasicTechMapper.padOut(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
BasicTechMapper.padOutT(Cell parent,
boolean clocked,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
TechMapper.netlist(Cell cell,
java.lang.String filename)
Netlists the given cell downward hierarchically into the given file. |
void |
TechMapper.netlist(Cell cell,
boolean flat,
java.lang.String filename)
Netlists the given cell downward hierarchically into the given file. |
void |
TechMapper.netlist(Cell cell,
boolean flat,
NetlistWriter nw)
Netlists the given cell downward hierarchically into the given file. |
protected void |
TechMapper.insertTechMapHints(Cell cell)
Does the work necessary to insert hints in the netlist of the cell. |
void |
TechMapper.place(Logic parent,
Cell c1,
int x,
int y,
java.lang.String hints)
|
Cell |
TechMapper.getSourcePlaceable(Cell parent,
Wire w1)
|
Cell |
TechMapper.getSourcePlaceableLeaf(Cell parent,
Wire w1)
|
Cell |
TechMapper.getSinkLeafCell(Logic parent,
Cell c,
Wire w1)
|
PlacementInfo |
TechMapper.createPlacementInfo(Cell c)
|
java.lang.String |
TechMapper.getTechMapHint(Logic parent,
Cell c)
|
void |
TechMapper.regc(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
TechMapper.regce(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
TechMapper.regp(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
TechMapper.regpe(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
TechMapper.regr(Cell parent,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
TechMapper.regre(Cell parent,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
TechMapper.regs(Cell parent,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
TechMapper.regse(Cell parent,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
TechMapper.regc(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
TechMapper.regce(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
TechMapper.regp(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
TechMapper.regpe(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
TechMapper.regr(Cell parent,
Wire clk,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
TechMapper.regre(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
TechMapper.regs(Cell parent,
Wire clk,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
TechMapper.regse(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
Logic.place(Cell c,
int x,
int y)
Annotates [x,y] placement hint onto the Cell parameter. |
void |
Logic.place(Cell c,
java.lang.String s)
Annotates target-specific String placement hint onto
the Cell parameter. |
static void |
Logic.place(Cell c,
int x,
int y,
java.lang.String s)
Aqnnotates [x,y] placement hint and target-specific String hint onto the Cell parameter. |
static void |
Logic.place(Cell c,
int x,
int y,
java.lang.String s,
boolean complain)
This is just here to let internal Logic placement not have warning messages. |
void |
Logic.place(Cell curr_cell,
Directive dir,
Wire prev_out)
Places curr_cell in the direction of dir from the cell associate with prev_out. |
void |
Logic.place(Wire curr_out,
Directive dir,
Cell prev_cell)
Places the cell associate with curr_out in the direction of dir from prev_cell. |
void |
Logic.place(Cell curr_cell,
Directive dir,
Cell prev_cell)
Places the cell curr_cell in the direction of dir from prev_cell. |
void |
Logic.place(Wire currWire,
Cell curr_cell,
Directive dir,
Wire prevWire,
Wire prev_out)
This place method is a convenience method for port placement. |
void |
Logic.place(Wire currWire,
Wire curr_out,
Directive dir,
Wire prevWire,
Cell prev_cell)
This place method is a convenience method for port placement. |
void |
Logic.place(Wire currWire,
Cell curr_cell,
Directive dir,
Wire prevWire,
Cell prev_cell)
This place method is the interface through which all port placement is done. |
Cell |
Logic.translate(Cell c,
int dx,
int dy)
Translates the specified cell by dx in the x direction and dy in the y direction. |
Cell |
Logic.rotate(Cell c,
int degrees)
Rotates the specified cell by the specifed number of degrees in a counter-clockwise direction. |
Cell |
Logic.scale(Cell c,
int xFact,
int yFact)
Scales the specified cell by the specifed amount in the x direction and by the specified amount in the y direction. |
static java.awt.Point |
Logic.setBBox(Cell par)
This method computes the bounding box of a cell, translates the children of that cell to position the upper left hand corner at (0,0) and returns how far the children were translated. |
protected java.awt.Point |
Logic.setWandH(Cell par)
|
static void |
Logic.lockChildPlacement(Cell c)
Locks the placement of the children of the specified cell. |
static Cell |
Logic.getSourceCell(Cell parent,
Wire w)
Finds the hierarchical/simulation source of the wire parameter. |
Cell |
Logic.sink(Wire w,
Cell c)
|
java.lang.String |
Logic.getTechMapHint(Cell c)
Returns a String describing the technology mapping
hints for the Cell parameter. |
static void |
Logic.netlist(Cell cell)
Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister. |
static void |
Logic.netlist(Cell cell,
java.lang.String filename)
Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister. |
static void |
Logic.netlist(Cell cell,
boolean flat)
Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister. |
static void |
Logic.netlist(Cell cell,
boolean flat,
java.lang.String filename)
Creates a netlist of the default variety determined by the techmapper, and default filename determined by the netlister. |
static Wire |
LogicStatic.buf(Cell parent,
Wire in)
Constructs a new buffer, with a new wire as its output. |
static Wire |
LogicStatic.buf(Cell parent,
Wire in,
java.lang.String name)
Constructs a new buffer, with a new wire as its output. |
static Wire |
LogicStatic.and(Cell parent,
Wire in)
|
static Wire |
LogicStatic.and(Cell parent,
Wire in1,
Wire in2)
Constructs a new 2-input and gate, with a new wire as its output. |
static Wire |
LogicStatic.and_o(Cell parent,
Wire in,
Wire out,
java.lang.String name)
Constructs a new arbitrary-number-input and gate. |
static Wire |
LogicStatic.and_o(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
Constructs a new 2-input and gate. |
static Wire |
LogicStatic.or(Cell parent,
Wire in)
Constructs a new named arbitrary-number-input or gate, with a new wire as its output. |
static Wire |
LogicStatic.or(Cell parent,
Wire in1,
Wire in2)
Constructs a new 2-input or gate with a new wire as its output. |
static Wire |
LogicStatic.or_o(Cell parent,
Wire in,
Wire out,
java.lang.String name)
Constructs a new arbitrary-number-input or gate. |
static Wire |
LogicStatic.or_o(Cell parent,
Wire in1,
Wire in2,
Wire out)
Constructs a new 2-input or gate. |
static Wire |
LogicStatic.xor(Cell parent,
Wire in1,
Wire in2)
Constructs a new 2-input xor gate with a new wire as its output. |
static Wire |
LogicStatic.xor_o(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
Constructs a new 2-input xor gate. |
static Wire |
LogicStatic.xnor(Cell parent,
Wire in1,
Wire in2)
Constructs a new 2-input xnor gate with a new wire as its output. |
static Wire |
LogicStatic.xnor_o(Cell parent,
Wire in,
Wire out,
java.lang.String name)
Constructs a new arbitrary-number-input xnor gate. |
static Wire |
LogicStatic.xnor_o(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
Constructs a new 2-input xnor gate. |
static Wire |
LogicStatic.reg(Cell parent,
Wire d)
Constructs a new register with a new wire as its output. |
static Wire |
LogicStatic.reg_o(Cell parent,
Wire d,
Wire q,
java.lang.String name)
Constructs a new register. |
static Wire |
LogicStatic.not(Cell parent,
Wire i)
Constructs a new inverter with a new wire as its output. |
static Wire |
LogicStatic.not(Cell parent,
Wire i,
java.lang.String name)
Constructs a new inverter with a new wire as its output. |
static Wire |
LogicStatic.not_o(Cell parent,
Wire i,
Wire o)
Constructs a new inverter. |
static Wire |
LogicStatic.not_o(Cell parent,
Wire i,
Wire o,
java.lang.String name)
Constructs a new inverter. |
static Wire |
LogicStatic.mux(Cell parent,
Wire d0,
Wire d1,
Wire d2,
Wire d3,
Wire d4,
Wire d5,
Wire d6,
Wire d7,
Wire sel)
Constructs a new multiplexor. |
static Wire |
LogicStatic.mux_o(Cell parent,
Wire d0,
Wire d1,
Wire d2,
Wire d3,
Wire d4,
Wire d5,
Wire d6,
Wire d7,
Wire sel,
Wire o,
java.lang.String name)
Constructs a new multiplexor. |
static Wire |
LogicStatic.vcc(Cell parent)
Returns a new atomic-width wire connected to power. |
static Wire |
LogicStatic.vcc(Cell parent,
java.lang.String name)
Returns a new atomic-width wire connected to power. |
static Wire |
LogicStatic.vcc(Cell parent,
int width)
Returns a new wire of the specified width connected to power. |
static Wire |
LogicStatic.vcc(Cell parent,
int width,
java.lang.String name)
Returns a new wire of the specified width connected to power. |
static Wire |
LogicStatic.vcc_o(Cell parent,
Wire o)
Connects wire o to power, and returns o. |
static Wire |
LogicStatic.vcc_o(Cell parent,
Wire o,
java.lang.String name)
Connects wire o to power, and returns o. |
static Wire |
LogicStatic.gnd(Cell parent)
Returns a new atomic-width wire connected to ground. |
static Wire |
LogicStatic.gnd(Cell parent,
java.lang.String name)
Returns a new atomic-width wire connected to ground. |
static Wire |
LogicStatic.gnd(Cell parent,
int width)
Returns a new wire of the specified width connected to ground. |
static Wire |
LogicStatic.gnd(Cell parent,
int width,
java.lang.String name)
Returns a new wire of the specified width connected to ground. |
static Wire |
LogicStatic.gnd_o(Cell parent,
Wire o)
Connects wire o to ground, and returns o. |
static Wire |
LogicStatic.gnd_o(Cell parent,
Wire o,
java.lang.String name)
Connects wire o to ground, and returns o. |
static Wire |
LogicStatic.add_o(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
Constructs a new adder with no carry-out. |
static Wire |
LogicStatic.add_o(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
Constructs a new adder. |
static Wire |
LogicStatic.wire(Cell p)
Constructs a new "primitive" wire, with the specified Node as parent. |
static Wire |
LogicStatic.wire(Cell p,
java.lang.String name)
Constructs a new named "primitive" wire, with the specified Node as parent. |
static Wire |
LogicStatic.wire(Cell p,
int width)
Constructs a new wire of width width, with the specified Node as parent. |
static Wire |
LogicStatic.wire(Cell p,
int width,
java.lang.String name)
Constructs a new named wire of width width, with the specified Node as parent. |
static Wire |
LogicStatic.concat(Cell parent,
Wire[] wa)
Returns a new wire that is the concatenation of the wires in the Wire[] parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
Wire o)
Returns a new wire that is the concatenation of the input parameter wires. |
static Wire |
LogicStatic.concat_o(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
Wire o,
java.lang.String name)
Returns a new wire that is the concatenation of the wire parameter, with name given by the String parameter. |
static Wire |
LogicStatic.nc(Cell parent)
Constructs a "dangling output" wire of width 1. |
static Wire |
LogicStatic.nc(Cell parent,
java.lang.String name)
|
static Wire |
LogicStatic.nc(Cell parent,
int width)
Constructs a "dangling output" wire of width width. |
static Wire |
LogicStatic.nc(Cell parent,
int width,
java.lang.String name)
|
static Wire |
LogicStatic.constant(Cell parent,
int width,
int value,
java.lang.String name)
Constructs a new named wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
int width,
long value,
java.lang.String name)
Constructs a new named wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
int width,
int[] value,
java.lang.String name)
Constructs a new named wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
int width,
BV value,
java.lang.String name)
Constructs a new named wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
BV value,
java.lang.String name)
Constructs a new named wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
int width,
int value)
Constructs a new wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
int width,
long value)
Constructs a new wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
int width,
int[] value)
Constructs a new wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
int width,
BV value)
Constructs a new wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant(Cell parent,
BV value)
Constructs a new wire of width width, driven with constant value value. |
static Wire |
LogicStatic.constant_o(Cell parent,
Wire o,
int value)
Drives the constant value value onto the wire parameter. |
static Wire |
LogicStatic.constant_o(Cell parent,
Wire o,
long value)
Drives the constant value value onto the wire parameter. |
static Wire |
LogicStatic.constant_o(Cell parent,
Wire o,
int[] value)
Drives the constant value value onto the wire parameter. |
static Wire |
LogicStatic.constant_o(Cell parent,
Wire o,
BV value)
Drives the constant value value onto the wire parameter. |
static Wire |
LogicStatic.constant_o(Cell parent,
Wire o,
int value,
java.lang.String name)
Drives the constant value value onto the wire parameter. |
static Wire |
LogicStatic.constant_o(Cell parent,
Wire o,
long value,
java.lang.String name)
Drives the constant value value onto the wire parameter. |
static Wire |
LogicStatic.constant_o(Cell parent,
Wire o,
int[] value,
java.lang.String name)
Drives the constant value value onto the wire parameter. |
static Wire |
LogicStatic.constant_o(Cell parent,
Wire o,
BV value,
java.lang.String name)
Drives the constant value value onto the wire parameter. |
void |
TechMapPadInterface.insertPads(Cell top)
Insert pads for the given cell |
void |
LibrarySelfTester.setCell(Cell c)
Initializes the test vectors for the given cell. |
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire[] warray,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
Wire w1,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
Wire w1,
Wire w2,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
Wire w1,
Wire w2,
Wire w3,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
int width,
int function)
|
static int[] |
WideBooleanFunction.compute(Cell cell,
Wire w0,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
int width,
int function)
|
| Constructors in byucc.jhdl.Logic with parameters of type Cell | |
LogicWire(Cell parent,
WireList wl)
Deprecated. Use LogicWire(Cell, Wire[]) |
|
LogicWire(Cell parent,
WireList wl,
java.lang.String name)
Deprecated. Use LogicWire(Cell, Wire[], String) |
|
LogicWire(Cell parent,
Wire[] wa)
|
|
LogicWire(Cell parent,
Wire[] wa,
java.lang.String name)
|
|
LogicWire(Cell parent,
int width)
|
|
LogicWire(Cell parent,
int width,
java.lang.String name)
|
|
| Uses of Cell in byucc.jhdl.Logic.Modules |
| Subclasses of Cell in byucc.jhdl.Logic.Modules | |
class |
COMPARATORS
General Description |
class |
CORDICS
General Description |
class |
COUNTERS
General Description |
class |
Decoder
implements an arbitrary-width decoder out of standard (wide) AND gates. |
class |
decoder1_2
General Description |
class |
decoder2_4
General Description |
class |
decoder3_8
General Description |
class |
decoder4_16
General Description |
class |
decoder5_32
General Description |
class |
decoder6_64
General Description |
class |
decoder7_128
General Description |
class |
decoder8_256
General Description |
class |
DECODERS
General Description |
class |
DIVIDERS
General Description |
class |
Duplicate
simply takes the one bit input wire and replicates it for every bit of the output. |
class |
Encoder
encodes the one-hot input value. |
class |
FreeRunTimer
a free-running timer that triggers (times out) at a user-defined interval. |
class |
LogShiftL
implements a barrel shifter by cascading a series of muxes. |
class |
LogShiftR
implements a barrel shifter by cascading a series of muxes. |
class |
MULTIPLIERS
General Description |
class |
OTHERS
General Description |
class |
ParallelLeftShiftReg
ParallelLeftShiftReg.java Created: Jan 03 |
class |
ParallelRightShiftReg
ParallelRightShiftReg.java Created: Jan 03 |
class |
Reverse
Completely reverses (mirrors) the bit order of the input, so that LSB becomes MSB, etc... |
class |
toggle
General Description |
class |
UpDownCount
General Description |
| Methods in byucc.jhdl.Logic.Modules with parameters of type Cell | |
static Wire |
CORDICS.gnd(Cell parent,
int width)
|
static Wire |
CORDICS.gnd_o(Cell parent,
Wire o,
java.lang.String name)
|
static Wire |
CORDICS.constant_o(Cell parent,
Wire o,
BV value,
java.lang.String name)
|
| Uses of Cell in byucc.jhdl.Logic.Modules.CordicPack |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.CordicPack | |
class |
carryLogic
|
| Uses of Cell in byucc.jhdl.Logic.Modules.DigitSerial |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.DigitSerial | |
class |
DPSR
|
class |
DS_FIR
|
class |
DS_FIR_module
|
class |
DSadder
|
class |
DScontrol
|
class |
DScross
|
class |
DSmult_module
|
class |
DSmult_module_last
|
class |
DSmultiplier
|
class |
DSPR
|
class |
PSR
|
class |
SPR
|
class |
tb_DS_FIR
|
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint | |
class |
FLOATINGPOINT
General Description |
class |
FPCompare
Floating-point comparator. |
class |
Pipe_SquareRoot
General Description |
class |
SquareRoot
General Description |
class |
toFixed
Under construction - This module is not yet finished. |
class |
toFloat
Fixed-point to floating-point converter (or integer to floating-point). |
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2 |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2 | |
class |
FPDiv_radix2
|
class |
tb_FPDiv_radix2
|
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8 |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8 | |
class |
FPDiv_radix8
|
class |
tb_FPDiv_radix8
|
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.examples |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.examples | |
class |
toFloatExample
A minimal example of toFloat. |
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack | |
class |
UIntDivide
This class may be moved, modified, or deprecated. A simple unsigned integer divider. |
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.helpers |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.helpers | |
class |
FPPack
General Description |
class |
FPUnpack
General Description |
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.Pipe_SqPack | |
class |
Pipe_algorithm
General Description |
class |
Pipe_Algorithm_Stage
General Description |
class |
Pipe_Frac
General Description |
class |
Pipe_Reg_e
General Description |
class |
Pipe_Reg_f
General Description |
class |
Pipe_Remainder
General Description |
class |
Pipe_Scale
General Description |
class |
Pipe_Scale_back
General Description |
class |
Pipe_Square_root
General Description |
class |
Pipe_Stage
General Description |
class |
Pipe_Stages
General Description |
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4 |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4 | |
class |
FPDiv_radix4
|
class |
scale
|
class |
scale_back
|
class |
specialHandler
|
class |
stage
|
class |
stages
|
class |
table
|
class |
tb_FPDiv_radix4
|
| Uses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.SqPack |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.FloatingPoint.SqPack | |
class |
Algorithm
General Description |
class |
counter
General Description |
class |
Exponent
General Description |
class |
Frac
General Description |
class |
Remainder
General Description |
class |
Scale
General Description |
class |
Scale_back
General Description |
class |
Square_root
General Description |
class |
Valid
General Description |
| Uses of Cell in byucc.jhdl.Logic.Modules.helpers |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.helpers | |
class |
tb_Template
Generic superclass for Module testbenches. |
| Methods in byucc.jhdl.Logic.Modules.helpers with parameters of type Cell | |
protected void |
tb_Template.buildNetlist(Cell cell,
boolean xBuild)
Generates an EDIF netlist and optionally builds the design. |
| Uses of Cell in byucc.jhdl.Logic.Modules.ShiftRegPack |
| Subclasses of Cell in byucc.jhdl.Logic.Modules.ShiftRegPack | |
class |
ShiftRegBit
ShiftRegBit.java Created: Jan 03 |
| Uses of Cell in byucc.jhdl.netlisters |
| Fields in byucc.jhdl.netlisters declared as Cell | |
protected Cell |
Netlister.topcell
The root cell of the netlist |
| Methods in byucc.jhdl.netlisters with parameters of type Cell | |
java.lang.String |
VHDLNetlister.generateFilename(Cell c)
Generates a netlist filename. |
void |
VHDLNetlister.netlist(Cell c,
java.lang.String file)
Create a structural vhdl netlist. |
protected void |
VHDLNetlister.expand(Cell currentCell,
NetlistWriter output)
|
void |
VHDLNetlister.header(Cell c,
NetlistWriter output)
Instantiates header from Netlister, prints preliminary part of netlist |
void |
VHDLNetlister.footer(Cell c,
NetlistWriter output)
Instantiates footer from Netlister, no conclusion needed |
java.lang.String |
OptNetlister.generateFilename(Cell c)
Creates the default filename for edif generated for the given cell |
void |
OptNetlister.netlist(Cell c,
java.lang.String file)
Netlists the given cell to the named file |
protected void |
OptNetlister.expand(Cell c,
NetlistWriter output)
Netlists the given cell to the given output writer |
protected void |
OptNetlister.header(Cell c,
NetlistWriter output)
Generates the file header for the netlist. |
protected void |
OptNetlister.footer(Cell top,
NetlistWriter output)
Generates the tail of the netlist file. |
java.lang.String |
EDIFNetlister.generateFilename(Cell c)
Creates the default filename for edif generated for the given cell |
void |
EDIFNetlister.netlist(Cell c,
java.lang.String file)
Netlists the given cell to the named file |
protected void |
EDIFNetlister.expand(Cell c,
NetlistWriter output)
Netlists the given cell to the given output writer |
protected void |
EDIFNetlister.header(Cell c,
NetlistWriter output)
Generates the file header for the netlist. |
protected void |
EDIFNetlister.footer(Cell top,
NetlistWriter output)
Generates the tail of the netlist file. |
void |
Netlister.netlist(Cell top)
Netlists the given cell and its hierarchical subtree. |
void |
Netlister.netlist(Cell top,
boolean flat)
Netlists the given cell and its hierarchical subtree |
void |
Netlister.netlist(Cell top,
boolean flat,
java.lang.String filename)
Netlists the given cell and its hierarchical subtree |
void |
Netlister.netlist(Cell top,
boolean flat,
NetlistWriter output)
Netlists the given cell and its hierarchical subtree. |
void |
Netlister.netlist(Cell top,
java.lang.String filename)
Netlists the given cell and its hierarchical subtree |
abstract java.lang.String |
Netlister.generateFilename(Cell c)
Given a cell, generate the default file name to place its netlist in |
protected abstract void |
Netlister.header(Cell c,
NetlistWriter output)
Given a cell, returns any initial text to go in the output file before cell expansion |
protected abstract void |
Netlister.expand(Cell c,
NetlistWriter output)
Given a cell, returns the text to go in the output file for cell expansion. |
protected abstract void |
Netlister.footer(Cell c,
NetlistWriter output)
Given a cell, returns any concluding text to go in the output file after cell expansion |
| Uses of Cell in byucc.jhdl.netlisters.jhdl |
| Subclasses of Cell in byucc.jhdl.netlisters.jhdl | |
class |
BuildJHDL
|
| Methods in byucc.jhdl.netlisters.jhdl with parameters of type Cell | |
protected void |
JHDLNetlistWriter.addObjectProperties(Cell c)
iterate through all of the CellProperties for a cell, and if any exist, write them out as an 'addProperty' JHDL call. |
| Constructors in byucc.jhdl.netlisters.jhdl with parameters of type Cell | |
JHDLNetlistWriter(Cell tp)
|
|
JHDLNetlistWriter(Cell tp,
java.lang.String target)
|
|
JHDLNetlistWriter(Cell tp,
java.lang.String target,
java.lang.String filename)
|
|
| Uses of Cell in byucc.jhdl.parsers.edif |
| Methods in byucc.jhdl.parsers.edif that return Cell | |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
PortInterface[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
java.lang.String subcellname,
PortInterface[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
Wire[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
java.lang.String subcellname,
Wire[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
| Methods in byucc.jhdl.parsers.edif with parameters of type Cell | |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
PortInterface[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
java.lang.String subcellname,
PortInterface[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
Wire[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
java.lang.String subcellname,
Wire[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
| Uses of Cell in byucc.jhdl.parsers.edif.NewJHDLGenerator |
| Fields in byucc.jhdl.parsers.edif.NewJHDLGenerator declared as Cell | |
Cell |
Cell.instance
|
| Methods in byucc.jhdl.parsers.edif.NewJHDLGenerator with parameters of type Cell | |
void |
NewJHDLGenerator.build(Cell cell)
|
void |
Cell.buildCell(Cell parent,
PortInterface[] portWires)
|
void |
Cell.buildCell(Cell parent,
Wire[] portWires)
The version above calls this one after sort everything and ensuring that the ports match up and everything is the right width... |
| Uses of Cell in byucc.jhdl.parsers.edif.sablecc |
| Methods in byucc.jhdl.parsers.edif.sablecc that return Cell | |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
EdifPortInterface[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
java.lang.String subcellname,
EdifPortInterface[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
Wire[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
java.lang.String subcellname,
Wire[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(java.lang.String filename,
java.lang.String targetStr)
Method to support the automatic parsing of a file to be used by DRC, etc. |
static Cell |
EdifParser.parse(Tbone tbone,
java.lang.String filename)
Method to support the automatic parsing of a file to be a child of Tbone |
| Methods in byucc.jhdl.parsers.edif.sablecc with parameters of type Cell | |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
EdifPortInterface[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
java.lang.String subcellname,
EdifPortInterface[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
Wire[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
static Cell |
EdifParser.parse(Cell parent,
java.lang.String filename,
java.lang.String subcellname,
Wire[] portWires,
java.lang.String targetStr)
Method to return a JHDL Cell as the result of parsing the given edif file |
| Uses of Cell in byucc.jhdl.parsers.edif.sablecc.translation |
| Fields in byucc.jhdl.parsers.edif.sablecc.translation declared as Cell | |
Cell |
JHDLEdifCell.instance
|
| Methods in byucc.jhdl.parsers.edif.sablecc.translation with parameters of type Cell | |
void |
JHDLEdifCell.buildCell(Cell parent,
EdifPortInterface[] portWires)
Describe buildCell
This does not build cell, it lowercases portWires name, adds to wires vector, create a Wire array from wires vector
and call the following buildCell with the Wire array |
void |
JHDLEdifCell.buildCell(Cell parent,
Wire[] portWires)
The version above calls this one after sort everything and ensuring that the ports match up and everything is the right width... |
| Uses of Cell in byucc.jhdl.parsers.xnf |
| Methods in byucc.jhdl.parsers.xnf that return Cell | |
Cell |
XNFCell.getInstance()
|
Cell |
XNFCell.buildCell(Cell parent,
java.util.Hashtable xnfNets,
java.lang.String newTarget)
|
Cell |
XNFCell.buildCell(Cell parent,
java.util.Hashtable xnfNets)
|
| Methods in byucc.jhdl.parsers.xnf with parameters of type Cell | |
static void |
XNFParser.parseXNF(Cell parent,
java.lang.Object[] ports,
java.lang.String fileName)
parseXNF will instantiate an XNFPrsr and an XNFPrsrVisitor to parse and visit the elements of an .xnf file. |
static void |
XNFParser.parseXNF(Cell parent,
java.lang.Object[] ports,
java.lang.String fileName,
boolean pushHierarchy)
parseXNF will instantiate an XNFPrsr and an XNFPrsrVisitor to parse and visit the elements of an .xnf file. |
static void |
XNFParser.parseXNF(Cell parent,
java.lang.String[] wireNames,
Wire[] xnfWires,
java.lang.String fileName)
parseXNF will instantiate an XNFPrsr and an XNFPrsrVisitor to parse and visit the elements of an .xnf file. |
static void |
XNFParser.parseXNF(Cell parent,
java.lang.String[] wireNames,
Wire[] xnfWires,
java.lang.String fileName,
boolean pushHierarchy)
parseXNF will instantiate an XNFPrsr and an XNFPrsrVisitor to parse and visit the elements of an .xnf file. |
Cell |
XNFCell.buildCell(Cell parent,
java.util.Hashtable xnfNets,
java.lang.String newTarget)
|
Cell |
XNFCell.buildCell(Cell parent,
java.util.Hashtable xnfNets)
|
Wire |
XNFNet.createWireInstance(Cell parent)
|
| Constructors in byucc.jhdl.parsers.xnf with parameters of type Cell | |
XNFToJHDLTranslator(Cell parent,
java.lang.Object[] ports,
java.lang.String fileName)
|
|
XNFToJHDLTranslator(Cell parent,
java.lang.Object[] ports,
java.lang.String fileName,
boolean pushHierarchy)
|
|
XNFToJHDLTranslator(Cell parent,
java.lang.Object[] ports,
java.lang.String target,
java.lang.String fileName)
|
|
XNFToJHDLTranslator(Cell parent,
java.lang.Object[] ports,
java.lang.String target,
java.lang.String fileName,
boolean pushHierarchy)
|
|
XNFToJHDLTranslator(Cell parent,
java.lang.String[] wireNames,
Wire[] wires,
java.lang.String fileName)
|
|
XNFToJHDLTranslator(Cell parent,
java.lang.String[] wireNames,
Wire[] wires,
java.lang.String fileName,
boolean pushHierarchy)
|
|
XNFToJHDLTranslator(Cell parent,
java.lang.String[] wireNames,
Wire[] wires,
java.lang.String target,
java.lang.String fileName)
|
|
XNFToJHDLTranslator(Cell parent,
java.lang.String[] wireNames,
Wire[] wires,
java.lang.String target,
java.lang.String fileName,
boolean pushHierarchy)
|
|
| Uses of Cell in byucc.jhdl.platforms.util |
| Subclasses of Cell in byucc.jhdl.platforms.util | |
class |
GenericBoard
Class designed for making the board-level of board models easier to create. |
class |
GenericInterfaceCell
|
class |
GenericProcessingElement
|
class |
GenericUserCore
Base class to be used for creating wrappers for user designs. |
class |
Virtex_IOB
This class is used to create IOBs for the Xilinx Virtex series parts. |
class |
XC4000_IOB
|
| Methods in byucc.jhdl.platforms.util that return Cell | |
protected Cell |
GenericBoard.instanceCell(java.lang.String instance)
Instances a declared cell. |
protected Cell |
GenericBoard.getCell(java.lang.String name)
Gets a cell for the cell list by its instance name. |
| Uses of Cell in byucc.jhdl.platforms.util.multicontext |
| Subclasses of Cell in byucc.jhdl.platforms.util.multicontext | |
class |
MultiContextTestBench
|
| Uses of Cell in byucc.jhdl.platforms.util.readback |
| Methods in byucc.jhdl.platforms.util.readback that return Cell | |
Cell |
NativeReadBackInterface.findJhdlCell(java.lang.String cellName)
This method finds a JHDL Cell based on its full name
and returns a reference to that Cell, if it is
found. |
| Uses of Cell in byucc.jhdl.platforms.util.readback.Xilinx |
| Methods in byucc.jhdl.platforms.util.readback.Xilinx with parameters of type Cell | |
void |
ReadBackSymbolWriter.writeRBSymInfo(Cell c)
Writes out an .rbsym file for a design starting with
the Cell c as the top-level
Cell. |
void |
ReadBackSymbolWriter.writeRBSymInfo(Cell c,
java.lang.String prefix)
Writes out an .rbsym file for a design starting with
the Cell c as the top-level
Cell, but adds a prefix to all names in the .rbsym
file. |
| Uses of Cell in byucc.jhdl.synth |
| Subclasses of Cell in byucc.jhdl.synth | |
class |
GraphTestBench
|
| Constructors in byucc.jhdl.synth with parameters of type Cell | |
GraphStack(Cell cell)
Constructs a new GraphStack that will be used to synthesize the given cell |
|
| Uses of Cell in byucc.jhdl.TERA |
| Subclasses of Cell in byucc.jhdl.TERA | |
class |
Constant
This class is a structural cell which drives a constant value on to its output wire. |
class |
FD
|
class |
muxX
Generic width 2-1 Mux. |
class |
regX
This instantiates a generic width dff. |
class |
tera_add
Full Adder teramac style. |
class |
tera_and2
This class implements and asynchronous 2-input and gate. |
class |
tera_and2_g
This class implements and asynchronous 2-input and gate. |
class |
tera_and3
This class implements and asynchronous 3-input and gate. |
class |
tera_and3_g
This class implements and asynchronous 3-input and gate. |
class |
tera_and4
This class implements and asynchronous 4-input and gate. |
class |
tera_and4_g
This class implements and asynchronous 4-input and gate. |
class |
tera_and5
This class implements and asynchronous 5-input and gate. |
class |
tera_and5_g
This class implements and asynchronous 5-input and gate. |
class |
tera_and6
This class implements and asynchronous 6-input and gate. |
class |
tera_and6_g
This class implements and asynchronous 6-input and gate. |
class |
tera_and7
This class implements and asynchronous 7-input and gate. |
class |
tera_and7_g
This class implements and asynchronous 7-input and gate. |
class |
tera_and8
This class implements and asynchronous 8-input and gate. |
class |
tera_and8_g
This class implements and asynchronous 8-input and gate. |
class |
tera_buf
Buffer. |
class |
tera_dff
The tera_dff is a simple D-flipflop. |
class |
tera_high
Returns a logic one. |
class |
tera_inv
Inverter. |
class |
tera_low
Returns a logic zero. |
class |
tera_mem
Buffer. |
class |
tera_mux2
Mux2 |
class |
tera_mux4
Mux4 |
class |
tera_nand2
This class implements and asynchronous 2-input nand gate. |
class |
tera_nand2_g
This class implements and asynchronous 2-input nand gate. |
class |
tera_nand3
This class implements and asynchronous 3-input nand gate. |
class |
tera_nand3_g
This class implements and asynchronous 3-input nand gate. |
class |
tera_nand4
This class implements and asynchronous 4-input nand gate. |
class |
tera_nand4_g
This class implements and asynchronous 4-input nand gate. |
class |
tera_nand5
This class implements and asynchronous 5-input nand gate. |
class |
tera_nand5_g
This class implements and asynchronous 5-input nand gate. |
class |
tera_nand6
This class implements and asynchronous 6-input nand gate. |
class |
tera_nand6_g
This class implements and asynchronous 6-input nand gate. |
class |
tera_nand7
This class implements and asynchronous 7-input nand gate. |
class |
tera_nand7_g
This class implements and asynchronous 7-input nand gate. |
class |
tera_nand8
This class implements and asynchronous 8-input nand gate. |
class |
tera_nand8_g
This class implements and asynchronous 8-input nand gate. |
class |
tera_nor2
This class implements and asynchronous 2-input nor gate. |
class |
tera_nor2_g
This class implements and asynchronous 2-input nor gate. |
class |
tera_nor3
This class implements and asynchronous 3-input nor gate. |
class |
tera_nor3_g
This class implements and asynchronous 3-input nor gate. |
class |
tera_nor4
This class implements and asynchronous 4-input nor gate. |
class |
tera_nor4_g
This class implements and asynchronous 4-input nor gate. |
class |
tera_nor5
This class implements and asynchronous 5-input nor gate. |
class |
tera_nor5_g
This class implements and asynchronous 5-input nor gate. |
class |
tera_nor6
This class implements and asynchronous 6-input nor gate. |
class |
tera_nor6_g
This class implements and asynchronous 6-input nor gate. |
class |
tera_nor7
This class implements and asynchronous 7-input nor gate. |
class |
tera_nor7_g
This class implements and asynchronous 7-input nor gate. |
class |
tera_nor8
This class implements and asynchronous 8-input nor gate. |
class |
tera_nor8_g
This class implements and asynchronous 8-input nor gate. |
class |
tera_or2
This class implements and asynchronous 2-input or gate. |
class |
tera_or2_g
This class implements and asynchronous 2-input or gate. |
class |
tera_or3
This class implements and asynchronous 3-input or gate. |
class |
tera_or3_g
This class implements and asynchronous 3-input or gate. |
class |
tera_or4
This class implements and asynchronous 4-input or gate. |
class |
tera_or4_g
This class implements and asynchronous 4-input or gate. |
class |
tera_or5
This class implements and asynchronous 5-input or gate. |
class |
tera_or5_g
This class implements and asynchronous 5-input or gate. |
class |
tera_or6
This class implements and asynchronous 6-input or gate. |
class |
tera_or6_g
This class implements and asynchronous 6-input or gate. |
class |
tera_or7
This class implements and asynchronous 7-input or gate. |
class |
tera_or7_g
This class implements and asynchronous 7-input or gate. |
class |
tera_or8
This class implements and asynchronous 8-input or gate. |
class |
tera_or8_g
This class implements and asynchronous 8-input or gate. |
class |
tera_xnor2
This class implements and asynchronous 2-input xnor gate. |
class |
tera_xnor2_g
This class implements and asynchronous 2-input xnor gate. |
class |
tera_xnor3
This class implements and asynchronous 3-input xnor gate. |
class |
tera_xnor3_g
This class implements and asynchronous 3-input xnor gate. |
class |
tera_xnor4
This class implements and asynchronous 4-input xnor gate. |
class |
tera_xnor4_g
This class implements and asynchronous 4-input xnor gate. |
class |
tera_xnor5
This class implements and asynchronous 5-input xnor gate. |
class |
tera_xnor5_g
This class implements and asynchronous 5-input xnor gate. |
class |
tera_xnor6
This class implements and asynchronous 6-input xnor gate. |
class |
tera_xnor6_g
This class implements and asynchronous 6-input xnor gate. |
class |
tera_xnor7
This class implements and asynchronous 7-input xnor gate. |
class |
tera_xnor7_g
This class implements and asynchronous 7-input xnor gate. |
class |
tera_xnor8
This class implements and asynchronous 8-input xnor gate. |
class |
tera_xnor8_g
This class implements and asynchronous 8-input xnor gate. |
class |
tera_xor2
This class implements and asynchronous 2-input xor gate. |
class |
tera_xor2_g
This class implements and asynchronous 2-input xor gate. |
class |
tera_xor3
This class implements and asynchronous 3-input xor gate. |
class |
tera_xor3_g
This class implements and asynchronous 3-input xor gate. |
class |
tera_xor4
This class implements and asynchronous 4-input xor gate. |
class |
tera_xor4_g
This class implements and asynchronous 4-input xor gate. |
class |
tera_xor5
This class implements and asynchronous 5-input xor gate. |
class |
tera_xor5_g
This class implements and asynchronous 5-input xor gate. |
class |
tera_xor6
This class implements and asynchronous 6-input xor gate. |
class |
tera_xor6_g
This class implements and asynchronous 6-input xor gate. |
class |
tera_xor7
This class implements and asynchronous 7-input xor gate. |
class |
tera_xor7_g
This class implements and asynchronous 7-input xor gate. |
class |
tera_xor8
This class implements and asynchronous 8-input xor gate. |
class |
tera_xor8_g
This class implements and asynchronous 8-input xor gate. |
class |
TERACL
|
class |
TESTTERALibrary
This class is the self-test controller for the TERA library. |
| Methods in byucc.jhdl.TERA with parameters of type Cell | |
protected void |
TechMapper.insertTechMapHints(Cell cell)
|
void |
TechMapper.clockDriver(Cell parent,
Wire clock_in,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
void |
TechMapper.clockDriver(Cell parent,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
void |
TechMapper.buf(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
TechMapper.and(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
TechMapper.or(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
TechMapper.nand(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
TechMapper.nor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
TechMapper.xor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
TechMapper.xnor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
TechMapper.not(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
TechMapper.vcc(Cell parent,
Wire o,
java.lang.String name)
|
void |
TechMapper.gnd(Cell parent,
Wire o,
java.lang.String name)
|
Wire |
TechMapper.vcc(Cell parent,
int width,
java.lang.String name)
|
Wire |
TechMapper.gnd(Cell parent,
int width,
java.lang.String name)
|
void |
TechMapper.reg(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
TechMapper.regce(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
TechMapper.add(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
TechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
TechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
Wire co,
java.lang.String name)
|
void |
TechMapper.add(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
TechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
TechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
java.lang.String name)
|
Wire |
TechMapper.wire(Cell p,
java.lang.String name)
|
Wire |
TechMapper.wire(Cell p,
int width,
java.lang.String name)
|
Wire |
TechMapper.concat(Cell parent,
Wire[] wa,
java.lang.String name)
|
Wire |
TechMapper.concat(Cell parent,
WireList wl,
java.lang.String name)
|
void |
TechMapper.mux(Cell parent,
Wire[] d,
Wire sel,
Wire out,
java.lang.String name)
|
Wire |
TechMapper.range(Cell parent,
Wire src,
int hi,
int lo)
|
void |
TechMapper.constant(Cell parent,
Wire out,
int value,
java.lang.String name)
|
void |
TechMapper.constant(Cell parent,
Wire out,
BV value,
java.lang.String name)
|
void |
TechMapper.padClock(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
TechMapper.padOut(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
TechMapper.padIn(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
TechMapper.padInout(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
TechMapper.padOutT(Cell parent,
boolean clocked,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
| Constructors in byucc.jhdl.TERA with parameters of type Cell | |
TWire(Cell parent,
int width)
|
|
TWire(Cell parent,
int width,
java.lang.String name)
|
|
TWire(Cell parent,
Wire w1,
Wire w2)
|
|
TWire(Cell parent,
Wire w1,
Wire w2,
Wire w3)
|
|
TWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4)
|
|
TWire(Cell parent,
Wire w1,
Wire w2,
java.lang.String name)
|
|
TWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
java.lang.String name)
|
|
TWire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
java.lang.String name)
|
|
TWire(Cell parent,
WireList wl)
|
|
TWire(Cell parent,
WireList wl,
java.lang.String name)
|
|
TWire(Cell parent,
Wire[] wa)
|
|
TWire(Cell parent,
Wire[] wa,
java.lang.String name)
|
|
ClockDriver(Cell parent,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
|
ClockDriver(Cell parent,
Wire clock_in,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
|
| Uses of Cell in byucc.jhdl.util.gui |
| Methods in byucc.jhdl.util.gui that return Cell | |
Cell |
SelectedCellList.getCell()
|
| Methods in byucc.jhdl.util.gui with parameters of type Cell | |
void |
SelectedCellList.insert(Cell c)
|
| Uses of Cell in byucc.jhdl.Xilinx |
| Subclasses of Cell in byucc.jhdl.Xilinx | |
class |
BasicMemory
This layer of memory abstraction does what "Memory" used to, except doesn't implement ExternallyUpdateable. |
class |
bufg
The BUFG cell is a global buffer which distributes high-fanout clock signals throughout the device. |
class |
bufgp
The BUFG cell is a global buffer which distributes high-fanout clock signals throughout the device. |
class |
gnd
This class is the GND cell for the Xilinx tools as well as for JHDL simulation. |
class |
Memory
This layer of Memory abstraction extends BasicMemory and simply adds the ExternallyUpdateable interface |
class |
Memory_1
This layer of Memory abstraction extends BasicMemory and simply adds the ExternallyUpdateable interface |
class |
ram_base
A simple wrapper class that provides an implicit clock port for ram's |
class |
ram_prop
Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call. |
class |
ram_prop_1
Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call. |
class |
ram_synch
Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call. |
class |
ram_synch_1
Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call. |
class |
ram_synch_shift
Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call. |
class |
ramd_prop
Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call. |
class |
ramd_prop_1
Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call. |
class |
TESTXilinxLibrary
This class is the self-test controller for the Xilinx library. |
class |
vcc
This class is the VCC cell for the Xilinx tools as well as for JHDL simulation. |
class |
XilinxAnn
Provides a wrapper of the Annotation class for all Xilinx-related annotations. |
class |
XilinxBasicMemoryCL
This is exactly the same as XilinxMemoryCL, but it doesn't have ExternallyUpdateable in it's ancestory. |
class |
XilinxCL
|
class |
XilinxClockDriver
|
class |
XilinxFD
|
class |
XilinxFD_1
|
class |
XilinxLatch
|
class |
XilinxLatch_1
|
class |
XilinxMemoryCL
|
class |
XilinxMemorySynch
|
class |
XilinxMemorySynch_1
|
| Methods in byucc.jhdl.Xilinx with parameters of type Cell | |
void |
TechMapper.checkCellnameCoherency(Cell c)
|
java.awt.Dimension |
TechMapper.checkAllPlacement(Cell c)
|
java.lang.String |
TechMapper.getRLOCFromPlacementInfo(Cell cell)
|
void |
TechMapper.insertPads(Cell top)
Called by the netlister to add I/O pads to all inputs and outputs to the "top" cell. |
protected void |
TechMapper.insertTechMapHints(Cell c)
Adds the hints to the tree - recurses through all cells and puts RLOC properties on placed cells |
void |
TechMapper.netlist(Cell c,
java.lang.String file)
|
void |
TechMapper.netlist(Cell c,
boolean flat,
java.lang.String file)
|
void |
TechMapper.clockDriver(Cell parent,
Wire clock,
java.lang.String schedule,
java.lang.String name)
|
java.lang.String |
TechMapper.getCellName(Cell c)
|
java.lang.String |
TechMapper.getParentCellName(Cell c)
|
java.lang.String |
TechMapper.getUniqueParentName(Cell c)
|
| Constructors in byucc.jhdl.Xilinx with parameters of type Cell | |
Xwire(Cell parent,
int width)
|
|
Xwire(Cell parent,
int width,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
java.lang.String name)
|
|
Xwire(Cell parent,
WireList wl)
|
|
Xwire(Cell parent,
WireList wl,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire[] wa)
|
|
Xwire(Cell parent,
Wire[] wa,
java.lang.String name)
|
|
XTwire(Cell parent,
int width)
Deprecated. Use a regular Xwire |
|
XTwire(Cell parent,
int width,
java.lang.String name)
Deprecated. Use a regular Xwire |
|
| Uses of Cell in byucc.jhdl.Xilinx.demo |
| Subclasses of Cell in byucc.jhdl.Xilinx.demo | |
class |
inc4
|
| Uses of Cell in byucc.jhdl.Xilinx.Virtex |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex | |
class |
and2
This class implements and asynchronous 2-input and gate. |
class |
and2_g
This class implements and asynchronous 2-input and gate. |
class |
and2b1
This class implements and asynchronous 2-input and gate. |
class |
and2b2
This class implements and asynchronous 2-input and gate. |
class |
and3
This class implements and asynchronous 3-input and gate. |
class |
and3_g
This class implements and asynchronous 3-input and gate. |
class |
and3b1
This class implements and asynchronous 3-input and gate. |
class |
and3b2
This class implements and asynchronous 3-input and gate. |
class |
and3b3
This class implements and asynchronous 3-input and gate. |
class |
and4
This class implements and asynchronous 4-input and gate. |
class |
and4_g
This class implements and asynchronous 4-input and gate. |
class |
and4b1
This class implements and asynchronous 4-input and gate. |
class |
and4b2
This class implements and asynchronous 4-input and gate. |
class |
and4b3
This class implements and asynchronous 4-input and gate. |
class |
and4b4
This class implements and asynchronous 4-input and gate. |
class |
and5
This class implements and asynchronous 5-input and gate. |
class |
and6
This class implements and asynchronous 6-input and gate. |
class |
and7
This class implements and asynchronous 7-input and gate. |
class |
and8
This class implements and asynchronous 8-input and gate. |
class |
and9
This class implements and asynchronous 9-input and gate. |
class |
andX_g
|
class |
BlockRam
Deprecated. See byucc.jhdl.Xilinx.Virtex.RAMB4Single and byucc.jhdl.Xilinx.Virtex.RAMB4Dual |
class |
BlockRamView
This class provides the \"storage\" space for the sake of the simulator. |
class |
bscan_virtex
The BSCAN_VIRTEX symbol is used to create internal boundary scan chains in a Virtex or Virtex- E device. |
class |
buf_g
The BUF_G is a generic-width non-inverting buffer cell. |
class |
bufcf
BUFCF is a single fast connect buffer used to connect the outputs of the LUTs and some dedicated logic directly to the input of another LUT. |
class |
bufe
BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple tristate buffers with inputs I, I3 - I0, I7 - I0, and I15 - I0, respectively; outputs O, O3 - O0, O7 - O0, and O15 - O0, respectively; and active-High output enable (E). |
class |
bufg_ann
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
bufge
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
bufgls
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
bufgs
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
buft
BUFT is a 3-state buffer with input I, output O, and active-Low output enable (T). |
class |
buft_g
The BUFT_G is a generic-width tristate buffer cell. |
class |
capture_virtex
CAPTURE_VIRTEX provides user control over when to capture register (flip-flop and latch) information for readback. |
class |
clkdll
CLKDLL is a clock delay locked loop used to minimize clock skew. |
class |
clkdllhf
CLKDLLHF is a high frequency clock delay locked loop used to minimize clock skew. |
class |
d3_8e
The d3_8e class implements an enabled 3:8 decoder. |
class |
fd
D is a single D-type flip-flop with data input (D) and data output (Q). |
class |
fd_1
FD_1 is a single D-type flip-flop with data input (D) and data output (Q). |
class |
fdc
FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q). |
class |
fdc_1
FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q). |
class |
fdc_1_g
Implements an asynchronously clearable register in the XC4000 library. |
class |
fdc_g
Implements an asynchronously clearable register in the XC4000 library. |
class |
fdce
The FDCE is an asynchronously cleared, enabled D-type flip-flop. |
class |
fdce_1
FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs, and data output (Q). |
class |
fdce_g
The FDCE_G is a generic-width, asynchronously cleared, enabled D-type flip-flop. |
class |
fdcp
FDCP is a single D-type flip-flop with data (D), asynchronous set (PRE), and asynchronous reset (CLR) inputs and data output (Q). |
class |
fdcp_1
FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q). |
class |
fdcpe
FDRSE is a single D-type flip-flop with synchronous reset (CLR), synchronous set (PRE), and clock enable (CE) inputs and data output (Q). |
class |
fdcpe_1
FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). |
class |
fde
FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q). |
class |
fde_1
FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q). |
class |
fdp
FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). |
class |
fdp_1
FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). |
class |
fdp_1_g
Implements an asynchronously settable register in the XC4000 library. |
class |
fdp_g
Implements an asynchronously settable register in the XC4000 library. |
class |
fdpe
The FDPE is an asynchronously preset, enabled D-type flip-flop. |
class |
fdpe_1
FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). |
class |
fdpe_g
The FDCE_P is a generic-width, asynchronously preset, enabled D-type flip-flop. |
class |
fdr
FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). |
class |
fdr_1
FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). |
class |
fdr_1_g
FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). |
class |
fdr_g
FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). |
class |
fdre
FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). |
class |
fdre_1
FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). |
class |
fdre_1_g
FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). |
class |
fdre_g
FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). |
class |
fdrs
FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). |
class |
fdrs_1
FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). |
class |
fdrs_1_g
FDRS_1 is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). |
class |
fdrs_g
FDRS is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). |
class |
fdrse
FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). |
class |
fdrse_1
FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). |
class |
fdrse_1_g
FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). |
class |
fdrse_g
FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). |
class |
fds
FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). |
class |
fds_1
FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). |
class |
fds_1_g
FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). |
class |
fds_g
FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). |
class |
fdse
FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). |
class |
fdse_1
FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). |
class |
fdse_1_g
FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). |
class |
fdse_g
FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). |
class |
fmap
The FMAP symbol is used to control logic partitioning into XC4000 family 4-input function generators. |
class |
fmap_g
The fmap_g is a generic_width and generic port count wrapper for all XC4000 techmapper specific cells. |
class |
ibuf
IBUF is a single input buffer. |
class |
ibuf_agp
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_ann
IBUF is a single input buffer. |
class |
ibuf_ctt
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_g
IBUF is a single input buffer. |
class |
ibuf_gtl
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_gtlp
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_hstl_i
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_hstl_iii
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_hstl_iv
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_lvcmos2
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_pci33_3
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_pci33_5
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_pci66_3
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_sstl2_i
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_sstl2_ii
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_sstl3_i
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibuf_sstl3_ii
For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. |
class |
ibufg
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_agp
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_ctt
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_gtl
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_gtlp
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_hstl_i
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_hstl_iii
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_hstl_iv
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_lvcmos2
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_pci33_3
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_pci33_5
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_pci66_3
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_sstl2_i
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_sstl2_ii
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_sstl3_i
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufg_sstl3_ii
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ifd
The IFD D-type flip-flop is contained in an input/output block (IOB). |
class |
ifd_1
The IFD_1 D-type flip-flop is contained in an input/output block (IOB) except for XC5200. |
class |
ifdi
The IFDI D-type flip-flop is contained in an input/output block (IOB). |
class |
ifdi_1
The IFDI_1 D-type flip-flop is contained in an input/output block (IOB). |
class |
ifdx
The IFDX D-type flip-flop is contained in an input/output block (IOB). |
class |
ifdxi
The IFDXI D-type flip-flop is contained in an input/output block (IOB). |
class |
ildx_1
ILDX_1 is a transparent data latch, which can be used to hold transient data entering a chip. |
class |
ildxi_1
ILDXI_1 is a transparent data latch, which can hold transient data entering a chip. |
class |
inv
The INV cell is an asynchronous inverter. |
class |
inv_g
The INV_G is a generic-width inverter cell. |
class |
iobuf
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_agp
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_ctt
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_f_12
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_f_16
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_f_2
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_f_24
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_f_4
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_f_6
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_f_8
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_gtl
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_gtlp
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_hstl_i
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_hstl_iii
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_hstl_iv
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_lvcmos2
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_pci33_3
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_pci33_5
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_pci66_3
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_s_12
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_s_16
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_s_2
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_s_24
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_s_4
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_s_6
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_s_8
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_sstl2_i
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_sstl2_ii
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_sstl3_i
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobuf_sstl3_ii
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iopad
Deprecated. iopads are not necessary. All that is necessary is an ibuf, and an obuft, with the input wire assigned to the perscribed pin. |
class |
ipad
Deprecated. ipads are not necessary. All that is necessary is an ibuf, with the input wire assigned to the perscribed pin. |
class |
ipad_sim
Deprecated. ipads are not necessary. All that is necessary is an ibuf, with the input wire assigned to the perscribed pin. |
class |
keeper
|
class |
ld
LD is a transparent data latch. |
class |
ld_1
LD_1 is a transparent data latch with an inverted gate. |
class |
ldc
LDC is a transparent data latch with asynchronous clear. |
class |
ldc_1
LDC_1 is a transparent data latch with asynchronous clear and inverted gate. |
class |
ldce
LDCE is a transparent data latch with asynchronous clear and gate enable. |
class |
ldce_1
LDCE_1 is a transparent data latch with asynchronous clear, gate enable, and inverted gate. |
class |
ldcp
LDCP is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs. |
class |
ldcp_1
LDCP_1 is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs. |
class |
ldcpe
LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), and gate enable (GE). |
class |
ldcpe_1
LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), and gate enable (GE). |
class |
lde
LDE is a transparent data latch with data (D) and gate enable (GE) inputs. |
class |
lde_1
LDE_1 is a transparent data latch with data (D) and gate enable (GE) inputs. |
class |
ldp
LDP is a transparent data latch with asynchronous preset (PRE). |
class |
ldp_1
LDP_1 is a transparent data latch with asynchronous preset (PRE). |
class |
ldpe
LDPE is a transparent data latch with asynchronous preset and gate enable. |
class |
ldpe_1
LDPE_1 is a transparent data latch with asynchronous preset, gate enable, and inverted gated. |
class |
lut1
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O). |
class |
lut1_d
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO. |
class |
lut1_l
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer. |
class |
lut2
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O). |
class |
lut2_d
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO. |
class |
lut2_l
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer. |
class |
lut3
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O). |
class |
lut3_d
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO. |
class |
lut3_l
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer. |
class |
lut4
LUT4 is a 4-bit look-up-table (LUT) with general output (O). |
class |
lut4_d
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO. |
class |
lut4_l
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer. |
class |
m2_1
The M2_1 multiplexer chooses one data bit from two sources (D1 or D0) under the control of the select input (S0). |
class |
m2_1_g
The M2_1 multiplexer is a generic-width 2:1 multiplexer. |
class |
mult_and
MULT_AND is an AND component used exclusively for building fast and smaller multipliers. |
class |
muxcy
MUXCY is used to implement a 1-bit high-speed carry propagate function. |
class |
muxcy_d
MUXCY_D is used to implement a 1-bit high-speed carry propagate function. |
class |
muxcy_l
MUXCY_L is used to implement a 1-bit high-speed carry propagate function. |
class |
muxf5
MUXF5 provides a multiplexer function in one half of a Virtex CLB for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables. |
class |
muxf5_d
MUXF5_D provides a multiplexer function in one half of a Virtex or Spartan2 CLB for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables. |
class |
muxf5_l
MUXF5_L provides a multiplexer function in one half of a Virtex or Spartan2 CLB for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables. |
class |
muxf6
MUXF6 provides a multiplexer function in a full Virtex CLB for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s. |
class |
muxf6_d
MUXF6_D provides a multiplexer function in a full Virtex or Spartan2 CLB for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s. |
class |
muxf6_l
MUXF6_L provides a multiplexer function in a full Virtex or Spartan2 CLB for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s. |
class |
nand2
This class implements and asynchronous 2-input nand gate. |
class |
nand2_g
This class implements and asynchronous 2-input nand gate. |
class |
nand2b1
This class implements and asynchronous 2-input nand gate. |
class |
nand2b2
This class implements and asynchronous 2-input nand gate. |
class |
nand3
This class implements and asynchronous 3-input nand gate. |
class |
nand3_g
This class implements and asynchronous 3-input nand gate. |
class |
nand3b1
This class implements and asynchronous 3-input nand gate. |
class |
nand3b2
This class implements and asynchronous 3-input nand gate. |
class |
nand3b3
This class implements and asynchronous 3-input nand gate. |
class |
nand4
This class implements and asynchronous 4-input nand gate. |
class |
nand4_g
This class implements and asynchronous 4-input nand gate. |
class |
nand4b1
This class implements and asynchronous 4-input nand gate. |
class |
nand4b2
This class implements and asynchronous 4-input nand gate. |
class |
nand4b3
This class implements and asynchronous 4-input nand gate. |
class |
nand4b4
This class implements and asynchronous 4-input nand gate. |
class |
nand5
This class implements and asynchronous 5-input nand gate. |
class |
nand6
This class implements and asynchronous 6-input nand gate. |
class |
nand7
This class implements and asynchronous 7-input nand gate. |
class |
nand8
This class implements and asynchronous 8-input nand gate. |
class |
nand9
This class implements and asynchronous 9-input nand gate. |
class |
nandX_g
|
class |
nor2
This class implements and asynchronous 2-input nor gate. |
class |
nor2_g
This class implements and asynchronous 2-input nor gate. |
class |
nor2b1
This class implements and asynchronous 2-input nor gate. |
class |
nor2b2
This class implements and asynchronous 2-input nor gate. |
class |
nor3
This class implements and asynchronous 3-input nor gate. |
class |
nor3_g
This class implements and asynchronous 3-input nor gate. |
class |
nor3b1
This class implements and asynchronous 3-input nor gate. |
class |
nor3b2
This class implements and asynchronous 3-input nor gate. |
class |
nor3b3
This class implements and asynchronous 3-input nor gate. |
class |
nor4
This class implements and asynchronous 4-input nor gate. |
class |
nor4_g
This class implements and asynchronous 4-input nor gate. |
class |
nor4b1
This class implements and asynchronous 4-input nor gate. |
class |
nor4b2
This class implements and asynchronous 4-input nor gate. |
class |
nor4b3
This class implements and asynchronous 4-input nor gate. |
class |
nor4b4
This class implements and asynchronous 4-input nor gate. |
class |
nor5
This class implements and asynchronous 5-input nor gate. |
class |
nor6
This class implements and asynchronous 6-input nor gate. |
class |
nor7
This class implements and asynchronous 7-input nor gate. |
class |
nor8
This class implements and asynchronous 8-input nor gate. |
class |
nor9
This class implements and asynchronous 9-input nor gate. |
class |
norX_g
|
class |
obuf
OBUF is a single output buffer. |
class |
obuf_agp
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_ann
OBUF is a single output buffer. |
class |
obuf_ctt
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_f_12
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_f_16
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_f_2
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_f_24
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_f_4
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_f_6
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_f_8
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_g
OBUF is a single output buffer. |
class |
obuf_gtl
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_gtlp
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_hstl_i
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_hstl_iii
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_hstl_iv
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_lvcmos2
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_pci33_3
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_pci33_5
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_pci66_3
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_s_12
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_s_16
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_s_2
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_s_24
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_s_4
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_s_6
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_s_8
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_sstl2_i
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_sstl2_ii
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_sstl3_i
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_sstl3_ii
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuft
OBUFT is a single 3-state output buffer with active-low enable. |
class |
obuft_agp
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_ctt
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_f_12
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_f_16
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_f_2
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_f_24
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_f_4
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_f_6
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_f_8
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_g
OBUFT is a single 3-state output buffer with active-low enable. |
class |
obuft_gtl
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_gtlp
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_hstl_i
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_hstl_iii
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_hstl_iv
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_lvcmos2
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_pci33_3
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_pci33_5
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_pci66_3
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_s_12
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_s_16
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_s_2
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_s_24
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_s_4
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_s_6
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_s_8
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_sstl2_i
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_sstl2_ii
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_sstl3_i
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuft_sstl3_ii
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
ofd
OFD, OFD4, OFD8, and OFD16 are single and multiple output D flip-flops except for XC5200 and XC9000. |
class |
ofde
OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops whose outputs are enabled by tristate buffers. |
class |
ofdi
OFDI is contained in an input/output block (IOB). |
class |
ofdt
OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers. |
class |
ofdtx
OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers. |
class |
ofdtxi
OFDTXI and its output buffer are contained in an input/output block (IOB). |
class |
ofdx
OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops. |
class |
ofdxi
OFDXI is contained in an input/output block (IOB). |
class |
opad
Deprecated. ipads are not necessary. All that is necessary is an obuf, with the input wire assigned to the perscribed pin. |
class |
opad_sim
Deprecated. ipads are not necessary. All that is necessary is an obuf, with the input wire assigned to the perscribed pin. |
class |
or2
This class implements and asynchronous 2-input or gate. |
class |
or2_g
This class implements and asynchronous 2-input or gate. |
class |
or2b1
This class implements and asynchronous 2-input or gate. |
class |
or2b2
This class implements and asynchronous 2-input or gate. |
class |
or3
This class implements and asynchronous 3-input or gate. |
class |
or3_g
This class implements and asynchronous 3-input or gate. |
class |
or3b1
This class implements and asynchronous 3-input or gate. |
class |
or3b2
This class implements and asynchronous 3-input or gate. |
class |
or3b3
This class implements and asynchronous 3-input or gate. |
class |
or4
This class implements and asynchronous 4-input or gate. |
class |
or4_g
This class implements and asynchronous 4-input or gate. |
class |
or4b1
This class implements and asynchronous 4-input or gate. |
class |
or4b2
This class implements and asynchronous 4-input or gate. |
class |
or4b3
This class implements and asynchronous 4-input or gate. |
class |
or4b4
This class implements and asynchronous 4-input or gate. |
class |
or5
This class implements and asynchronous 5-input or gate. |
class |
or6
This class implements and asynchronous 6-input or gate. |
class |
or7
This class implements and asynchronous 7-input or gate. |
class |
or8
This class implements and asynchronous 8-input or gate. |
class |
or9
This class implements and asynchronous 9-input or gate. |
class |
orX_g
|
class |
pulldown
PULLDOWN resistor elements are available in each XC4000 Input/Output Block (IOB). |
class |
pulldown_g
The PULLDOWN_G is a generic-width pulldown resistor cell. |
class |
pullup
The pull-up element establishes a High logic level for open-drain elements and macros (DECODE, WAND, WORAND) or 3-state nodes (TBUF) when all the drivers are off. |
class |
pullup_g
The PULLUP_G is a generic-width pullup resistor cell. |
class |
ram16x1d
RAM16X1D is a 16-word by 1-bit static dual-ported RAM. |
class |
ram16x1d_1
RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock. |
class |
ram16x1s
RAM16X1S is a synchronous 16-word by 1-bit static RAM. |
class |
ram16x1s_1
RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock. |
class |
ram16x2d
RAM16X2D is a 16-word by 2-bit static dual-ported RAM. |
class |
ram16x2s
RAM16X2S is a synchronous 16-word by 2-bit static RAM. |
class |
ram16x4d
RAM16X4D is a 16-word by 4-bit static dual-ported RAM. |
class |
ram16x4s
RAM16X4S is a synchronous 16-word by 4-bit static RAM. |
class |
ram16x8d
RAM16X8D is a 16-word by 8-bit static dual-ported RAM. |
class |
ram16x8s
RAM16X8S is a synchronous 16-word by 8-bit static RAM. |
class |
ram32x1s
RAM32X1S is a synchronous 32-word by 1-bit static RAM. |
class |
ram32x1s_1
RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability. |
class |
ram32x1s_ack
|
class |
ram32x2s
RAM32X2S is a synchronous 32-word by 2-bit static RAM. |
class |
ram32x4s
RAM32X4S is a synchronous 32-word by 4-bit static RAM. |
class |
ram32x8s
RAM32X8S is a synchronous 32-word by 8-bit static RAM. |
(package private) class |
byucc.jhdl.Xilinx.Virtex.RAMB4
This class provides the functionality of the RAMB4 Virtex library elements. |
class |
RAMB4Dual
This class provides the functionality of the RAMB4_Sn_Sn Virtex library elements. |
class |
RAMB4Dual_rb
|
class |
RAMB4Single
This class provides the functionality of the RAMB4_Sn Virtex library elements. |
class |
RAMB4Single_rb
|
class |
rom16x1
ROM16X1 is a 16-word by 1-bit ROM. |
class |
rom32x1
ROM32X1 is a 32-word by 1-bit ROM. |
class |
SimulationBuffer
|
class |
srl16
SRL16 is a shift register look up table (LUT). |
class |
srl16_1
SRL16_1 is a shift register look up table (LUT). |
class |
srl16e
SRL16E is a shift register look up table (LUT). |
class |
srl16e_1
SRL16E_1 is a shift register look up table (LUT). |
class |
startup_virtex
The STARTUP_VIRTEX primitive is used for Global Set/Reset, global 3-state control, and the user configuration clock. |
class |
tb_BlockRam
This class is used by the development team to test the block ram's. |
class |
TESTVirtexLibrary
This class is the self-test controller for the Virtex library. |
class |
upad
A UPAD allows the use of any unbonded IOBs in a device. |
class |
xnor2
This class implements and asynchronous 2-input xnor gate. |
class |
xnor2_g
This class implements and asynchronous 2-input xnor gate. |
class |
xnor3
This class implements and asynchronous 3-input xnor gate. |
class |
xnor3_g
This class implements and asynchronous 3-input xnor gate. |
class |
xnor4
This class implements and asynchronous 4-input xnor gate. |
class |
xnor4_g
This class implements and asynchronous 4-input xnor gate. |
class |
xnor5
This class implements and asynchronous 5-input xnor gate. |
class |
xnor6
This class implements and asynchronous 6-input xnor gate. |
class |
xnor7
This class implements and asynchronous 7-input xnor gate. |
class |
xnor8
This class implements and asynchronous 8-input xnor gate. |
class |
xnor9
This class implements and asynchronous 9-input xnor gate. |
class |
xor2
This class implements and asynchronous 2-input xor gate. |
class |
xor2_g
This class implements and asynchronous 2-input xor gate. |
class |
xor3
This class implements and asynchronous 3-input xor gate. |
class |
xor3_g
This class implements and asynchronous 3-input xor gate. |
class |
xor4
This class implements and asynchronous 4-input xor gate. |
class |
xor4_g
This class implements and asynchronous 4-input xor gate. |
class |
xor5
This class implements and asynchronous 5-input xor gate. |
class |
xor6
This class implements and asynchronous 6-input xor gate. |
class |
xor7
This class implements and asynchronous 7-input xor gate. |
class |
xor8
This class implements and asynchronous 8-input xor gate. |
class |
xor9
This class implements and asynchronous 9-input xor gate. |
class |
xorcy
XORCY is a special XOR with general O output used for generating faster and smaller arithmetic functions. |
class |
xorcy_d
XORCY_D is a special XOR used for generating faster and smaller arithmetic functions. |
class |
xorcy_l
XORCY_L is a special XOR with general O output used for generating faster and smaller arithmetic functions. |
| Methods in byucc.jhdl.Xilinx.Virtex with parameters of type Cell | |
void |
TMCellList.insert(Cell c)
|
java.lang.String |
VirtexPlacementInfo.getTransformation(Cell c)
|
void |
VirtexTechMapper.padClock(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
VirtexTechMapper.padIn(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
VirtexTechMapper.padInout(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
VirtexTechMapper.padInoutR(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
VirtexTechMapper.padOut(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
VirtexTechMapper.padOutT(Cell parent,
boolean clocked,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
VirtexTechMapper.buf(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.tbuf(Cell parent,
Wire in,
Wire en,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.not(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.vcc(Cell parent,
Wire o,
java.lang.String name)
|
void |
VirtexTechMapper.gnd(Cell parent,
Wire o,
java.lang.String name)
|
void |
VirtexTechMapper.pullup(Cell parent,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.pulldown(Cell parent,
Wire out,
java.lang.String name)
|
Wire |
VirtexTechMapper.wire(Cell p,
java.lang.String name)
|
Wire |
VirtexTechMapper.wire(Cell p,
int width,
java.lang.String name)
|
Wire |
VirtexTechMapper.concat(Cell parent,
Wire[] wa,
java.lang.String name)
|
Wire |
VirtexTechMapper.concat(Cell parent,
WireList wl,
java.lang.String name)
|
Wire |
VirtexTechMapper.range(Cell parent,
Wire src,
int hi,
int lo)
|
void |
VirtexTechMapper.constant(Cell parent,
Wire out,
int value,
java.lang.String name)
|
void |
VirtexTechMapper.constant(Cell parent,
Wire out,
BV value,
java.lang.String name)
|
void |
VirtexTechMapper.mux(Cell parent,
Wire[] d,
Wire sel,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.and(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.or(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.xor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.nand(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.nor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.xnor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.reg(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regc(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regp(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regr(Cell parent,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regre(Cell parent,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regs(Cell parent,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regse(Cell parent,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.reg(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regc(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regp(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regr(Cell parent,
Wire clk,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regs(Cell parent,
Wire clk,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regse(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regre(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regce(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regpe(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regce(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.regpe(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
VirtexTechMapper.add(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
VirtexTechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
VirtexTechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
Wire co,
java.lang.String name)
|
void |
VirtexTechMapper.add(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
VirtexTechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
VirtexTechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
java.lang.String name)
|
Wire |
VirtexTechMapper.ashiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
VirtexTechMapper.shiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
VirtexTechMapper.shiftl(Cell parent,
Wire in,
int shift,
Wire out)
|
java.lang.String |
VirtexTechMapper.getRLOCFromPlacementInfo(Cell c)
|
static Cell |
VirtexTechMapper.getSourceHierarchicalCell(Cell caller,
Wire w)
|
static Cell |
VirtexTechMapper.getSinkHierarchicalCell(Cell caller,
Cell par,
Wire w)
|
Cell |
VirtexTechMapper.getSourcePlaceable(Cell requester,
Wire w)
|
Cell |
VirtexTechMapper.getSourcePlaceableLeaf(Cell requester,
Wire w)
|
Cell |
VirtexTechMapper.getSinkLeafCell(Logic requester,
Cell par,
Wire w)
Deprecated. Returns any arbitrary leaf cell on the sink list of this wire. |
Cell |
VirtexTechMapper.sink(Logic caller,
Wire w1,
Cell c1)
Deprecated. use getSinkLeafCell |
PlacementInfo |
VirtexTechMapper.createPlacementInfo(Cell c)
|
void |
VirtexTechMapper.place(Logic parent,
Cell c1,
int x,
int y,
java.lang.String hints)
|
java.lang.String |
VirtexTechMapper.getTechMapHint(Logic parent,
Cell c)
|
| Constructors in byucc.jhdl.Xilinx.Virtex with parameters of type Cell | |
norX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
Xwire(Cell parent,
int width)
|
|
Xwire(Cell parent,
int width,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
java.lang.String name)
|
|
Xwire(Cell parent,
WireList wl)
|
|
Xwire(Cell parent,
WireList wl,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire[] wa)
|
|
Xwire(Cell parent,
Wire[] wa,
java.lang.String name)
|
|
VirtexPlacementInfo(Cell c)
|
|
VirtexPlacementInfo(Cell c,
int x,
int y)
|
|
nandX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
orX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
andX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
| Uses of Cell in byucc.jhdl.Xilinx.Virtex.helpers |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex.helpers | |
class |
adder
Class used by the TechMapper. |
class |
adderSubtractor
Class used by the TechMapper. |
class |
Subtractor
Class used by the TechMapper. |
class |
tb_adder
Class used by the development team. |
| Uses of Cell in byucc.jhdl.Xilinx.Virtex.Modules |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex.Modules | |
class |
arrayMult
Variable width array multiplier with the option of signed or unsigned multiply and generic pipeline depth. |
class |
booth
General Description |
class |
delay
Generic Delay Line |
class |
downcnt
A generic sized down counter |
class |
DS2Pconv
DS2Pconv.java Created: 3/2002 |
class |
DSMult
DSMult.java Created: 1/2002 |
class |
Equals
Parameterizable module for creating a bit-wise comparator. |
class |
KCMMult
KCMMult.java Created: 12/2000 |
class |
Mux
implements and arbitrary -width and -height mux, optimized to use all of the Virtex internal mux primitives. |
class |
mux41
Class used by the TechMapper. |
class |
mux81
Class used by the TechMapper. |
class |
P2DSconv
P2DSconv.java Created: 3/2002 |
class |
ParellelDSMult
ParellelDSMult.java Created: 1/2002 |
class |
Priority
Outputs only the most significant '1' of the input. |
class |
PriorityEncoder
encodes the input value, prioritizing the bits by MSB has highest priority. |
class |
ramrom
Generic Ram or Rom generator |
class |
ReversePriorityEncoder
encodes the input value, prioritizing the bits by LSB has highest priority. |
class |
S2Pconv
S2Pconv.java Created: 3/2002 |
class |
Shifter
Class used by the TechMapper. |
class |
srl_array
Deprecated. use SRLArray |
class |
SRLArray
General Description |
class |
SRLFifo
arbitrary-width, arbitrary depth FIFO based on shift registers (SRL16). |
class |
upcnt
General Description |
| Uses of Cell in byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex.Modules.DSMult_Pack | |
class |
MultCell
MultCell.java Created: 1/2002 |
class |
MultRow
MultRow.java Created: 1/2002 |
| Uses of Cell in byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack | |
class |
KCM_ROM
KCM_ROM.java Created: 12/2000 |
class |
KCMRom_Adder
KCMRom_Adder.java This is a complete KCMRom_Adder stage. |
class |
KCMRom_AdderBit
KCMRom_AdderBit.java A single bit of a KCM_ROMAddr. |
class |
tb_VirtexKCMMultiplier
tb_VirtexKCMMultiplier.java Created: 12/2000 |
| Uses of Cell in byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack | |
class |
And_fmap_g
|
class |
EXAMINE_CI_Virtex
|
class |
MultAdd
|
class |
MultAddVirtex
|
class |
multCol
|
class |
MultSub
|
class |
MultSubVirtex
|
| Methods in byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack that return Cell | |
static Cell |
And_fmap_g.and_map(Node parent,
Wire a,
Wire b,
Wire out)
|
| Uses of Cell in byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack | |
class |
RightShiftReg
RightShiftReg.java Created: 3/2002 |
class |
ShiftBit
ShiftBit.java Created: 3/2002 |
| Uses of Cell in byucc.jhdl.Xilinx.Virtex.ramb4_wrapper |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex.ramb4_wrapper | |
class |
RAMB4_Dual
This class provides the functionality of the RAMB4_Sn_Sn Virtex library elements for EDIF parsing only. |
class |
ramb4_s1
This class provides the functionality of the RAMB4_S1 Virtex library element for EDIF netlisting only. |
class |
ramb4_s1_s1
This class provides the functionality of the RAMB4_S1_S1 Virtex library element for EDIF netlisting only. |
class |
ramb4_s1_s16
This class provides the functionality of the RAMB4_S1_S16 Virtex library element for EDIF netlisting only. |
class |
ramb4_s1_s2
This class provides the functionality of the RAMB4_S1_S2 Virtex library element for EDIF netlisting only. |
class |
ramb4_s1_s4
This class provides the functionality of the RAMB4_S1_S4 Virtex library element for EDIF netlisting only. |
class |
ramb4_s1_s8
This class provides the functionality of the RAMB4_S1_S8 Virtex library element for EDIF netlisting only. |
class |
ramb4_s16
This class provides the functionality of the RAMB4_S16 Virtex library element for EDIF netlisting only. |
class |
ramb4_s16_s16
This class provides the functionality of the RAMB4_S16_S16 Virtex library element for EDIF netlisting only. |
class |
ramb4_s2
This class provides the functionality of the RAMB4_S2 Virtex library element for EDIF netlisting only. |
class |
ramb4_s2_s16
This class provides the functionality of the RAMB4_S2_S16 Virtex library element for EDIF netlisting only. |
class |
ramb4_s2_s2
This class provides the functionality of the RAMB4_S2_S2 Virtex library element for EDIF netlisting only. |
class |
ramb4_s2_s4
This class provides the functionality of the RAMB4_S2_S4 Virtex library element for EDIF netlisting only. |
class |
ramb4_s2_s8
This class provides the functionality of the RAMB4_S2_S8 Virtex library element for EDIF netlisting only. |
class |
ramb4_s4
This class provides the functionality of the RAMB4_S4 Virtex library element for EDIF netlisting only. |
class |
ramb4_s4_s16
This class provides the functionality of the RAMB4_S4_S16 Virtex library element for EDIF netlisting only. |
class |
ramb4_s4_s4
This class provides the functionality of the RAMB4_S4_S4 Virtex library element for EDIF netlisting only. |
class |
ramb4_s4_s8
This class provides the functionality of the RAMB4_S4_S8 Virtex library element for EDIF netlisting only. |
class |
ramb4_s8
This class provides the functionality of the RAMB4_S8 Virtex library element for EDIF netlisting only. |
class |
ramb4_s8_s16
This class provides the functionality of the RAMB4_S8_S16 Virtex library element for EDIF netlisting only. |
class |
ramb4_s8_s8
This class provides the functionality of the RAMB4_S8_S8 Virtex library element for EDIF netlisting only. |
class |
RAMB4_Single
This class provides the functionality of the RAMB4_Sn Virtex library elements for EDIF parsing only. |
| Uses of Cell in byucc.jhdl.Xilinx.Virtex2 |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex2 | |
class |
BlockRamViewParity
Deprecated. Use BlockRamView in RamPack instead. |
class |
bscan_virtex2
The BSCAN_VIRTEX2 symbol is used to create internal boundary scan chains in a Virtex2 or Virtex2- E device. |
class |
bufgce
BUFGCE is a multiplexed global clock buffer with a single gated input. |
class |
bufgce_1
BUFGCE_1 is a multiplexed global clock buffer with a single gated input. |
class |
bufgdll
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
bufgmux
BUFGMUX is a multiplexed global clock buffer that can select between two input clocks I0 and I1. |
class |
bufgmux_1
BUFGMUX_1 is a multiplexed global clock buffer that can select between two input clocks I0 and I1. |
class |
capture_virtex2
CAPTURE_VIRTEX2 provides user control over when to capture register (flip-flop and latch) information for readback. |
class |
dcm
DCM is a digital clock manager that provides multiple functions. |
class |
fddrcpe
FDDRCPE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1). |
class |
fddrrse
FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1). |
class |
ibuf_lvttl
IBUF is a single input buffer. |
class |
ibufds
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_blvds_25
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_diff_out
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_ldt_25
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvds_25
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvds_25_dci
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvds_33
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvds_33_dci
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvdsext_25
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvdsext_25_dci
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvdsext_33
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvdsext_33_dci
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvpecl_25
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_lvpecl_33
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufds_ulvds_25
IBUFDS is an input buffer that supports low-voltage, differential signaling. |
class |
ibufg_lvttl
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. |
class |
ibufgds
IBUFGDS is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or DCM. |
class |
ibufgds_lvds_25
IBUFGDS is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or DCM. |
class |
ibufgds_lvdsext_25
IBUFGDS is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or DCM. |
class |
icap_virtex2
|
class |
ifddrcpe
IFDDRCPE is a dual data rate (DDR) input D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR). |
class |
ifddrrse
FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1). |
class |
iobuf_sstl2_ii_dci
IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. |
class |
iobufds
|
class |
mult18x18
MULT18X18 is a combinational signed 18-bit by 18-bit multiplier. |
class |
mult18x18s
MULT18X18S is a signed 18-bit by 18-bit multiplier with output registered. |
class |
muxf7
MUXF7 provides a multiplexer function in a full Virtex-II CLB for creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables. |
class |
muxf7_d
MUXF7_D provides a multiplexer function in one full Virtex-II CLB for creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables. |
class |
muxf7_l
MUXF7_L provides a multiplexer function in a full Virtex-II CLB for creating a func-tion- of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables. |
class |
muxf8
MUXF8 provides a multiplexer function in two full Virtex-II CLBs for creating a func-tion- of-7 lookup table or a 32-to-1 multiplexer in combination with the associated lookup tables and two MUXF8s. |
class |
muxf8_d
MUXF8_D provides a multiplexer function in two full Virtex-II CLBs for creating a function-of-8 lookup table or a 32-to-1 multiplexer in combination with the associated four lookup tables and two MUXF8s. |
class |
muxf8_l
MUXF8_L provides a multiplexer function in two full Virtex-II CLBs for creating a function-of-8 lookup table or a 32-to-1 multiplexer in combination with the associated four lookup tables and two MUXF8s. |
class |
obuf_lvttl_f_12
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obuf_sstl2_i_dci
OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard. |
class |
obufds
OBUFDS is a single output buffer that supports low-voltage, differential signaling (1.8v CMOS). |
class |
obufds_lvds_25
OBUFDS is a single output buffer that supports low-voltage, differential signaling (1.8v CMOS). |
class |
obufds_lvdsext_25
OBUFDS is a single output buffer that supports low-voltage, differential signaling (1.8v CMOS). |
class |
obuft_sstl2_i_dci
OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. |
class |
obuftds
OBUFTDS is a single 3-state, differential signaling output buffer with active Low enable and a selectIO interface. |
class |
ofddrcpe
OFDDRCPE is a dual data rate (DDR) output D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR). |
class |
ofddrrse
OFDDRRSE is a dual data rate (DDR) output D flip-flop with synchronous reset (R) and set (S) and clock enable (CE). |
class |
ofddrtcpe
OFDDRTCPE is a dual data rate (DDR) D flip-flop with clock enable (CE) and asynchronous preset and clear whose output is enabled by a 3-state buffer. |
class |
ofddrtrse
OFDDRTRSE is a dual data rate (DDR) D flip-flop with clock enable (CE) and synchronous reset and set whose output is enabled by a 3-state buffer. |
class |
orcy
ORCY is a special OR with general O output used for generating faster and smaller arithmetic functions. |
class |
ram128x1s
RAM128X1S is a 128-word by 1-bit static random access memory with synchronous write capability. |
class |
ram128x1s_1
RAM128X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability. |
class |
ram32x1d
RAM32X1D is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock. |
class |
ram32x1d_1
RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock. |
class |
ram64x1d
RAM64X1D is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock. |
class |
ram64x1d_1
RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock. |
class |
ram64x1s
RAM64X1S is a 64-word by 1-bit static random access memory with synchronous write capability. |
class |
ram64x1s_1
RAM64X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability and a negative-edge clock. |
class |
ram64x2s
RAM64X2S is a 64-word by 2-bit static random access memory with synchronous write capability. |
class |
RAMB16_S
This class provides the functionality of the RAMB16_Sn Virtex2 library elements - The Single-ported BlockRams. |
class |
RAMB16_S_S
This class provides the functionality of the RAMB16_Sn_Sn Virtex2 library elements - The Dual-ported BlockRams. |
class |
RAMB16DualNoParity
Deprecated. Use RAMB16_S_S instead. |
class |
RAMB16DualParity
Deprecated. Use RAMB16_S_S instead. |
class |
RAMB16DualParityB
Deprecated. Use RAMB16_S_S instead. |
class |
RAMB16SingleNoParity
Deprecated. Use RAMB16_S instead. |
class |
RAMB16SingleParity
Deprecated. Use RAMB16_S instead. |
class |
roc
|
class |
rocbuf
|
class |
rom128x1
ROM128X1 is a 128-word by 1-bit ROM. |
class |
Rom128x1View
This class is for the simulation of block ram's to work correctly. |
class |
rom256x1
ROM256X1 is a 256-word by 1-bit ROM. |
class |
Rom256x1View
This class is for the simulation of block ram's to work correctly. |
class |
rom64x1
ROM64X1 is a 64-word by 1-bit ROM. |
class |
Rom64x1View
This class is for the simulation of block ram's to work correctly. |
class |
srlc16
SRLC16 is a shift register look up table (LUT). |
class |
srlc16_1
SRLC16_1 is a shift register look up table (LUT). |
class |
srlc16e
SRLC16E is a shift register look up table (LUT) with carry, clock enable, and asynchro-nous clear. |
class |
srlc16e_1
SRLC16E_1 is a shift register look up table (LUT). |
class |
startbuf_architecture
|
class |
startup_virtex2
The STARTUP_VIRTEX2 primitive is used for Global Set/Reset, global 3-state control, and the user configuration clock. |
class |
TESTVirtex2Library
This class is the self-test controller for the Virtex2 library. |
class |
toc
|
class |
tocbuf
|
class |
Virtex2LibrarySelfTester
This class is the self-test controller for the Virtex2 library. |
| Methods in byucc.jhdl.Xilinx.Virtex2 with parameters of type Cell | |
java.lang.String |
Virtex2PlacementInfo.getTransformation(Cell c)
|
void |
Virtex2TechMapper.padClock(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.padClockR(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.padIn(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.padInR(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.padInout(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.padInoutR(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.padOut(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.padOutR(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.padOutT(Cell parent,
boolean clocked,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
Virtex2TechMapper.buf(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.tbuf(Cell parent,
Wire in,
Wire en,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.not(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.vcc(Cell parent,
Wire o,
java.lang.String name)
|
void |
Virtex2TechMapper.gnd(Cell parent,
Wire o,
java.lang.String name)
|
void |
Virtex2TechMapper.pullup(Cell parent,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.pulldown(Cell parent,
Wire out,
java.lang.String name)
|
Wire |
Virtex2TechMapper.wire(Cell p,
java.lang.String name)
|
Wire |
Virtex2TechMapper.wire(Cell p,
int width,
java.lang.String name)
|
Wire |
Virtex2TechMapper.concat(Cell parent,
Wire[] wa,
java.lang.String name)
|
Wire |
Virtex2TechMapper.concat(Cell parent,
WireList wl,
java.lang.String name)
|
Wire |
Virtex2TechMapper.range(Cell parent,
Wire src,
int hi,
int lo)
|
void |
Virtex2TechMapper.constant(Cell parent,
Wire out,
int value,
java.lang.String name)
|
void |
Virtex2TechMapper.constant(Cell parent,
Wire out,
BV value,
java.lang.String name)
|
void |
Virtex2TechMapper.mux(Cell parent,
Wire[] d,
Wire sel,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.and(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.or(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.xor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.nand(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.nor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.xnor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.reg(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regc(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regp(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regr(Cell parent,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regre(Cell parent,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regs(Cell parent,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regse(Cell parent,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.reg(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regc(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regp(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regr(Cell parent,
Wire clk,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regs(Cell parent,
Wire clk,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regse(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regre(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regce(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regpe(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regce(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.regpe(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
Virtex2TechMapper.add(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
Virtex2TechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
Virtex2TechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
Wire co,
java.lang.String name)
|
void |
Virtex2TechMapper.add(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
Virtex2TechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
Virtex2TechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
java.lang.String name)
|
Wire |
Virtex2TechMapper.ashiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
Virtex2TechMapper.shiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
Virtex2TechMapper.shiftl(Cell parent,
Wire in,
int shift,
Wire out)
|
java.lang.String |
Virtex2TechMapper.getRLOCFromPlacementInfo(Cell c)
|
static Cell |
Virtex2TechMapper.getSourceHierarchicalCell(Cell caller,
Wire w)
|
static Cell |
Virtex2TechMapper.getSinkHierarchicalCell(Cell caller,
Cell par,
Wire w)
|
Cell |
Virtex2TechMapper.getSourcePlaceable(Cell requester,
Wire w)
|
Cell |
Virtex2TechMapper.getSourcePlaceableLeaf(Cell requester,
Wire w)
|
Cell |
Virtex2TechMapper.getSinkLeafCell(Logic requester,
Cell par,
Wire w)
Deprecated. Returns any arbitrary leaf cell on the sink list of this wire. |
Cell |
Virtex2TechMapper.sink(Logic caller,
Wire w1,
Cell c1)
Deprecated. use getSinkLeafCell |
PlacementInfo |
Virtex2TechMapper.createPlacementInfo(Cell c)
|
void |
Virtex2TechMapper.place(Logic parent,
Cell c1,
int x,
int y,
java.lang.String hints)
Add placement hints. |
java.lang.String |
Virtex2TechMapper.getTechMapHint(Logic parent,
Cell c)
|
void |
TMCellList.insert(Cell c)
|
| Constructors in byucc.jhdl.Xilinx.Virtex2 with parameters of type Cell | |
Virtex2PlacementInfo(Cell c)
|
|
Virtex2PlacementInfo(Cell c,
int x,
int y)
|
|
andX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
nandX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
norX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
Xwire(Cell parent,
int width)
|
|
Xwire(Cell parent,
int width,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
java.lang.String name)
|
|
Xwire(Cell parent,
WireList wl)
|
|
Xwire(Cell parent,
WireList wl,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire[] wa)
|
|
Xwire(Cell parent,
Wire[] wa,
java.lang.String name)
|
|
orX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
| Uses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules | |
class |
EmbeddedMultiplier
Constructs an arbitrary-width unsigned multiplier using Virtex2 embedded multipliers. |
class |
MultiplierBlock
Basic block for constructing a parameterizeable multiplier based on the Virtex 2 architecture's 18x18 embedded multipliers. |
class |
MultiplierBlockSigned
Basic block for constructing a parameterizeable multiplier based on the Virtex 2 architecture's 18x18 embedded multipliers. |
| Uses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint | |
class |
FPAddSub
General Description |
class |
FPDivide
Floating-point divider. |
class |
FPMult
Floating-point multiplier. |
| Uses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack | |
class |
BarrelShiftL
|
class |
BarrelShiftR
|
class |
FP_ALU
|
class |
FPExponentMatch
|
class |
Maximum
|
class |
Normalize
|
class |
NormalizePE
|
class |
Round
|
class |
ShifterTable
|
class |
TestOverflow
|
| Uses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack | |
class |
DelayS
Generic Delay Line |
class |
FPMantissaDivide
|
class |
LookupTableBlockRAM
|
| Uses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack | |
class |
EXAMINE_CI_Virtex2
|
class |
MultAddVirtex2
|
class |
MultSubVirtex2
|
| Methods in byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack that return Cell | |
static Cell |
And_fmap_g.and_map(Node parent,
Wire a,
Wire b,
Wire out)
|
| Uses of Cell in byucc.jhdl.Xilinx.Virtex2.RamPack |
| Subclasses of Cell in byucc.jhdl.Xilinx.Virtex2.RamPack | |
class |
BlockRamViewL
This class is for the simulation of block ram's to work correctly. |
class |
RAMB16
This class provides the functionality of the RAMB16 Virtex2 library elements. |
| Uses of Cell in byucc.jhdl.Xilinx.XC4000 |
| Subclasses of Cell in byucc.jhdl.Xilinx.XC4000 | |
class |
bscan
The BSCAN symbol indicates that boundary scan logic should be enabled after the programmable logic device (PLD) configuration is complete. |
class |
buffclk
BUFFCLK (FastCLK buffer) provides the fastest way to bring a clock into the XC4000X device. |
class |
bufge_ann
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
bufgls_ann
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
bufgp_ann
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
bufgs_ann
Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e. |
class |
cy4
This class implements the carry modes for the XC4000 architecture. |
class |
cy4_mode
The cy4_mode block is the Annotation wrapper to indicate the exact carry function being implemented to the back end Xilinx tools. |
class |
hmap
The HMAP symbol is used to control logic partitioning into XC4000 family 3-input H funciton generators. |
class |
ilffx
ILFFX, an optional latch that drives the input flip-flop, allows the very fast capture of input data. |
class |
ilffxi
ILFFXI, an optional latch that drives the input flip-flop, allows the very fast capture of input data. |
class |
ilflx_1
ILFLX_1, an optional latch that drives the input latch, allows the very fast capture of input data. |
class |
ilflxi_1
ILFLXI_1, an optional latch that drives the input latch, allows the very fast capture of input data. |
class |
md0
The MD0 input pad is connected to the Mode 0 (MO) input pin, which is used to determine the configuration mode on an XC4000 device. |
class |
md1
The MD1 input pad is connected to the Mode 1 (M1) input pin, which is used to determine the configuration mode on an XC4000 device. |
class |
md2
The MD2 input pad is connected to the Mode 2 (M2) input pin, which is used to determine the configuration mode on an XC4000 device. |
class |
oand2
OAND2 is a 2-input AND gate that is implemented in the output multiplexer of the XC4000X IOB. |
class |
omux2
The OMUX2 multiplexer chooses one data bit from two sources (D1 or D0) under the control of the select input (S0). |
class |
onand2
ONAND2 is a 2-input NAND gate that is implemented in the output multiplexer of the XC4000X IOB. |
class |
onor2
ONOR2 is a 2-input NOR gate that is implemented in the output multiplexer of the XC4000X IOB. |
class |
oor2
OOR2 is a 2-input OR gate that is implemented in the output multiplexer of the XC4000X IOB. |
class |
oxnor2
OXNOR2 is a 2-input exclusive NOR gate that is implemented in the output multiplexer of the XC4000X and SpartanXL IOB. |
class |
oxor2
OXOR2 is a 2-input exclusive OR gate that is implemented in the output multiplexer of the XC4000X IOB. |
class |
ram16x1
RAM16X1 is a 16-word by 1-bit static RAM. |
class |
ram32x1
RAM32X1 is a 32-word by 1-bit static RAM. |
class |
startup
The STARTUP symbol is used for initializing the Global Set/Reset, global 3-state control, and the user configuration clock. |
class |
tb_andX
|
class |
tck
The TCK input pad is connected to the boundary scan test clock, which shifts the serial data and instructions into and out of the boundary scan data registers. |
class |
tdi
The TDI input pad is connected to the boundary scan TDI input. |
class |
tdo
The TDO data output pad is connected to the boundary scan TDO output. |
class |
TESTXC4000Library
This class is the self-test controller for the XC4000 library. |
class |
tms
The TMS input pad is connected to the boundary scan TMS input. |
class |
wand
WAND1, WAND4, WAND8, and WAND16 are single and multiple open-drain buffers. |
class |
wor2and
WOR2AND is a 2-input (I1 and I2) OR gate/buffer with an open-drain output (O). |
| Methods in byucc.jhdl.Xilinx.XC4000 that return Cell | |
Cell |
XC4000TechMapper.map(Logic parent,
Wire[] in,
Wire out,
java.lang.String hints)
|
Cell |
XC4000TechMapper.source(Logic parent,
Wire w)
Deprecated. use getSourcePlaceable, getSourcePlaceableLeaf, or getSourceLeafCell |
Cell |
XC4000TechMapper.sink(Logic parent,
Wire w,
Cell c)
Deprecated. use getSinkLeafCell |
Cell |
XC4000TechMapper.getSourcePlaceable(Cell parent,
Wire w)
|
Cell |
XC4000TechMapper.getSourcePlaceableLeaf(Cell parent,
Wire w)
|
Cell |
XC4000TechMapper.getSourceLeafCell(Logic parent,
Wire w)
|
Cell |
XC4000TechMapper.getSinkLeafCell(Logic parent,
Cell c,
Wire w)
|
| Methods in byucc.jhdl.Xilinx.XC4000 with parameters of type Cell | |
void |
XC4000TechMapper.checkCellnameCoherency(Cell c)
|
java.awt.Dimension |
XC4000TechMapper.checkAllPlacement(Cell c)
|
void |
XC4000TechMapper.mux(Cell parent,
Wire[] d,
Wire sel,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.and(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.nand(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.or(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.nor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.xor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.xnor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.reg(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regc(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regp(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.reg(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regc(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regp(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regr(Cell parent,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regre(Cell parent,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regs(Cell parent,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regse(Cell parent,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regr(Cell parent,
Wire clk,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regre(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regs(Cell parent,
Wire clk,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.regse(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
XC4000TechMapper.add(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
XC4000TechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
XC4000TechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
Wire co,
java.lang.String name)
|
void |
XC4000TechMapper.add(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
XC4000TechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
XC4000TechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
java.lang.String name)
|
Wire |
XC4000TechMapper.ashiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
XC4000TechMapper.shiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
XC4000TechMapper.shiftl(Cell parent,
Wire in,
int shift,
Wire out)
|
void |
XC4000TechMapper.rom(Cell parent,
Wire addr,
Wire data,
long[] init,
java.lang.String name)
|
void |
XC4000TechMapper.ram(Cell parent,
Wire din,
Wire we,
Wire addr,
Wire dout,
long[] init,
java.lang.String name)
|
void |
XC4000TechMapper.rams(Cell parent,
Wire din,
Wire we,
Wire addr,
Wire dout,
long[] init,
java.lang.String name)
|
void |
XC4000TechMapper.ramd(Cell parent,
Wire din,
Wire we,
Wire addrA,
Wire addrB,
Wire outA,
Wire outB,
long[] init,
java.lang.String name)
|
java.lang.String |
XC4000TechMapper.getRLOCFromPlacementInfo(Cell c)
|
void |
XC4000TechMapper.place(Logic parent,
Cell c1,
int x,
int y,
java.lang.String hints)
|
Cell |
XC4000TechMapper.sink(Logic parent,
Wire w,
Cell c)
Deprecated. use getSinkLeafCell |
Cell |
XC4000TechMapper.getSourcePlaceable(Cell parent,
Wire w)
|
Cell |
XC4000TechMapper.getSourcePlaceableLeaf(Cell parent,
Wire w)
|
Cell |
XC4000TechMapper.getSinkLeafCell(Logic parent,
Cell c,
Wire w)
|
PlacementInfo |
XC4000TechMapper.createPlacementInfo(Cell c)
|
java.lang.String |
XC4000TechMapper.getTechMapHint(Logic parent,
Cell c)
|
void |
XC4000TechMapper.padIn(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC4000TechMapper.padInR(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC4000TechMapper.padInout(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC4000TechMapper.padInoutR(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC4000TechMapper.padOut(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC4000TechMapper.padOutR(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC4000TechMapper.padOutT(Cell parent,
boolean clocked,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC4000TechMapper.padClock(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
abstract void |
XilinxTechMapper.checkCellnameCoherency(Cell c)
|
abstract java.awt.Dimension |
XilinxTechMapper.checkAllPlacement(Cell c)
|
abstract java.lang.String |
XilinxTechMapper.getRLOCFromPlacementInfo(Cell cell)
|
void |
XilinxTechMapper.buf(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.tbuf(Cell parent,
Wire in,
Wire en,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.not(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.vcc(Cell parent,
Wire o,
java.lang.String name)
|
void |
XilinxTechMapper.gnd(Cell parent,
Wire o,
java.lang.String name)
|
void |
XilinxTechMapper.regce(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.regpe(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.regce(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.regpe(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.pullup(Cell parent,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.pulldown(Cell parent,
Wire out,
java.lang.String name)
|
Wire |
XilinxTechMapper.wire(Cell p,
java.lang.String name)
|
Wire |
XilinxTechMapper.wire(Cell p,
int width,
java.lang.String name)
|
Wire |
XilinxTechMapper.concat(Cell parent,
Wire[] wa,
java.lang.String name)
|
Wire |
XilinxTechMapper.concat(Cell parent,
WireList wl,
java.lang.String name)
|
Wire |
XilinxTechMapper.range(Cell parent,
Wire src,
int hi,
int lo)
|
void |
XilinxTechMapper.constant(Cell parent,
Wire out,
int value,
java.lang.String name)
|
void |
XilinxTechMapper.constant(Cell parent,
Wire out,
long value,
java.lang.String name)
|
void |
XilinxTechMapper.constant(Cell parent,
Wire out,
int[] value,
java.lang.String name)
|
void |
XilinxTechMapper.constant(Cell parent,
Wire out,
BV value,
java.lang.String name)
|
| Constructors in byucc.jhdl.Xilinx.XC4000 with parameters of type Cell | |
Xwire(Cell parent,
int width)
|
|
Xwire(Cell parent,
int width,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
java.lang.String name)
|
|
Xwire(Cell parent,
WireList wl)
|
|
Xwire(Cell parent,
WireList wl,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire[] wa)
|
|
Xwire(Cell parent,
Wire[] wa,
java.lang.String name)
|
|
| Uses of Cell in byucc.jhdl.Xilinx.XC4000.carryLogic |
| Uses of Cell in byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack |
| Subclasses of Cell in byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack | |
class |
MultAddXC4000
|
class |
MultSubXC4000
|
| Uses of Cell in byucc.jhdl.Xilinx.XC4000.techmap |
| Methods in byucc.jhdl.Xilinx.XC4000.techmap that return Cell | |
static Cell |
TechMapHelper.getSourcePlaceableLeaf(Cell requester,
Wire w)
|
static Cell |
TechMapHelper.getSourceLeafCell(Cell requester,
Wire w)
|
static Cell |
TechMapHelper.getSinkLeafCell(Cell requester,
Cell par,
Wire w)
|
static Cell |
TechMapHelper.getSourceSimulationCell(Wire w)
|
static Cell |
TechMapHelper.getSourcePlaceable(Cell parent,
Wire w1)
|
static Cell |
TechMapHelper.getSourceCell(Cell parent,
Wire w1)
Deprecated. Use getSourcePlaceable() or other getSource methods |
static Cell |
TechMapHelper.getSourcePlaceableCell(Cell parent,
Wire w1)
|
static Cell |
TechMapHelper.getSinkCell(Cell parent,
Wire w1,
Cell c1)
|
static Cell |
TechMapHelper.getSourceHierarchicalCell(Cell caller,
Wire w)
|
static Cell |
TechMapHelper.getSinkHierarchicalCell(Cell caller,
Cell par,
Wire w)
|
Cell |
PlacedCell.getCell()
|
Cell |
XC4000PlacementInfo.getCell()
|
Cell |
CLB.getCellResource(int resourceID)
|
Cell |
Mapper.map(Cell parent,
Wire[] in,
Wire out,
java.lang.String hintstring)
|
Cell |
Mapper.CreateNewfmap_g(Node parent,
Wire[] in,
Wire out,
int generic_width,
int[] widths,
java.lang.String hints)
|
| Methods in byucc.jhdl.Xilinx.XC4000.techmap with parameters of type Cell | |
static int |
TechMapHelper.getPlaceableType(Cell p)
|
static Cell |
TechMapHelper.getSourcePlaceableLeaf(Cell requester,
Wire w)
|
static Cell |
TechMapHelper.getSourceLeafCell(Cell requester,
Wire w)
|
static Cell |
TechMapHelper.getSinkLeafCell(Cell requester,
Cell par,
Wire w)
|
static Cell |
TechMapHelper.getSourcePlaceable(Cell parent,
Wire w1)
|
static Cell |
TechMapHelper.getSourceCell(Cell parent,
Wire w1)
Deprecated. Use getSourcePlaceable() or other getSource methods |
static Cell |
TechMapHelper.getSourcePlaceableCell(Cell parent,
Wire w1)
|
static Cell |
TechMapHelper.getSinkCell(Cell parent,
Wire w1,
Cell c1)
|
static Cell |
TechMapHelper.getSourceHierarchicalCell(Cell caller,
Wire w)
|
static Cell |
TechMapHelper.getSinkHierarchicalCell(Cell caller,
Cell par,
Wire w)
|
static Node |
TechMapHelper.getParentInCurrentLevel(Cell c,
Cell p)
|
XC4000PlacementInfo |
TechMapHelper.createXC4000PlacementInfo(Cell c)
|
static XC4000PlacementInfo |
TechMapHelper.getXC4000PlacementInfo(Cell c)
|
void |
TechMapHelper.addUserMappingHints(Cell cell)
|
abstract void |
PlacedCell.finalizeMove(Cell topcell,
int dx,
int dy,
int pack)
|
void |
PlacedHierarchicalCell.finalizeMove(Cell topcell,
int dx,
int dy,
int pack)
|
void |
TreeCoherencyChecker.checkTreeCoherency(Cell parent)
|
void |
PlacedLeafCell.finalizeMove(Cell topcell,
int dx,
int dy,
int pack)
|
boolean |
XC4000FloorPlanModule.addLayoutView(Cell cell)
|
java.lang.String |
XC4000FloorPlanModule.getCellName(Cell c)
|
boolean |
XC4000FloorPlanModule.NothingPlaced(Cell par)
|
void |
XC4000FloorPlanModule.init(javax.swing.JPanel panel,
Cell top)
|
Cell |
Mapper.map(Cell parent,
Wire[] in,
Wire out,
java.lang.String hintstring)
|
void |
Mapper.re_place(Cell parent,
Cell c1,
int x,
int y,
java.lang.String hints)
|
void |
Mapper.place(Cell parent,
Cell c1,
int x,
int y,
java.lang.String hints)
|
void |
Mapper.iteratedPlaceWire(Cell parent,
Wire w,
int x,
int y,
int dx,
int dy,
java.lang.String hints)
|
java.lang.String |
Mapper.getTechMapHint(Cell c)
|
| Constructors in byucc.jhdl.Xilinx.XC4000.techmap with parameters of type Cell | |
XC4000PlacementInfo(Cell c,
int x,
int y)
|
|
XC4000PlacementInfo(Cell c)
|
|
PlacementChecker(Cell top)
|
|
| Uses of Cell in byucc.jhdl.Xilinx.XC4000.techmap.lists |
| Methods in byucc.jhdl.Xilinx.XC4000.techmap.lists that return Cell | |
Cell |
HierarchicalMappedCellList.getCell()
|
Cell |
TMCellList.getCell()
|
| Methods in byucc.jhdl.Xilinx.XC4000.techmap.lists with parameters of type Cell | |
void |
HierarchicalMappedCellList.append(Cell c)
|
void |
TMCellList.insert(Cell c)
|
| Uses of Cell in byucc.jhdl.Xilinx.XC4000.techmap.tree |
| Methods in byucc.jhdl.Xilinx.XC4000.techmap.tree with parameters of type Cell | |
void |
PlacedLeafCellListGen.processLeafNode(Cell cell)
|
void |
PlacedLeafCellListGen.processHierarchicalNode(Cell cell)
|
void |
RecursionOperator.processLeafNode(Cell cell)
|
void |
RecursionOperator.processHierarchicalNode(Cell cell)
|
boolean |
RecursionOperator.push(Cell cell)
|
void |
RecursionOperator.pop(Cell cell)
|
void |
Recurser.recurse(Cell cell,
RecursionOperator op)
|
boolean |
PlacedCellSelector.push(Cell cell)
|
void |
PlacedCellSelector.pop(Cell cell)
|
void |
PlacedCellSelector.processLeafNode(Cell cell)
|
void |
LeafCellListGenerator.processLeafNode(Cell cell)
|
void |
LeafCellListGenerator.processHierarchicalNode(Cell cell)
|
boolean |
PlacementBoundsChecker.push(Cell cell)
|
void |
PlacementBoundsChecker.pop(Cell cell)
|
void |
PlacementBoundsChecker.processLeafNode(Cell cell)
|
| Constructors in byucc.jhdl.Xilinx.XC4000.techmap.tree with parameters of type Cell | |
PlacedCellSelector(Cell parentCell,
SelectedPlacedCellList selectionList,
boolean select,
XC4000TechMapper mapper,
XC4000FloorPlanCanvas canvas)
|
|
| Uses of Cell in byucc.jhdl.Xilinx.XC9000 |
| Subclasses of Cell in byucc.jhdl.Xilinx.XC9000 | |
class |
add1
See the Xilinx Libraries Guide for details. |
class |
adsu1
See the Xilinx Libraries Guide for details. |
class |
and5_g
This class implements and asynchronous 5-input and gate. |
class |
and6_g
This class implements and asynchronous 6-input and gate. |
class |
and7_g
This class implements and asynchronous 7-input and gate. |
class |
and8_g
This class implements and asynchronous 8-input and gate. |
class |
and9_g
This class implements and asynchronous 9-input and gate. |
class |
bufgsr
See the Xilinx Libraries guide for details. |
class |
fdcp_g
Implements an asynchronously settable/clearable register in the XC4000 library. |
class |
ftcp
Asynchronously presettable/clearable toggle flip-flop. |
class |
nand5_g
This class implements and asynchronous 5-input nand gate. |
class |
nand6_g
This class implements and asynchronous 6-input nand gate. |
class |
nand7_g
This class implements and asynchronous 7-input nand gate. |
class |
nand8_g
This class implements and asynchronous 8-input nand gate. |
class |
nand9_g
This class implements and asynchronous 9-input nand gate. |
class |
nor5_g
This class implements and asynchronous 5-input nor gate. |
class |
nor6_g
This class implements and asynchronous 6-input nor gate. |
class |
nor7_g
This class implements and asynchronous 7-input nor gate. |
class |
nor8_g
This class implements and asynchronous 8-input nor gate. |
class |
nor9_g
This class implements and asynchronous 9-input nor gate. |
class |
or5_g
This class implements and asynchronous 5-input or gate. |
class |
or6_g
This class implements and asynchronous 6-input or gate. |
class |
or7_g
This class implements and asynchronous 7-input or gate. |
class |
or8_g
This class implements and asynchronous 8-input or gate. |
class |
or9_g
This class implements and asynchronous 9-input or gate. |
class |
TESTXC9000Library
This class is the self-test controller for the XC9000 library. |
class |
xnor5_g
This class implements and asynchronous 5-input xnor gate. |
class |
xnor6_g
This class implements and asynchronous 6-input xnor gate. |
class |
xnor7_g
This class implements and asynchronous 7-input xnor gate. |
class |
xnor8_g
This class implements and asynchronous 8-input xnor gate. |
class |
xnor9_g
This class implements and asynchronous 9-input xnor gate. |
class |
xor5_g
This class implements and asynchronous 5-input xor gate. |
class |
xor6_g
This class implements and asynchronous 6-input xor gate. |
class |
xor7_g
This class implements and asynchronous 7-input xor gate. |
class |
xor8_g
This class implements and asynchronous 8-input xor gate. |
class |
xor9_g
This class implements and asynchronous 9-input xor gate. |
| Methods in byucc.jhdl.Xilinx.XC9000 with parameters of type Cell | |
void |
XC9000TechMapper.checkCellnameCoherency(Cell c)
|
java.awt.Dimension |
XC9000TechMapper.checkAllPlacement(Cell c)
|
void |
XC9000TechMapper.padClock(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.padClockR(Cell parent,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.padIn(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.padInR(Cell parent,
boolean clocked,
Wire pad,
Wire in,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.padInout(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.padInoutR(Cell parent,
boolean clockedIn,
Wire in,
boolean clockedOut,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.padOut(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.padOutR(Cell parent,
boolean clocked,
Wire out,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.padOutT(Cell parent,
boolean clocked,
Wire out,
Wire ctl,
Wire pad,
java.lang.String[] mods,
java.lang.String name)
|
void |
XC9000TechMapper.mux(Cell parent,
Wire[] d,
Wire sel,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.and(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.or(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.xor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.nand(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.nor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.xnor(Cell parent,
Wire[] in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.reg(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regc(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regp(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regr(Cell parent,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regre(Cell parent,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regs(Cell parent,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regse(Cell parent,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.reg(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regc(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regp(Cell parent,
Wire clk,
Wire in,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regr(Cell parent,
Wire clk,
Wire in,
Wire r,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regs(Cell parent,
Wire clk,
Wire in,
Wire s,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regse(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire s,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.regre(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire r,
Wire out,
java.lang.String name)
|
void |
XC9000TechMapper.add(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
XC9000TechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire s,
Wire co,
java.lang.String name)
|
void |
XC9000TechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
Wire co,
java.lang.String name)
|
void |
XC9000TechMapper.add(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
XC9000TechMapper.sub(Cell parent,
Wire a,
Wire b,
Wire s,
java.lang.String name)
|
void |
XC9000TechMapper.addsub(Cell parent,
Wire a,
Wire b,
Wire ci,
Wire add,
Wire s,
java.lang.String name)
|
Wire |
XC9000TechMapper.ashiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
XC9000TechMapper.shiftr(Cell parent,
Wire in,
int shift,
Wire out)
|
Wire |
XC9000TechMapper.shiftl(Cell parent,
Wire in,
int shift,
Wire out)
|
void |
XC9000TechMapper.rom(Cell parent,
Wire addr,
Wire data,
long[] init,
java.lang.String name)
|
void |
XC9000TechMapper.ram(Cell parent,
Wire din,
Wire we,
Wire addr,
Wire dout,
long[] init,
java.lang.String name)
|
void |
XC9000TechMapper.rams(Cell parent,
Wire din,
Wire we,
Wire addr,
Wire dout,
long[] init,
java.lang.String name)
|
void |
XC9000TechMapper.ramd(Cell parent,
Wire din,
Wire we,
Wire addrA,
Wire addrB,
Wire outA,
Wire outB,
long[] init,
java.lang.String name)
|
java.lang.String |
XC9000TechMapper.getRLOCFromPlacementInfo(Cell c)
|
static Cell |
XC9000TechMapper.getSourceHierarchicalCell(Cell caller,
Wire w)
|
static Cell |
XC9000TechMapper.getSinkHierarchicalCell(Cell caller,
Cell par,
Wire w)
|
Cell |
XC9000TechMapper.getSourcePlaceable(Cell requester,
Wire w)
|
Cell |
XC9000TechMapper.getSourcePlaceableLeaf(Cell requester,
Wire w)
|
Cell |
XC9000TechMapper.getSinkLeafCell(Logic requester,
Cell par,
Wire w)
Deprecated. Returns any arbitrary leaf cell on the sink list of this wire. |
Cell |
XC9000TechMapper.sink(Logic caller,
Wire w1,
Cell c1)
Deprecated. use getSinkLeafCell |
PlacementInfo |
XC9000TechMapper.createPlacementInfo(Cell c)
|
void |
XC9000TechMapper.place(Logic parent,
Cell c1,
int x,
int y,
java.lang.String hints)
|
java.lang.String |
XC9000TechMapper.getTechMapHint(Logic parent,
Cell c)
|
java.lang.String |
XC9000PlacementInfo.getTransformation(Cell c)
|
abstract void |
XilinxTechMapper.checkCellnameCoherency(Cell c)
|
abstract java.awt.Dimension |
XilinxTechMapper.checkAllPlacement(Cell c)
|
abstract java.lang.String |
XilinxTechMapper.getRLOCFromPlacementInfo(Cell cell)
|
void |
XilinxTechMapper.buf(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.tbuf(Cell parent,
Wire in,
Wire en,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.and(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.or(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.mux(Cell parent,
Wire d0,
Wire d1,
Wire sel,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nand(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.nor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.xnor(Cell parent,
Wire in1,
Wire in2,
Wire in3,
Wire in4,
Wire in5,
Wire in6,
Wire in7,
Wire in8,
Wire in9,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.not(Cell parent,
Wire in,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.vcc(Cell parent,
Wire o,
java.lang.String name)
|
void |
XilinxTechMapper.gnd(Cell parent,
Wire o,
java.lang.String name)
|
void |
XilinxTechMapper.regce(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.regpe(Cell parent,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.regce(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.regpe(Cell parent,
Wire clk,
Wire in,
Wire ce,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.pullup(Cell parent,
Wire out,
java.lang.String name)
|
void |
XilinxTechMapper.pulldown(Cell parent,
Wire out,
java.lang.String name)
|
Wire |
XilinxTechMapper.wire(Cell p,
java.lang.String name)
|
Wire |
XilinxTechMapper.wire(Cell p,
int width,
java.lang.String name)
|
Wire |
XilinxTechMapper.concat(Cell parent,
Wire[] wa,
java.lang.String name)
|
Wire |
XilinxTechMapper.concat(Cell parent,
WireList wl,
java.lang.String name)
|
Wire |
XilinxTechMapper.range(Cell parent,
Wire src,
int hi,
int lo)
|
void |
XilinxTechMapper.constant(Cell parent,
Wire out,
int value,
java.lang.String name)
|
void |
XilinxTechMapper.constant(Cell parent,
Wire out,
long value,
java.lang.String name)
|
void |
XilinxTechMapper.constant(Cell parent,
Wire out,
int[] value,
java.lang.String name)
|
void |
XilinxTechMapper.constant(Cell parent,
Wire out,
BV value,
java.lang.String name)
|
void |
TMCellList.insert(Cell c)
|
| Constructors in byucc.jhdl.Xilinx.XC9000 with parameters of type Cell | |
XC9000PlacementInfo(Cell c)
|
|
XC9000PlacementInfo(Cell c,
int x,
int y)
|
|
andX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
Xwire(Cell parent,
int width)
|
|
Xwire(Cell parent,
int width,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire w1,
Wire w2,
Wire w3,
Wire w4,
Wire w5,
Wire w6,
Wire w7,
Wire w8,
Wire w9,
Wire w10,
Wire w11,
Wire w12,
Wire w13,
Wire w14,
Wire w15,
Wire w16,
java.lang.String name)
|
|
Xwire(Cell parent,
WireList wl)
|
|
Xwire(Cell parent,
WireList wl,
java.lang.String name)
|
|
Xwire(Cell parent,
Wire[] wa)
|
|
Xwire(Cell parent,
Wire[] wa,
java.lang.String name)
|
|
orX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
nandX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
norX_g(Cell parent,
java.lang.String name,
Wire[] in,
Wire out)
|
|
|
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