Package byucc.jhdl.DRC.Rules

Class Summary
AddPropertyMissing This design rule checks every top-level wire for a property.
Bufg  
ClockWires This class implements a DesignRule for checking that implicit and explicit clocks are not being mixed.
DeadHardware  
IBufsAndOBufs This class implements a DesignRule for the Xilinx libraries.
IOBufs This class implements a DesignRule.
MultipleDrivers This is a Design Rule.
NoConnect  
Template  
 



Copyright ? 2006 Brigham Young University, Configurable Computing Laboratory. All Rights Reserved.