byucc.jhdl.platforms.util.readback.Xilinx
Class ReadBackSymbolWriter

java.lang.Object
  byucc.jhdl.platforms.util.readback.Xilinx.ReadBackSymbolWriter

public class ReadBackSymbolWriter

extends java.lang.Object

This class creates the .rbsym "netlist" of all ExternallyUpdateable and LargeExternallyUpdateable objects for Xilinx XC4000 and Virtex FPGAs in JHDL. This class needs to be instanced and used by the testbench or other tool just after creating an (EDIF) netlist. The same Cell used for netlisting to EDIF should be used for creating the .rbsym file. The information from this file provides the various symbol table creation programs with a list of JHDL Cells which can be sampled via readback as well as some vital information about the cells, such as instance names and class names as well as signals attached to their inputs and outputs. The signal names are mainly used for handling the LUT RAM address permutation issues.

Author:

Paul Graham

Constructor Summary

ReadBackSymbolWriter(java.lang.String baseName)
The constructor essentially prepares an .rbsym file for writing.

Method Summary

void	writeRBSymInfo(Cell c) Writes out an .rbsym file for a design starting with the Cell c as the top-level Cell.
void	writeRBSymInfo(Cell c, java.lang.String prefix) Writes out an .rbsym file for a design starting with the Cell c as the top-level Cell, but adds a prefix to all names in the .rbsym file.
void	writeRBSymInfo(HWSystem system) Writes out an .rbsym file for a design assuming that the only child of the HWSystem is the cell to be processed.

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Constructor Detail

ReadBackSymbolWriter

public ReadBackSymbolWriter(java.lang.String baseName)

The constructor essentially prepares an .rbsym file for writing. Once the object is contructed one of the various writeRBSymInfo methods can then be called to write out the contents of the .rbsym file.

Parameters:

baseName - The name of the design without any extensions. It is used for creating the .rbsym file, the name of which will be baseName+".rbsym".

Method Detail

writeRBSymInfo

public void writeRBSymInfo(HWSystem system)

Writes out an .rbsym file for a design assuming that the only child of the HWSystem is the cell to be processed.

Parameters:

system - A reference to the HWSystem for the design. The child of the HWSystem is found and then processed for creating the .rbsym file.

writeRBSymInfo

public void writeRBSymInfo(Cell c)

Writes out an .rbsym file for a design starting with the Cell c as the top-level Cell.

Parameters:

c - A reference to the top-level Cell for the design, the same Cell used for creating the design's (EDIF) netlist.

writeRBSymInfo

public void writeRBSymInfo(Cell c,
                           java.lang.String prefix)

Writes out an .rbsym file for a design starting with the Cell c as the top-level Cell, but adds a prefix to all names in the .rbsym file. This particular version of the method is needed for the cases where a JHDL design is embedded in a larger non-JHDL design as a module. In this case, the prefix must be the name of the design hierachy at which the JHDL design appears in the non-JHDL design. For instance, if the JHDL design appears as "part/X0_JHDL_WRAPPER" in a VHDL design, the prefix string in this method call should be "part/X0_JHDL_WRAPPER". This is needed for the readback symbol table to be properly created since the actual names in the non-JHDL design's FPGA implementation will have an prefix for the names referring to the JHDL module. This currently does not handle more than one instance of a JHDL module in a non-JHDL design.

Parameters:

c - A reference to the top-level Cell for the design, the same Cell used for creating the design's (EDIF) netlist.