A B C D E F G H I J K L M N O P Q R S T U V W X Y Z _

R

R0 - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

R180 - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

R270 - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

R90 - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RADIAN - Static variable in class byucc.jhdl.Logic.Modules.Cordic

RADIAN - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.End_rot

RADIAN - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Init_rot

RADIAN - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Stage

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.Cordic

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.End_rot

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Init_rot

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Stage

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.CordicRP

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.StageRP

RADIX_FORMAT_LIST - Static variable in class byucc.jhdl.apps.Viewers.Schematic.SchematicViewerPanel

RADIX_NAME_LIST - Static variable in class byucc.jhdl.apps.Viewers.Schematic.SchematicViewerPanel

Used to support the JComboBox for radix selection

RAM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

RAM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

RAM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

RAM16X1D - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates that a ram16x1d is located in the slice.

RAM16X1D - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates that a ram16x1d is located in the slice.

RAM16X1F - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates that a ram16x1s/srl16(e) is located in the F LUT.

RAM16X1F - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates that a ram16x1s/srl16(e) is located in the F LUT.

RAM16X1G - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates that a ram16x1s/srl16(e) is located in the G LUT.

RAM16X1G - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates that a ram16x1s/srl16(e) is located in the G LUT.

RAM32X1 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates that a ram32x1s is located in the slice.

RAM32X1 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates that a ram32x1s is located in the slice.

RAMB16 - class byucc.jhdl.Xilinx.Virtex2.RamPack.RAMB16.

This class provides the functionality of the RAMB16 Virtex2 library elements.

RAMB16(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RamPack.RAMB16

RAMB16(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RamPack.RAMB16

RAMB16(Node, String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RamPack.RAMB16

RAMB16Dual - class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual.

Deprecated. Use RAMB16_S_S instead.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualNoParity - class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity.

Deprecated. Use RAMB16_S_S instead.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualParity - class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity.

Deprecated. Use RAMB16_S_S instead.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualParityB - class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB.

Deprecated. Use RAMB16_S_S instead.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16Single - class byucc.jhdl.Xilinx.Virtex2.RAMB16Single.

Deprecated. Use RAMB16_S instead.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new single-ported Block RAM with clock.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new single-ported Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16SingleNoParity - class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity.

Deprecated. Use RAMB16_S instead.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new single-ported Block RAM with clock.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16SingleParity - class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity.

Deprecated. Use RAMB16_S instead.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new single-ported Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S - class byucc.jhdl.Xilinx.Virtex2.RAMB16_S.

This class provides the functionality of the RAMB16_Sn Virtex2 library elements - The Single-ported BlockRams.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new named, single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new named, single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new named, single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[], String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S_S - class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S.

This class provides the functionality of the RAMB16_Sn_Sn Virtex2 library elements - The Dual-ported BlockRams.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[], String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[], String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[], String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB4Dual - class byucc.jhdl.Xilinx.Virtex.RAMB4Dual.

This class provides the functionality of the RAMB4_Sn_Sn Virtex library elements.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

RAMB4Dual_rb - class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb.

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Single - class byucc.jhdl.Xilinx.Virtex.RAMB4Single.

This class provides the functionality of the RAMB4_Sn Virtex library elements.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new single-ported Block RAM with clock.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new, named single-ported Block RAM with clock.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new, named single-ported Block RAM with clock.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new, named single-ported Block RAM with clock.

RAMB4Single(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

RAMB4Single_rb - class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb.

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4_Dual - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Dual.

This class provides the functionality of the RAMB4_Sn_Sn Virtex library elements for EDIF parsing only.

RAMB4_Dual(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Dual

RAMB4_Single - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Single.

This class provides the functionality of the RAMB4_Sn Virtex library elements for EDIF parsing only.

RAMB4_Single(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Single

RAMLoc - Variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates what RAM resources are used in the block.

RAMLoc - Variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates what RAM resources are used in the block.

RAMType - Variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates what types RAMs are implemented by the block.

RAMType - Variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates what types RAMs are implemented by the block.

RAM_DATA_SIZE - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack.LookupTableBlockRAM

RAM_DATA_WIDTH - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack.LookupTableBlockRAM

RAM_FRAME_COUNT - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexBitstreamParams

Block RAM frame count from XAPP 138, the same for all devices

RAM_FRAME_COUNT - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Virtex2BitstreamParams

Block RAM frame count from XAPP 138, the same for all devices

RAM_PARITY_WIDTH - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack.LookupTableBlockRAM

RANGEVECTOR - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

RBLocation - class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation.

This class is used to keep track of the location of a symbol (flip-flop or RAM) in the readback bitstream.

RBLocation() - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation

Constructs an object, setting the frame and frameOffset to the illegal values of -1

RBLocation(RBLocation) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation

Constructs an object, copying the values of an existing RBLocation object to the new object.

RBLocation(int, int) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation

Deprecated. See RBLocation.RBLocation(int,int,int)

RBLocation(int, int, int) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation

Constructs an object by directly setting the frame and frame offset based on its parameters.

RBLocation - class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation.

This class is used to keep track of the location of a symbol (flip-flop or RAM) in the readback bitstream.

RBLocation() - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation

Constructs an object, setting the frame and frameOffset to the illegal values of -1

RBLocation(RBLocation) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation

Constructs an object, copying the values of an existing RBLocation object to the new object.

RBLocation(int, int) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation

Deprecated. See RBLocation.RBLocation(int,int,int)

RBLocation(int, int, int) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation

Constructs an object by directly setting the frame and frame offset based on its parameters.

RBR - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

RBRACKET - Static variable in interface byucc.jhdl.util.BVFormat.FormatStringParserConstants

RB_FAILURE - Static variable in interface byucc.jhdl.platforms.util.readback.NativeReadBackInterface

Constant indicating the failure of an operation

RB_FAILURE - Static variable in interface byucc.jhdl.platforms.util.readback.NativeReadWriteBackInterface

Constant indicating the failure of an operation

RB_POSTAMBLE_SIZE - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XC4KBitstreamParams

The size of one start bit and 11 CRC bits

RB_SUCCESS - Static variable in interface byucc.jhdl.platforms.util.readback.NativeReadBackInterface

Constant indicating the success of an operation

RB_SUCCESS - Static variable in interface byucc.jhdl.platforms.util.readback.NativeReadWriteBackInterface

Constant indicating the success of an operation

READ_FIRST - Static variable in class byucc.jhdl.Xilinx.Virtex2.RamPack.BlockRamView

READ_FIRST - Static variable in class byucc.jhdl.Xilinx.Virtex2.RamPack.BlockRamViewL

RECTANGLE - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RECTANGLESIZE - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RECURSION_FLAG - Static variable in interface byucc.jhdl.base.BooleanFlags

Whether a wire has been visited during a recursive trace

REDUNDANTBLOCKS - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

REDUNDANTBLOCKS - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

REDUNDANTBLOCKS - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.Logic.Modules.MultArrayPack.multCol

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack.multCol

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack.multCol

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack.multCol

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.contrib.modgen.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.Logic.Modules.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.contrib.modgen.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.Logic.Modules.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.contrib.modgen.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.Logic.Modules.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.contrib.modgen.MultArrayPack.multCol

REMAINDER_INDEX - Static variable in class byucc.jhdl.Logic.Modules.IntDivide

For indexing the remainder in the 3 element array compute() returns

REMAINDER_INDEX - Static variable in class byucc.jhdl.contrib.modgen.IntDivide

For indexing the remainder in the 3 element array compute returns

REMOVED - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

REMOVED - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

REMOVED - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

RENAME - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

REQUIRED - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RESET - Static variable in class byucc.jhdl.apps.Broker.BrokerCmds

RESET - Static variable in class byucc.jhdl.apps.Viewers.SimControl.SimControlActionEvent

RESET_METHOD_IMPLEMENTED_BY_USER - Static variable in interface byucc.jhdl.base.BooleanFlags

Records whether the Structural.reset() method of a Structural cell is implemented by the use.

RESISTANCE - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RESOLVES - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

REVISION - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

REVISION - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

REVISION - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

RIGHT - Static variable in class byucc.jhdl.CSRC.Shifter

Simple flag for identifying the right-shift direction in the constructor call.

RIGHT - Static variable in class byucc.jhdl.TERA.Shifter

Simple flag for identifying the right-shift direction in the constructor call.

RIGHT - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.Shifter

RIGHT - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.Shifter

RIGHT - Static variable in class byucc.jhdl.Xilinx.XC4000.Shifter

Simple flag for identifying the right-shift direction in the constructor call.

RIGHT - Static variable in class byucc.jhdl.Xilinx.XC9000.Modules.Shifter

RIGHT_OF - Static variable in class byucc.jhdl.Logic.Logic

Relational Placement directive which indicates that the current cell should be placed in the positive X direction on the JHDL grid from a previous cell.

RIPPER - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

ROM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

ROM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

ROM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

ROM_ADDR_BITS - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.KCMMult

ROM_ADDR_BITS - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack.KCMRom_Adder

ROM_ADDR_BITS - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack.KCM_ROM

ROM_BITS - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.KCMMult

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.Cordic

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Cordic_ctrl

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.End_rot

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Init_rot

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Stage

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.Cordic

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Cordic_ctrl

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Cordicl_ctrl

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.End_rot

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Init_rot

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Stage

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Stagel

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicRP

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.Cordicl

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.StageRP

ROUND - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

ROUND_TOWARD_ZERO - Static variable in class byucc.jhdl.Logic.Modules.FloatingPoint.FPDivide

A constant for truncation mode (no rounding).

ROUND_TOWARD_ZERO - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDivide

A constant for truncation mode (no rounding).

ROUND_TO_NEAREST - Static variable in class byucc.jhdl.Logic.Modules.FloatingPoint.FPDivide

A constant for the default rounding mode: Round to nearest.

ROUND_TO_NEAREST - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDivide

A constant for the default rounding mode: Round to nearest.

ROW_COUNT_XC2S100 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S15 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S150 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S200 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S30 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S50 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV100 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV1000 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV150 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV200 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV300 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV400 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV50 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

The row count for the different part types

ROW_COUNT_XCV600 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV800 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

RPARAN - Static variable in interface byucc.jhdl.util.BVFormat.FormatStringParserConstants

RPAREN - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

RPAREN - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

RPAREN - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

RULES_ONLY - Static variable in class byucc.jhdl.DRC.DesignRuleBrowser

Ram(int, int, int, String) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

Parses the "Ram=..." clauses of the RAM LL entries and enters the data into the RAMGroupHash.

Ram(int, int, int, String) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

Parses the "Ram=..." clauses of the RAM LL entries and enters the data into the RAMGroupHash.

Ram(int, int, int, String) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

Parses the "Ram=..." clauses of the RAM LL entries and enters the data into the RAMGroupHash.

Random - class byucc.jhdl.apps.Stimulator.functions.Random.

This class implements the ValueProvider interface to provide a random value for wire stimulus.

Random(long) - Constructor for class byucc.jhdl.apps.Stimulator.functions.Random

Creates a new Random ValueProvider that uses the given value as a seed for the random values.

Random() - Constructor for class byucc.jhdl.apps.Stimulator.functions.Random

Creates a new Random ValueProvider that uses the current time as the seed for the random values.

Range() - Method in class byucc.jhdl.util.BVFormat.FormatStringParser

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.Fsm.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.Fsm.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.Fsm.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.Fsm.ASCII_CharStream

ReInit(InputStream) - Method in class byucc.jhdl.Fsm.Parser

ReInit(Reader) - Method in class byucc.jhdl.Fsm.Parser

ReInit(ParserTokenManager) - Method in class byucc.jhdl.Fsm.Parser

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.Fsm.ParserTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.Fsm.ParserTokenManager

ReInit(Reader, int, int, int) - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

ReInit(Reader, int, int) - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

ReInit(InputStream, int, int, int) - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

ReInit(InputStream, int, int) - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

ReInit(InputStream) - Static method in class byucc.jhdl.base.genericparser.exprParser

ReInit(Reader) - Static method in class byucc.jhdl.base.genericparser.exprParser

ReInit(exprParserTokenManager) - Method in class byucc.jhdl.base.genericparser.exprParser

ReInit(ASCII_CharStream) - Static method in class byucc.jhdl.base.genericparser.exprParserTokenManager

ReInit(ASCII_CharStream, int) - Static method in class byucc.jhdl.base.genericparser.exprParserTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.parsers.edif.EdifParserCoreTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.parsers.edif.EdifParserCoreTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

ReInit(LL_VirtexTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexTokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexTokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

ReInit(MRP_VirtexTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexTokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_Virtex

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_Virtex

ReInit(XDL_VirtexTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_Virtex

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_VirtexTokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_VirtexTokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

ReInit(LL_Virtex2TokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2TokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2TokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

ReInit(MRP_Virtex2TokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2TokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2TokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2

ReInit(XDL_Virtex2TokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2TokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2TokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

ReInit(LL_4KTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KTokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

ReInit(MRP_4KTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KTokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4K

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4K

ReInit(XDL_4KTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4K

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4KTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4KTokenManager

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.synth.graph.parser.ASCII_UCodeESC_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.synth.graph.parser.ASCII_UCodeESC_CharStream

ReInit(InputStream) - Static method in class byucc.jhdl.synth.graph.parser.DotFileParser

ReInit(DotFileParserTokenManager) - Method in class byucc.jhdl.synth.graph.parser.DotFileParser

ReInit(ASCII_UCodeESC_CharStream) - Static method in class byucc.jhdl.synth.graph.parser.DotFileParserTokenManager

ReInit(ASCII_UCodeESC_CharStream, int) - Static method in class byucc.jhdl.synth.graph.parser.DotFileParserTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

ReInit(InputStream) - Method in class byucc.jhdl.util.BVFormat.FormatStringParser

ReInit(Reader) - Method in class byucc.jhdl.util.BVFormat.FormatStringParser

ReInit(FormatStringParserTokenManager) - Method in class byucc.jhdl.util.BVFormat.FormatStringParser

ReInit(SimpleCharStream) - Method in class byucc.jhdl.util.BVFormat.FormatStringParserTokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.util.BVFormat.FormatStringParserTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(Reader) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReadBackData - class byucc.jhdl.platforms.util.readback.ReadBackData.

The class provides a place for holding all of the information relating to readback for a given PE.

ReadBackDataException - exception byucc.jhdl.platforms.util.readback.ReadBackDataException.

This exception class is used to indicate that various error conditions experienced by the ReadBackData class.

ReadBackManager - class byucc.jhdl.platforms.util.readback.ReadBackManager.

This class provides a testbench (frequently, a board model) with the functionality required to manage readback for a board of contiguously numbered PEs starting with PE 0.

ReadBackManager(NativeReadBackInterface, int) - Constructor for class byucc.jhdl.platforms.util.readback.ReadBackManager

The constructor allocates and initializes the data structures for managing readback for the testbench.

ReadBackManager(NativeReadBackInterface, int, boolean) - Constructor for class byucc.jhdl.platforms.util.readback.ReadBackManager

This is only used by ReadWriteBackManager.

ReadBackSymbolWriter - class byucc.jhdl.platforms.util.readback.Xilinx.ReadBackSymbolWriter.

This class creates the .rbsym "netlist" of all ExternallyUpdateable and LargeExternallyUpdateable objects for Xilinx XC4000 and Virtex FPGAs in JHDL.

ReadBackSymbolWriter(String) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.ReadBackSymbolWriter

The constructor essentially prepares an .rbsym file for writing.

ReadRBSymFile(String) - Static method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexToJHDLSyms

Creates a Hashtable of RBSym objects keyed on the state elements' instance names from the design's .rbsym file.

ReadRBSymFile(String) - Static method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressToJHDLSyms

ReadRBSymFile(String) - Static method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Virtex2ToJHDLSyms

Creates a Hashtable of RBSym objects keyed on the state elements' instance names from the design's .rbsym file.

ReadRBSymFile(String) - Static method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XC4KToJHDLSyms

Creates a Hashtable of RBSym objects keyed on the state elements' instance names from the design's .rbsym file.

ReadStateCommand - class byucc.jhdl.apps.Tbone.ReadStateCommand.

ReadStateCommand(Tbone) - Constructor for class byucc.jhdl.apps.Tbone.ReadStateCommand

ReadWriteBackData - class byucc.jhdl.platforms.util.readback.ReadWriteBackData.

The class provides a place for holding all of the information relating to readback and writeback for a given PE.

ReadWriteBackManager - class byucc.jhdl.platforms.util.readback.ReadWriteBackManager.

This class provides a board model with the functionality required to manage readback and writeback for a board of contiguously numbered PEs starting with PE 0.

ReadWriteBackManager(NativeReadWriteBackInterface, int) - Constructor for class byucc.jhdl.platforms.util.readback.ReadWriteBackManager

The constructore allocates and initializes the data structures for managing readback for the board.

Recent_Classes_File - Static variable in class byucc.jhdl.apps.Jab.BrowserCore

Deprecated.

Recent_Format_File - Static variable in class byucc.jhdl.apps.Jab.BrowserCore

Deprecated.

RectToPolar(Node, Wire, Wire, Wire, Wire) - Static method in class byucc.jhdl.Logic.Modules.CORDICS

Recurser - class byucc.jhdl.Xilinx.XC4000.techmap.tree.Recurser.

Recurser() - Constructor for class byucc.jhdl.Xilinx.XC4000.techmap.tree.Recurser

RecursionOperator - class byucc.jhdl.Xilinx.XC4000.techmap.tree.RecursionOperator.

RecursionOperator() - Constructor for class byucc.jhdl.Xilinx.XC4000.techmap.tree.RecursionOperator

RedundantBlocks() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

Parses the Redundant Block subsection of the file.

RedundantBlocks() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

Parses the Redundant Block subsection of the file.

RedundantBlocks() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

Parses the Redundant Block subsection of the file.

Reflection - class byucc.jhdl.apps.util.Reflection.

Class to assist in the some of the reflection work done by classes such as Stimulator and DynamicTestBench

Reflection() - Constructor for class byucc.jhdl.apps.util.Reflection

RegNode - class byucc.jhdl.apps.Viewers.Schematic.RegNode.

RegNode(Cell, SchematicCanvas, int) - Constructor for class byucc.jhdl.apps.Viewers.Schematic.RegNode

RegisterException - exception byucc.jhdl.platforms.util.RegisterException.

RegisterException() - Constructor for class byucc.jhdl.platforms.util.RegisterException

ReleaseCommand - class byucc.jhdl.apps.Tbone.ReleaseCommand.

ReleaseCommand(Tbone) - Constructor for class byucc.jhdl.apps.Tbone.ReleaseCommand

Remainder - class byucc.jhdl.Logic.Modules.FloatingPoint.SqPack.Remainder.

General Description

Remainder(Node, Wire, Wire) - Constructor for class byucc.jhdl.Logic.Modules.FloatingPoint.SqPack.Remainder

Remainder(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Logic.Modules.FloatingPoint.SqPack.Remainder

RemoteDataReturn - class byucc.jhdl.platforms.util.hwi.RemoteDataReturn.

RemoteDataReturn() - Constructor for class byucc.jhdl.platforms.util.hwi.RemoteDataReturn

RemoteDataReturn(int, byte[][], byte[]) - Constructor for class byucc.jhdl.platforms.util.hwi.RemoteDataReturn

RemoteHardwareControl - class byucc.jhdl.platforms.util.hwi.RemoteHardwareControl.

RemoteHardwareControl(HardwareControlInterface) - Constructor for class byucc.jhdl.platforms.util.hwi.RemoteHardwareControl

RemovedBlock() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

Parses just the removed logic/block clauses for the Trimmed Logic section.

RemovedBlock() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

Parses just the removed logic/block clauses for the Trimmed Logic section.

RemovedBlock() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

Parses just the removed logic/block clauses for the Trimmed Logic section.

RemovedSignal() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

Parses just the removed signal clauses for the Trimmed Logic section.

RemovedSignal() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

Parses just the removed signal clauses for the Trimmed Logic section.

RemovedSignal() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

Parses just the removed signal clauses for the Trimmed Logic section.

Reset - Static variable in class byucc.jhdl.apps.Jab.KeyMan

ResetCommand - class byucc.jhdl.apps.Tbone.ResetCommand.

ResetCommand(HWSystem) - Constructor for class byucc.jhdl.apps.Tbone.ResetCommand

ResetParser - class byucc.jhdl.util.xmac.ResetParser.

Parse the reset tag.

ResetParser(DocInfo) - Constructor for class byucc.jhdl.util.xmac.ResetParser

The default constructor for this class.

Reverse - class byucc.jhdl.Logic.Modules.Reverse.

Completely reverses (mirrors) the bit order of the input, so that LSB becomes MSB, etc...

Reverse(Node, Wire, Wire) - Constructor for class byucc.jhdl.Logic.Modules.Reverse

every output is reversed order of the input, i.e.

ReversePriorityEncoder - class byucc.jhdl.Xilinx.Virtex.Modules.ReversePriorityEncoder.

encodes the input value, prioritizing the bits by LSB has highest priority.

ReversePriorityEncoder(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ReversePriorityEncoder

ReversePriorityEncoder(Node, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ReversePriorityEncoder

"Active" output is removed, for performance reasons.

ReversePriorityEncoder - class byucc.jhdl.Xilinx.Virtex2.Modules.ReversePriorityEncoder.

encodes the input value, prioritizing the bits by LSB has highest priority.

ReversePriorityEncoder(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ReversePriorityEncoder

ReversePriorityEncoder(Node, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ReversePriorityEncoder

"Active" output is removed, for performance reasons.

ReversedDepthFirstAdapter - class byucc.jhdl.parsers.edif.sablecc.analysis.ReversedDepthFirstAdapter.

ReversedDepthFirstAdapter() - Constructor for class byucc.jhdl.parsers.edif.sablecc.analysis.ReversedDepthFirstAdapter

Revision() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

Parses the revision information for the .ll file.

Revision() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

Parses the revision information for the .ll file.

Revision() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

Parses the revision information for the .ll file.

RightShiftReg - class byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack.RightShiftReg.

RightShiftReg.java Created: 3/2002

RightShiftReg(Node, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack.RightShiftReg

Rom() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

Parses "Rom=..." entries, but doesn't do anything with them.

Rom() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

Parses "Rom=..." entries, but doesn't do anything with them.

Rom() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

Parses "Rom=..." entries, but doesn't do anything with them.

Rom128x1View - class byucc.jhdl.Xilinx.Virtex2.Rom128x1View.

This class is for the simulation of block ram's to work correctly.

Rom128x1View(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Rom128x1View

Rom256x1View - class byucc.jhdl.Xilinx.Virtex2.Rom256x1View.

This class is for the simulation of block ram's to work correctly.

Rom256x1View(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Rom256x1View

Rom64x1View - class byucc.jhdl.Xilinx.Virtex2.Rom64x1View.

This class is for the simulation of block ram's to work correctly.

Rom64x1View(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Rom64x1View

Round - class byucc.jhdl.Logic.Modules.FloatingPoint.FPAddSubPack.Round.

Round(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int, int) - Constructor for class byucc.jhdl.Logic.Modules.FloatingPoint.FPAddSubPack.Round

Round - class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack.Round.

Round(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int, int) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack.Round

RoundPipe_IntDivide(Node, Wire, Wire, Wire, Wire, int) - Static method in class byucc.jhdl.Logic.Modules.DIVIDERS

RoundPipe_IntDivide(Node, Wire, Wire, Wire, Wire, int, String) - Static method in class byucc.jhdl.Logic.Modules.DIVIDERS

Round_IntDivide(Node, Wire, Wire, Wire, Wire) - Static method in class byucc.jhdl.Logic.Modules.DIVIDERS

Round_IntDivide(Node, Wire, Wire, Wire, Wire, String) - Static method in class byucc.jhdl.Logic.Modules.DIVIDERS

Rounder(Node, Wire, Wire) - Static method in class byucc.jhdl.Logic.Modules.OTHERS

Rounder(Node, Wire, Wire, String) - Static method in class byucc.jhdl.Logic.Modules.OTHERS

rCompound() - Static method in class byucc.jhdl.synth.graph.parser.DotFileParser

rCompound - class byucc.jhdl.synth.graph.parser.syntaxtree.rCompound.

Grammar production: f0 -> edgeOp() f1 -> simple() f2 -> ( edgeOp() simple() )*

rCompound(edgeOp, simple, NodeListOptional) - Constructor for class byucc.jhdl.synth.graph.parser.syntaxtree.rCompound

radix - Static variable in class byucc.jhdl.apps.Viewers.Schematic.CircuitView

radixFormat - Variable in class byucc.jhdl.apps.Viewers.Schematic.CircuitView

radixFormat - Variable in class byucc.jhdl.apps.Viewers.Schematic.SchematicCanvas

This is the BVFormat that will format the values on the wires of the schematic viewer

ram(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

ram(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

ram(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

ram128x1s - class byucc.jhdl.Xilinx.Virtex2.ram128x1s.

RAM128X1S is a 128-word by 1-bit static random access memory with synchronous write capability.

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

ram128x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Used only by child classes to pass up the parent cell.

ram128x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Used only by child classes to pass up the parent cell and instance name.

ram128x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram128x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram128x1s_1 - class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1.

RAM128X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability.

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

ram128x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Used only by child classes to pass up the parent cell.

ram128x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram128x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram128x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1 - class byucc.jhdl.Xilinx.XC4000.ram16x1.

RAM16X1 is a 16-word by 1-bit static RAM.

ram16x1(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Used only by child classes to pass up the parent cell.

ram16x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Used only by child classes to pass up the parent cell and instance name.

ram16x1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1.

ram16x1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1.

ram16x1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1.

ram16x1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1.

ram16x1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d - class byucc.jhdl.Xilinx.Virtex.ram16x1d.

RAM16X1D is a 16-word by 1-bit static dual-ported RAM.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

ram16x1d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Used only by child classes to pass up the parent cell.

ram16x1d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Used only by child classes to pass up the parent cell and instance name.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d - class byucc.jhdl.Xilinx.Virtex2.ram16x1d.

RAM16X1D is a 16-word by 1-bit static dual-ported RAM.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

ram16x1d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Used only by child classes to pass up the parent cell.

ram16x1d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Used only by child classes to pass up the parent cell and instance name.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d - class byucc.jhdl.Xilinx.XC4000.ram16x1d.

RAM16X1D is a 16-word by 1-bit static dual-ported RAM.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

ram16x1d(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Used only by child classes to pass up the parent cell.

ram16x1d(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Used only by child classes to pass up the parent cell and instance name.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d_1 - class byucc.jhdl.Xilinx.Virtex.ram16x1d_1.

RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

ram16x1d_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Used only by child classes to pass up the parent cell.

ram16x1d_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Used only by child classes to pass up the parent cell and instance name.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d_1 - class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1.

RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

ram16x1d_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Used only by child classes to pass up the parent cell.

ram16x1d_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Used only by child classes to pass up the parent cell and instance name.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s - class byucc.jhdl.Xilinx.Virtex.ram16x1s.

RAM16X1S is a synchronous 16-word by 1-bit static RAM.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

ram16x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Used only by child classes to pass up the parent cell.

ram16x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Used only by child classes to pass up the parent cell and instance name.

ram16x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s - class byucc.jhdl.Xilinx.Virtex2.ram16x1s.

RAM16X1S is a synchronous 16-word by 1-bit static RAM.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

ram16x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Used only by child classes to pass up the parent cell.

ram16x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Used only by child classes to pass up the parent cell and instance name.

ram16x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s - class byucc.jhdl.Xilinx.XC4000.ram16x1s.

RAM16X1S is a synchronous 16-word by 1-bit static RAM.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

ram16x1s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Used only by child classes to pass up the parent cell.

ram16x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Used only by child classes to pass up the parent cell and instance name.

ram16x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s_1 - class byucc.jhdl.Xilinx.Virtex.ram16x1s_1.

RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

ram16x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Used only by child classes to pass up the parent cell.

ram16x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram16x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s_1 - class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1.

RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

ram16x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Used only by child classes to pass up the parent cell.

ram16x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram16x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d - class byucc.jhdl.Xilinx.Virtex.ram16x2d.

RAM16X2D is a 16-word by 2-bit static dual-ported RAM.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

ram16x2d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Used only by child classes to pass up the parent cell.

ram16x2d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Used only by child classes to pass up the parent cell and instance name.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d - class byucc.jhdl.Xilinx.Virtex2.ram16x2d.

RAM16X2D is a 16-word by 2-bit static dual-ported RAM.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

ram16x2d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Used only by child classes to pass up the parent cell.

ram16x2d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Used only by child classes to pass up the parent cell and instance name.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d - class byucc.jhdl.Xilinx.XC4000.ram16x2d.

RAM16X2D is a 16-word by 2-bit static dual-ported RAM.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

ram16x2d(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Used only by child classes to pass up the parent cell.

ram16x2d(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Used only by child classes to pass up the parent cell and instance name.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2s - class byucc.jhdl.Xilinx.Virtex.ram16x2s.

RAM16X2S is a synchronous 16-word by 2-bit static RAM.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

ram16x2s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Used only by child classes to pass up the parent cell.

ram16x2s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Used only by child classes to pass up the parent cell and instance name.

ram16x2s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2s

Constructs a new ram16x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2s - class byucc.jhdl.Xilinx.Virtex2.ram16x2s.

RAM16X2S is a synchronous 16-word by 2-bit static RAM.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

ram16x2s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Used only by child classes to pass up the parent cell.

ram16x2s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Used only by child classes to pass up the parent cell and instance name.

ram16x2s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2s

Constructs a new ram16x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2s - class byucc.jhdl.Xilinx.XC4000.ram16x2s.

RAM16X2S is a synchronous 16-word by 2-bit static RAM.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

ram16x2s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Used only by child classes to pass up the parent cell.

ram16x2s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Used only by child classes to pass up the parent cell and instance name.

ram16x2s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2s

Constructs a new ram16x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4d - class byucc.jhdl.Xilinx.Virtex.ram16x4d.

RAM16X4D is a 16-word by 4-bit static dual-ported RAM.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

ram16x4d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Used only by child classes to pass up the parent cell.

ram16x4d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Used only by child classes to pass up the parent cell and instance name.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4d

Constructs a new ram16x4d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4d - class byucc.jhdl.Xilinx.Virtex2.ram16x4d.

RAM16X4D is a 16-word by 4-bit static dual-ported RAM.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

ram16x4d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Used only by child classes to pass up the parent cell.

ram16x4d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Used only by child classes to pass up the parent cell and instance name.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4d

Constructs a new ram16x4d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4d - class byucc.jhdl.Xilinx.XC4000.ram16x4d.

RAM16X4D is a 16-word by 4-bit static dual-ported RAM.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

ram16x4d(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Used only by child classes to pass up the parent cell.

ram16x4d(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Used only by child classes to pass up the parent cell and instance name.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4d

Constructs a new ram16x4d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4s - class byucc.jhdl.Xilinx.Virtex.ram16x4s.

RAM16X4S is a synchronous 16-word by 4-bit static RAM.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

ram16x4s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Used only by child classes to pass up the parent cell.

ram16x4s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Used only by child classes to pass up the parent cell and instance name.

ram16x4s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x4s

Constructs a new ram16x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4s - class byucc.jhdl.Xilinx.Virtex2.ram16x4s.

RAM16X4S is a synchronous 16-word by 4-bit static RAM.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

ram16x4s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Used only by child classes to pass up the parent cell.

ram16x4s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Used only by child classes to pass up the parent cell and instance name.

ram16x4s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x4s

Constructs a new ram16x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4s - class byucc.jhdl.Xilinx.XC4000.ram16x4s.

RAM16X4S is a synchronous 16-word by 4-bit static RAM.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

ram16x4s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Used only by child classes to pass up the parent cell.

ram16x4s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Used only by child classes to pass up the parent cell and instance name.

ram16x4s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x4s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x4s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x4s

Constructs a new ram16x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8d - class byucc.jhdl.Xilinx.Virtex.ram16x8d.

RAM16X8D is a 16-word by 8-bit static dual-ported RAM.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

ram16x8d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Used only by child classes to pass up the parent cell.

ram16x8d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Used only by child classes to pass up the parent cell and instance name.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8d

Constructs a new ram16x8d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8d - class byucc.jhdl.Xilinx.Virtex2.ram16x8d.

RAM16X8D is a 16-word by 8-bit static dual-ported RAM.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

ram16x8d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Used only by child classes to pass up the parent cell.

ram16x8d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Used only by child classes to pass up the parent cell and instance name.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8d

Constructs a new ram16x8d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8d - class byucc.jhdl.Xilinx.XC4000.ram16x8d.

RAM16X8D is a 16-word by 8-bit static dual-ported RAM.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

ram16x8d(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Used only by child classes to pass up the parent cell.

ram16x8d(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Used only by child classes to pass up the parent cell and instance name.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8d

Constructs a new ram16x8d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8s - class byucc.jhdl.Xilinx.Virtex.ram16x8s.

RAM16X8S is a synchronous 16-word by 8-bit static RAM.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

ram16x8s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Used only by child classes to pass up the parent cell.

ram16x8s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Used only by child classes to pass up the parent cell and instance name.

ram16x8s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

Constructs a new ram16x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x8s

ram16x8s - class byucc.jhdl.Xilinx.Virtex2.ram16x8s.

RAM16X8S is a 16-word by 8-bit static random access memory with synchronous write capability.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

ram16x8s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Used only by child classes to pass up the parent cell.

ram16x8s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Used only by child classes to pass up the parent cell and instance name.

ram16x8s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x8s

Constructs a new ram16x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8s - class byucc.jhdl.Xilinx.XC4000.ram16x8s.

RAM16X8S is a synchronous 16-word by 8-bit static RAM.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

ram16x8s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Used only by child classes to pass up the parent cell.

ram16x8s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Used only by child classes to pass up the parent cell and instance name.

ram16x8s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x8s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

Constructs a new ram16x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x8s

ram32x1 - class byucc.jhdl.Xilinx.XC4000.ram32x1.

RAM32X1 is a 32-word by 1-bit static RAM.

ram32x1(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Used only by child classes to pass up the parent cell.

ram32x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Used only by child classes to pass up the parent cell and instance name.

ram32x1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1.

ram32x1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1.

ram32x1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1.

ram32x1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1.

ram32x1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1

Constructs a new ram32x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1d - class byucc.jhdl.Xilinx.Virtex2.ram32x1d.

RAM32X1D is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.

ram32x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

ram32x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

ram32x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

ram32x1d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Used only by child classes to pass up the parent cell.

ram32x1d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Used only by child classes to pass up the parent cell and instance name.

ram32x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d.

ram32x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d.

ram32x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d.

ram32x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d.

ram32x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d.

ram32x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d.

ram32x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d.

ram32x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d.

ram32x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d

Constructs a new ram32x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1d_1 - class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1.

RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.

ram32x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

ram32x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

ram32x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

ram32x1d_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Used only by child classes to pass up the parent cell.

ram32x1d_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Used only by child classes to pass up the parent cell and instance name.

ram32x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1.

ram32x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1.

ram32x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1.

ram32x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1.

ram32x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1.

ram32x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1.

ram32x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1.

ram32x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1.

ram32x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1d_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1d_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

Constructs a new ram32x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s - class byucc.jhdl.Xilinx.Virtex.ram32x1s.

RAM32X1S is a synchronous 32-word by 1-bit static RAM.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

ram32x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Used only by child classes to pass up the parent cell.

ram32x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Used only by child classes to pass up the parent cell and instance name.

ram32x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s

Constructs a new ram32x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s - class byucc.jhdl.Xilinx.Virtex2.ram32x1s.

RAM32X1S is a synchronous 32-word by 1-bit static RAM.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

ram32x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Used only by child classes to pass up the parent cell.

ram32x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Used only by child classes to pass up the parent cell and instance name.

ram32x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s

Constructs a new ram32x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s - class byucc.jhdl.Xilinx.XC4000.ram32x1s.

RAM32X1S is a synchronous 32-word by 1-bit static RAM.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

ram32x1s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Used only by child classes to pass up the parent cell.

ram32x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Used only by child classes to pass up the parent cell and instance name.

ram32x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x1s

Constructs a new ram32x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_1 - class byucc.jhdl.Xilinx.Virtex.ram32x1s_1.

RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability.

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

ram32x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Used only by child classes to pass up the parent cell.

ram32x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram32x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

Constructs a new ram32x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_1 - class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1.

RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability.

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

ram32x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Used only by child classes to pass up the parent cell.

ram32x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram32x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1.

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

Constructs a new ram32x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_ack - class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack.

ram32x1s_ack(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Used only by child classes to pass up the parent cell.

ram32x1s_ack(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Used only by child classes to pass up the parent cell and instance name.

ram32x1s_ack(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_ack(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_ack(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x1s_ack

ram32x1s_ack - class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack.

ram32x1s_ack(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Used only by child classes to pass up the parent cell.

ram32x1s_ack(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Used only by child classes to pass up the parent cell and instance name.

ram32x1s_ack(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack.

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x1s_ack(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_ack(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

Constructs a new ram32x1s_ack, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x1s_ack(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

ram32x1s_ack(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x1s_ack

ram32x2s - class byucc.jhdl.Xilinx.Virtex.ram32x2s.

RAM32X2S is a synchronous 32-word by 2-bit static RAM.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

ram32x2s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Used only by child classes to pass up the parent cell.

ram32x2s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Used only by child classes to pass up the parent cell and instance name.

ram32x2s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x2s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x2s

Constructs a new ram32x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x2s - class byucc.jhdl.Xilinx.Virtex2.ram32x2s.

RAM32X2S is a synchronous 32-word by 2-bit static RAM.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

ram32x2s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Used only by child classes to pass up the parent cell.

ram32x2s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Used only by child classes to pass up the parent cell and instance name.

ram32x2s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x2s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x2s

Constructs a new ram32x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x2s - class byucc.jhdl.Xilinx.XC4000.ram32x2s.

RAM32X2S is a synchronous 32-word by 2-bit static RAM.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

ram32x2s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Used only by child classes to pass up the parent cell.

ram32x2s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Used only by child classes to pass up the parent cell and instance name.

ram32x2s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x2s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x2s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x2s

Constructs a new ram32x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x4s - class byucc.jhdl.Xilinx.Virtex.ram32x4s.

RAM32X4S is a synchronous 32-word by 4-bit static RAM.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

ram32x4s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Used only by child classes to pass up the parent cell.

ram32x4s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Used only by child classes to pass up the parent cell and instance name.

ram32x4s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x4s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x4s

Constructs a new ram32x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x4s - class byucc.jhdl.Xilinx.Virtex2.ram32x4s.

RAM32X4S is a synchronous 32-word by 4-bit static RAM.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

ram32x4s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Used only by child classes to pass up the parent cell.

ram32x4s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Used only by child classes to pass up the parent cell and instance name.

ram32x4s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x4s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x4s

Constructs a new ram32x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x4s - class byucc.jhdl.Xilinx.XC4000.ram32x4s.

RAM32X4S is a synchronous 32-word by 4-bit static RAM.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

ram32x4s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Used only by child classes to pass up the parent cell.

ram32x4s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Used only by child classes to pass up the parent cell and instance name.

ram32x4s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x4s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x4s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x4s

Constructs a new ram32x4s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x8s - class byucc.jhdl.Xilinx.Virtex.ram32x8s.

RAM32X8S is a synchronous 32-word by 8-bit static RAM.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

ram32x8s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Used only by child classes to pass up the parent cell.

ram32x8s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Used only by child classes to pass up the parent cell and instance name.

ram32x8s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x8s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram32x8s

Constructs a new ram32x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x8s - class byucc.jhdl.Xilinx.Virtex2.ram32x8s.

RAM32X8S is a synchronous 32-word by 8-bit static RAM.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

ram32x8s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Used only by child classes to pass up the parent cell.

ram32x8s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Used only by child classes to pass up the parent cell and instance name.

ram32x8s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x8s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram32x8s

Constructs a new ram32x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x8s - class byucc.jhdl.Xilinx.XC4000.ram32x8s.

RAM32X8S is a synchronous 32-word by 8-bit static RAM.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

ram32x8s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Used only by child classes to pass up the parent cell.

ram32x8s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Used only by child classes to pass up the parent cell and instance name.

ram32x8s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String, String, String, String, String, String, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram32x8s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram32x8s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram32x8s

Constructs a new ram32x8s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x1d - class byucc.jhdl.Xilinx.Virtex2.ram64x1d.

RAM64X1D is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.

ram64x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

ram64x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

ram64x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

ram64x1d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Used only by child classes to pass up the parent cell.

ram64x1d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Used only by child classes to pass up the parent cell and instance name.

ram64x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d.

ram64x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d.

ram64x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d.

ram64x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d.

ram64x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d.

ram64x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d.

ram64x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d.

ram64x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d.

ram64x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram64x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram64x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x1d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d

Constructs a new ram64x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x1d_1 - class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1.

RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.

ram64x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

ram64x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

ram64x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

ram64x1d_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Used only by child classes to pass up the parent cell.

ram64x1d_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Used only by child classes to pass up the parent cell and instance name.

ram64x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1.

ram64x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1.

ram64x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1.

ram64x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1.

ram64x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1.

ram64x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1.

ram64x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1.

ram64x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1.

ram64x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram64x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram64x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1d_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x1d_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

Constructs a new ram64x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x1s - class byucc.jhdl.Xilinx.Virtex2.ram64x1s.

RAM64X1S is a 64-word by 1-bit static random access memory with synchronous write capability.

ram64x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

ram64x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

ram64x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

ram64x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Used only by child classes to pass up the parent cell.

ram64x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Used only by child classes to pass up the parent cell and instance name.

ram64x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s.

ram64x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s.

ram64x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s.

ram64x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s.

ram64x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s.

ram64x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s.

ram64x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s.

ram64x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s.

ram64x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram64x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram64x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s

Constructs a new ram64x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x1s_1 - class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1.

RAM64X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability and a negative-edge clock.

ram64x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

ram64x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

ram64x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

ram64x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Used only by child classes to pass up the parent cell.

ram64x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram64x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1.

ram64x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1.

ram64x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1.

ram64x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1.

ram64x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1.

ram64x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1.

ram64x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1.

ram64x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1.

ram64x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram64x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram64x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

Constructs a new ram64x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x2s - class byucc.jhdl.Xilinx.Virtex2.ram64x2s.

RAM64X2S is a 64-word by 2-bit static random access memory with synchronous write capability.

ram64x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

ram64x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

ram64x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

ram64x2s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Used only by child classes to pass up the parent cell.

ram64x2s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Used only by child classes to pass up the parent cell and instance name.

ram64x2s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s.

ram64x2s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s.

ram64x2s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s.

ram64x2s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s.

ram64x2s(Node, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s.

ram64x2s(Node, String, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s.

ram64x2s(Node, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s.

ram64x2s(Node, String, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s.

ram64x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram64x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram64x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram64x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x2s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x2s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram64x2s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram64x2s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram64x2s

Constructs a new ram64x2s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram_base - class byucc.jhdl.Xilinx.ram_base.

A simple wrapper class that provides an implicit clock port for ram's

ram_base(Logic) - Constructor for class byucc.jhdl.Xilinx.ram_base

ram_base(Logic, boolean) - Constructor for class byucc.jhdl.Xilinx.ram_base

ram_prop - class byucc.jhdl.Xilinx.ram_prop.

Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.

ram_prop(Memory, int, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ram_prop

Deprecated.

ram_prop_1 - class byucc.jhdl.Xilinx.ram_prop_1.

Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.

ram_prop_1(BasicMemory, int, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ram_prop_1

Deprecated.

ram_synch - class byucc.jhdl.Xilinx.ram_synch.

Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.

ram_synch(XilinxMemorySynch, int, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ram_synch

Deprecated.

ram_synch(XilinxMemorySynch, int, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ram_synch

Deprecated.

ram_synch_1 - class byucc.jhdl.Xilinx.ram_synch_1.

Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.

ram_synch_1(XilinxMemorySynch_1, int, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ram_synch_1

Deprecated.

ram_synch_1(XilinxMemorySynch_1, int, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ram_synch_1

Deprecated.

ram_synch_shift - class byucc.jhdl.Xilinx.ram_synch_shift.

Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.

ram_synch_shift(BasicMemory, int, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ram_synch_shift

Deprecated.

ram_synch_shift(BasicMemory, int, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ram_synch_shift

Deprecated.

ramb4_s1 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1.

This class provides the functionality of the RAMB4_S1 Virtex library element for EDIF netlisting only.

ramb4_s1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1

ramb4_s1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1

ramb4_s1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1

ramb4_s16 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s16.

This class provides the functionality of the RAMB4_S16 Virtex library element for EDIF netlisting only.

ramb4_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s16

ramb4_s16(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s16

ramb4_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s16

ramb4_s16_s16 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s16_s16.

This class provides the functionality of the RAMB4_S16_S16 Virtex library element for EDIF netlisting only.

ramb4_s16_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s16_s16

ramb4_s16_s16(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s16_s16

ramb4_s16_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s16_s16

ramb4_s1_s1 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s1.

This class provides the functionality of the RAMB4_S1_S1 Virtex library element for EDIF netlisting only.

ramb4_s1_s1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s1

ramb4_s1_s1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s1

ramb4_s1_s1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s1

ramb4_s1_s16 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s16.

This class provides the functionality of the RAMB4_S1_S16 Virtex library element for EDIF netlisting only.

ramb4_s1_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s16

ramb4_s1_s16(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s16

ramb4_s1_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s16

ramb4_s1_s2 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s2.

This class provides the functionality of the RAMB4_S1_S2 Virtex library element for EDIF netlisting only.

ramb4_s1_s2(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s2

ramb4_s1_s2(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s2

ramb4_s1_s2(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s2

ramb4_s1_s4 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s4.

This class provides the functionality of the RAMB4_S1_S4 Virtex library element for EDIF netlisting only.

ramb4_s1_s4(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s4

ramb4_s1_s4(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s4

ramb4_s1_s4(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s4

ramb4_s1_s8 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s8.

This class provides the functionality of the RAMB4_S1_S8 Virtex library element for EDIF netlisting only.

ramb4_s1_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s8

ramb4_s1_s8(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s8

ramb4_s1_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s1_s8

ramb4_s2 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2.

This class provides the functionality of the RAMB4_S2 Virtex library element for EDIF netlisting only.

ramb4_s2(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2

ramb4_s2(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2

ramb4_s2(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2

ramb4_s2_s16 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s16.

This class provides the functionality of the RAMB4_S2_S16 Virtex library element for EDIF netlisting only.

ramb4_s2_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s16

ramb4_s2_s16(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s16

ramb4_s2_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s16

ramb4_s2_s2 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s2.

This class provides the functionality of the RAMB4_S2_S2 Virtex library element for EDIF netlisting only.

ramb4_s2_s2(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s2

ramb4_s2_s2(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s2

ramb4_s2_s2(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s2

ramb4_s2_s4 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s4.

This class provides the functionality of the RAMB4_S2_S4 Virtex library element for EDIF netlisting only.

ramb4_s2_s4(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s4

ramb4_s2_s4(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s4

ramb4_s2_s4(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s4

ramb4_s2_s8 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s8.

This class provides the functionality of the RAMB4_S2_S8 Virtex library element for EDIF netlisting only.

ramb4_s2_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s8

ramb4_s2_s8(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s8

ramb4_s2_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s2_s8

ramb4_s4 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4.

This class provides the functionality of the RAMB4_S4 Virtex library element for EDIF netlisting only.

ramb4_s4(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4

ramb4_s4(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4

ramb4_s4(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4

ramb4_s4_s16 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s16.

This class provides the functionality of the RAMB4_S4_S16 Virtex library element for EDIF netlisting only.

ramb4_s4_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s16

ramb4_s4_s16(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s16

ramb4_s4_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s16

ramb4_s4_s4 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s4.

This class provides the functionality of the RAMB4_S4_S4 Virtex library element for EDIF netlisting only.

ramb4_s4_s4(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s4

ramb4_s4_s4(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s4

ramb4_s4_s4(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s4

ramb4_s4_s8 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s8.

This class provides the functionality of the RAMB4_S4_S8 Virtex library element for EDIF netlisting only.

ramb4_s4_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s8

ramb4_s4_s8(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s8

ramb4_s4_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s4_s8

ramb4_s8 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8.

This class provides the functionality of the RAMB4_S8 Virtex library element for EDIF netlisting only.

ramb4_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8

ramb4_s8(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8

ramb4_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8

ramb4_s8_s16 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8_s16.

This class provides the functionality of the RAMB4_S8_S16 Virtex library element for EDIF netlisting only.

ramb4_s8_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8_s16

ramb4_s8_s16(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8_s16

ramb4_s8_s16(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8_s16

ramb4_s8_s8 - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8_s8.

This class provides the functionality of the RAMB4_S8_S8 Virtex library element for EDIF netlisting only.

ramb4_s8_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8_s8

ramb4_s8_s8(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8_s8

ramb4_s8_s8(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.ramb4_s8_s8

ramd(Cell, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

ramd(Cell, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

ramd(Cell, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

ramd_prop - class byucc.jhdl.Xilinx.ramd_prop.

Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.

ramd_prop(XilinxMemorySynch, int, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ramd_prop

Deprecated.

ramd_prop_1 - class byucc.jhdl.Xilinx.ramd_prop_1.

Deprecated. Don't use this class anymore, use isAsynchronousSourceSinkResolved() call.

ramd_prop_1(XilinxMemorySynch_1, int, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.ramd_prop_1

Deprecated.

ramrom - class byucc.jhdl.Xilinx.Virtex.Modules.ramrom.

Generic Ram or Rom generator

ramrom(Node, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

ramrom - class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom.

Generic Ram or Rom generator

ramrom(Node, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

ramrom - class byucc.jhdl.Xilinx.XC4000.Modules.ramrom.

Generic Ram or Rom generator

ramrom(Node, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, int[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, int[], String) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, long[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, boolean, long[], String) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

ramrom(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

rams(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

rams(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

rams(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

random - Variable in class byucc.jhdl.Logic.Modules.helpers.tb_Template

A random number generator

range(Cell, Wire, int, int) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

range(Cell, Wire, int, int) - Method in class byucc.jhdl.Logic.BasicTechMapper

range(Wire, int, int) - Method in class byucc.jhdl.Logic.Logic

Returns the sub-range of bits, [hi, lo] (inclusive) from a bus.

range(Cell, Wire, int, int) - Method in class byucc.jhdl.TERA.TechMapper

range(Cell, Wire, int, int) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

range(Cell, Wire, int, int) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

range(Cell, Wire, int, int) - Method in class byucc.jhdl.Xilinx.XC4000.XilinxTechMapper

range(Cell, Wire, int, int) - Method in class byucc.jhdl.Xilinx.XC9000.XilinxTechMapper

range(int, int) - Method in class byucc.jhdl.base.BV

Returns a BV that has the present value of the specified range of this.

range(int, int, BV) - Method in class byucc.jhdl.base.BV

Returns a BV that has the present value of the specified range of this.

range(Cell, int, int, String) - Method in class byucc.jhdl.base.Wire

This returns a new wire that contains only the prescribed range in BITS.

range(Cell, int, int) - Method in class byucc.jhdl.base.Wire

This returns a new wire that contains only the prescribed range.

range(int, int) - Method in class byucc.jhdl.base.Wire

This returns a new wire that contains only the prescribed range.

range(int, int, String) - Method in class byucc.jhdl.base.Wire

This returns a new wire that contains only the prescribed range.

range - class byucc.jhdl.parsers.edif.syntaxtree.range.

Grammar production: f0 -> atLeast() | atMost() | between() | exactly() | greaterThan() | lessThan()

range(NodeChoice) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.range

rangeVector - class byucc.jhdl.parsers.edif.syntaxtree.rangeVector.

Grammar production: f0 -> f1 -> f2 -> ( range() | singleValueSet() )* f3 ->

rangeVector(NodeToken, NodeToken, NodeListOptional, NodeToken) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.rangeVector

rangeVector(NodeListOptional) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.rangeVector

re_place(Cell, Cell, int, int, String) - Method in class byucc.jhdl.Xilinx.XC4000.techmap.Mapper

read(int) - Method in class byucc.jhdl.Xilinx.BasicMemory

read(int, int) - Static method in class byucc.jhdl.Xilinx.MemUtils

read() - Method in class byucc.jhdl.parsers.edif.sablecc.LowerCaseFileReader

readBackData - Variable in class byucc.jhdl.platforms.util.readback.ReadBackManager

The array of ReadBackData objects, one for each PE.

readChar() - Method in class byucc.jhdl.Fsm.ASCII_CharStream

readChar() - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

readChar() - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

readChar() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

readChar() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

readChar() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

readChar() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

readChar() - Static method in class byucc.jhdl.synth.graph.parser.ASCII_UCodeESC_CharStream

readChar() - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

readChar() - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

readLocalRcFile() - Method in class byucc.jhdl.DRC.DesignRuleIndex

readLocalRcFile(String) - Method in class byucc.jhdl.DRC.DesignRuleIndex

readMemoryLocation(int) - Method in class byucc.jhdl.platforms.util.GenericMemory

Reads an entry in the memory and returns it as a BV (Bit Vector).

readMemoryLocation(int, BV) - Method in class byucc.jhdl.platforms.util.GenericMemory

Reads an entry in the memory and returns it as a BV (Bit Vector).

readRegister(int, int, BV) - Method in class byucc.jhdl.platforms.util.GenericBoard

readRegister(int, int, BV) - Method in interface byucc.jhdl.platforms.util.GenericRegisterInterface

readRegisterCmd - class byucc.jhdl.platforms.util.module.readRegisterCmd.

readRegisterCmd(Module, String, boolean) - Constructor for class byucc.jhdl.platforms.util.module.readRegisterCmd

readSingleRegisterSetCmd - class byucc.jhdl.platforms.util.module.readSingleRegisterSetCmd.

readSingleRegisterSetCmd(Module, String, int, boolean) - Constructor for class byucc.jhdl.platforms.util.module.readSingleRegisterSetCmd

readSingleRegisterSetCmd(Module, String, int, boolean, Hashtable) - Constructor for class byucc.jhdl.platforms.util.module.readSingleRegisterSetCmd

readStateFromHardware(int) - Method in class byucc.jhdl.base.ExternalUpdateManager

ReadState.

readSystemState(int, int) - Method in class byucc.jhdl.base.HWSystem

This is to cause the ExternalUpdate Manager to load the state of system from the State object corresponding to the given cycle count

readSystemState(String, int, int) - Method in class byucc.jhdl.base.HWSystem

This is to cause the ExternalUpdate Manager to load the state of system from the State object corresponding to the given cycle count

readSystemState(InputStream) - Method in class byucc.jhdl.base.HWSystem

This is to cause the ExternalUpdate Manager to load the state of system from the State object corresponding to the given cycle count

readback(int, byte[]) - Method in class byucc.jhdl.platforms.util.hwi.HardwareControlInterface

Readbacks the state of the specified FPGA.

readback(int, byte[]) - Method in interface byucc.jhdl.platforms.util.hwi.HardwareControlInterfaceStub

Readbacks the state of the specified FPGA.

readback(int, byte[]) - Method in class byucc.jhdl.platforms.util.hwi.NetworkHardwareControl

Readbacks the state of the specified FPGA.

readback(int, byte[]) - Method in class byucc.jhdl.platforms.util.hwi.RemoteHardwareControl

Readbacks the state of the specified FPGA.

readl(int) - Method in class byucc.jhdl.Xilinx.BasicMemory

rebuildTable(Cell) - Method in class byucc.jhdl.apps.Viewers.WiresTable.WiresTablePanel

record - Variable in class byucc.jhdl.apps.Viewers.Schematic.NetConnection

recreate() - Method in class byucc.jhdl.platforms.util.GenericProcessingElement

rectangle - class byucc.jhdl.parsers.edif.syntaxtree.rectangle.

Grammar production: f0 -> f1 -> f2 -> pointValue() f3 -> pointValue() f4 -> ( property() )* f5 ->

rectangle(NodeToken, NodeToken, pointValue, pointValue, NodeListOptional, NodeToken) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.rectangle

rectangle(pointValue, pointValue, NodeListOptional) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.rectangle

rectangleSize - class byucc.jhdl.parsers.edif.syntaxtree.rectangleSize.

Grammar production: f0 -> f1 -> f2 -> ruleNameDef() f3 -> figureGroupObject() f4 -> ( rangeVector() | multipleValueSet() ) f5 -> ( comment() | userData() )* f6 ->

rectangleSize(NodeToken, NodeToken, ruleNameDef, figureGroupObject, NodeChoice, NodeListOptional, NodeToken) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.rectangleSize

rectangleSize(ruleNameDef, figureGroupObject, NodeChoice, NodeListOptional) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.rectangleSize

recurse(Cell, RecursionOperator) - Method in class byucc.jhdl.Xilinx.XC4000.techmap.tree.Recurser

redirect(String, int) - Static method in class byucc.jhdl.JHDLOutput

Redirects the OutputStream for a given JHDLPrintWriter (identified by its integer ID value) in a named JHDLOutput (i.e., "jab" or "simulator") to null.

redirect(String, int, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the OutputStream for a given JHDLPrintWriter (identified by its integer ID value) in a named JHDLOutput (i.e., "jab" or "simulator") to the OutputStream object passed by the caller.

redirect(String, int, OutputStream, boolean) - Static method in class byucc.jhdl.JHDLOutput

Redirects the OutputStream for a given JHDLPrintWriter (identified by its integer ID value) in a named JHDLOutput (i.e., "jab" or "simulator") to the OutputStream object passed by the caller.

redirect(String, int, Writer) - Static method in class byucc.jhdl.JHDLOutput

Redirects the OutputStream for a given JHDLPrintWriter (identified by its integer ID value) in a named JHDLOutput (i.e., "jab" or "simulator") to the Writer object passed by the caller.

redirect(String, int, Writer, boolean) - Static method in class byucc.jhdl.JHDLOutput

Redirects the OutputStream for a given JHDLPrintWriter (identified by its integer ID value) in a named JHDLOutput (i.e., "jab" or "simulator") to the Writer object passed by the caller.

redirect(int) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance identified by jhdlPrintWriterID to null.

redirect(int, OutputStream, boolean) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance identified by jhdlPrintWriterID to outputStream.

redirect(int, OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance identified by jhdlPrintWriterID to outputStream.

redirect(int, Writer, boolean) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance identified by jhdlPrintWriterID to a Writer.

redirect(int, Writer) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance identified by jhdlPrintWriterID to a Writer.

redirectAll(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects all JHDLPrintWriter instances within the JHDLOutput identified by jhdlOutputID to outputStream.

redirectAll(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects all JHDLPrintWriter instances across the JHDLOutput instance from which it is called to outputStream.

redirectAll(String, Writer) - Static method in class byucc.jhdl.JHDLOutput

Redirects all JHDLPrintWriter instances within the JHDLOutput identified by jhdlOutputID to a Writer.

redirectAll(Writer) - Method in class byucc.jhdl.JHDLOutput

Redirects all JHDLPrintWriter instances across the JHDLOutput instance from which it is called to outputStream.

redirectAllJHDLOutputs(OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects all JHDLPrintWriter instances across all JHDLOutput instances to outputStream.

redirectAllJHDLOutputs(Writer) - Static method in class byucc.jhdl.JHDLOutput

Redirects all JHDLPrintWriter instances across all JHDLOutput instances to a Writer.

redirectDebug(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named debug to the given OutputStream.

redirectDebug(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named debug to the given OutputStream.

redirectErr(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named error to the given OutputStream.

redirectErr(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named error to the given OutputStream.

redirectError(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named error to the given OutputStream.

redirectError(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named error to the given OutputStream.

redirectNotice(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named notice to the given OutputStream.

redirectNotice(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named notice to the given OutputStream.

redirectNotify(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named notice to the given OutputStream.

redirectNotify(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named notice to the given OutputStream.

redirectStatus(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named status to the given OutputStream.

redirectStatus(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named status to the given OutputStream.

redirectWarn(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named warning to the given OutputStream.

redirectWarn(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named warning to the given OutputStream.

redirectWarning(String, OutputStream) - Static method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named warning to the given OutputStream.

redirectWarning(OutputStream) - Method in class byucc.jhdl.JHDLOutput

Redirects the JHDLPrintWriter instance named warning to the given OutputStream.

refreshCellHierarchy() - Method in class byucc.jhdl.apps.Viewers.cvt.cvtFrame

refresh the viewer after changes to the cell hierarchy.

refreshCellHierarchy() - Method in class byucc.jhdl.apps.Viewers.cvt.cvtPanel

update the viewer after the cell hierarchy has been changed.

refreshData() - Method in class byucc.jhdl.util.ui.UISelectorTable

refreshGUI() - Method in class byucc.jhdl.apps.Viewers.Event.JHDLAbstractHostPanel

Refreshes the Master Widget (used for after you add to its JMenuBar.

refreshGUI() - Method in interface byucc.jhdl.apps.Viewers.Event.JHDLHostWidgetInterface

Refreshes the Master Widget (used for after you add to its JMenuBar.

refreshGUI() - Method in class byucc.jhdl.apps.Viewers.cvt.cvtPanel

refreshO() - Method in interface byucc.jhdl.base.Observable

Deprecated. Refresh the view of the observable

reg(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

reg(Cell, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

reg(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Logic.BasicTechMapper

reg(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.BasicTechMapper

reg(Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output.

reg(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output.

reg(Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output.

reg(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output.

reg(Cell, Wire) - Static method in class byucc.jhdl.Logic.LogicStatic

Constructs a new register with a new wire as its output.

reg(Cell, Wire, Wire, String) - Method in class byucc.jhdl.TERA.TechMapper

reg(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

reg(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

reg(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

reg(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

reg(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

reg(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

reg(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

reg(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regX - class byucc.jhdl.TERA.regX.

This instantiates a generic width dff.

regX(Node) - Constructor for class byucc.jhdl.TERA.regX

Used only by child classes to pass up the parent cell.

regX(Node, String) - Constructor for class byucc.jhdl.TERA.regX

Used only by child classes to pass up the parent cell and instance name.

regX(Node, Wire, Wire) - Constructor for class byucc.jhdl.TERA.regX

Constructs a new regX.

regX(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.TERA.regX

Constructs a new regX.

regX(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.TERA.regX

Constructs a new regX, connecting each Wire to the port whose name is given by the accompanying String parameter

regX(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.TERA.regX

Constructs a new regX, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

regX(Node, ArgBlockList) - Constructor for class byucc.jhdl.TERA.regX

Constructs a new regX, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

regX(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.TERA.regX

Constructs a new regX, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

reg_data - Variable in class byucc.jhdl.platforms.util.hwi.RemoteDataReturn

reg_o(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register.

reg_o(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register.

reg_o(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register.

reg_o(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register.

reg_o(Cell, Wire, Wire, String) - Static method in class byucc.jhdl.Logic.LogicStatic

Constructs a new register.

regc(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regc(Cell, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regc(Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output, with global reset state '0'.

regc(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output, with global reset state '0'.

regc(Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output, with global reset state '0'.

regc(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output, with global reset state '0'.

regc(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regc(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regc(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regc(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regc(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regc(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regc(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regc(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regc(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regc(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regc_o(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register, with global reset state '0'.

regc_o(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register, with global reset state '0'.

regc_o(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register, with global reset state '0'.

regc_o(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register, with global reset state '0'.

regce(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regce(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regce(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register with a new wire as its output, with global reset state '0'.

regce(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register with a new wire as its output, with global reset state '0'.

regce(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register with a new wire as its output, with global reset state '0'.

regce(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register with a new wire as its output, with global reset state '0'.

regce(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regce(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regce(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.TERA.TechMapper

regce(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regce(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regce(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regce(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regce(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XilinxTechMapper

regce(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XilinxTechMapper

regce(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XilinxTechMapper

regce(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XilinxTechMapper

regce_o(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register.

regce_o(Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register.

regce_o(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register.

regce_o(Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register.

regfile - class byucc.jhdl.examples.xr16cpu.regfile.

regfile(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.examples.xr16cpu.regfile

registerAlias(String, String) - Method in class byucc.jhdl.util.cli.CLInterpreter

registerCLICommandListener(CLICommandListener) - Method in class byucc.jhdl.util.cli.CLInterpreter

registerCLICommands(HWSystem, CLInterpreter) - Method in class byucc.jhdl.apps.Broker.Broker

Subclasses may use this method to override the default behavior of the broker's CLI commands

registerCLICommands(CLInterpreter) - Static method in class byucc.jhdl.apps.Stimulator.Stimulator

Creates a set of CLI commands for the Stimulator.

registerCells(DesignRuleChecker) - Method in class byucc.jhdl.DRC.DesignRuleViolation

Registers all cells that are involved in this violation with the DRC.

registerCommand(String, CLICommand) - Method in class byucc.jhdl.util.cli.CLInterpreter

registerCommand(String, CLICommand, int) - Method in class byucc.jhdl.util.cli.CLInterpreter

registerConsole(CLIConsole) - Method in class byucc.jhdl.util.cli.CLInterpreter

registerContext(String) - Method in class byucc.jhdl.platforms.util.multicontext.MultiContextTestBench

Informs the multicontext engine about a new context.

registerCustomViewer(Window) - Method in class byucc.jhdl.apps.Broker.Broker

registerDesignRule(DesignRule) - Method in class byucc.jhdl.DRC.DesignRuleChecker

Registers new DesignRules with this DesignRuleChecker.

registerJHDLHostWidgetInterface(JHDLHostWidgetInterface) - Method in class byucc.jhdl.apps.Broker.Broker

Method used to pass the Broker a copy of the JHDLHostWidgetInterface.

registerLoadMemCommand(CLInterpreter) - Method in class byucc.jhdl.platforms.util.module.Module

registerOpCodeArray(OpCode[]) - Static method in class byucc.jhdl.synth.classparse.OpCode

registerPeProgramCommand(CLInterpreter) - Method in class byucc.jhdl.platforms.util.module.Module

registerRegisterCommands(CLInterpreter) - Method in class byucc.jhdl.platforms.util.module.Module

registerRule(DesignRule) - Method in class byucc.jhdl.DRC.DesignRuleChecker

Registers new DesignRules with this DesignRuleChecker.

registerSchematicActionListener(SchematicActionListener) - Method in class byucc.jhdl.apps.Broker.Broker

Deprecated.

registerSelector(CircuitSelector) - Method in class byucc.jhdl.apps.Viewers.BrowserMainFrame.BrowserMainFrame

registerSelector(CircuitSelector) - Method in interface byucc.jhdl.util.gui.CircuitSelectionListener

registerTopFrame(JFrame) - Method in class byucc.jhdl.util.cli.CLInterpreterPanel

registerViolation() - Method in class byucc.jhdl.DRC.DesignRule

Registers that the most recent run against this rule failed.

registerViolation(DesignRule) - Method in class byucc.jhdl.DRC.DesignRuleChecker

Registers a violation of a rule.

registerWireAssignments(boolean) - Method in class byucc.jhdl.synth.GraphStack

Should wire assignments be registered or not.

registerWireAssignments() - Method in class byucc.jhdl.synth.GraphStack

Should wire assignments be registered or not.

regp(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regp(Cell, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regp(Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output, with global reset state '1' x (width of output wire).

regp(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output, with global reset state '1' x (width of output wire).

regp(Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output, with global reset state '1' x (width of output wire).

regp(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register with a new wire as its output, with global reset state '1' x (width of output wire).

regp(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regp(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regp(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regp(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regp(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regp(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regp(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regp(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regp(Cell, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regp(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regp_o(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register, with global reset state '1' x (width of output wire).

regp_o(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register, with global reset state '1' x (width of output wire).

regp_o(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register, with global reset state '1' x (width of output wire).

regp_o(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new register, with global reset state '1' x (width of output wire).

regpe(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regpe(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regpe(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register with a new wire as its output, with global reset state '1' x (width of output wire).

regpe(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register with a new wire as its output, with global reset state '1' x (width of output wire).

regpe(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register with a new wire as its output, with global reset state '1' x (width of output wire).

regpe(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register with a new wire as its output, with global reset state '1' x (width of output wire).

regpe(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regpe(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regpe(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regpe(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regpe(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regpe(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regpe(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XilinxTechMapper

regpe(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XilinxTechMapper

regpe(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XilinxTechMapper

regpe(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XilinxTechMapper

regpe_o(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register, with global reset state '1' x (width of output wire).

regpe_o(Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register, with global reset state '1' x (width of output wire).

regpe_o(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register, with global reset state '1' x (width of output wire).

regpe_o(Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new enabled register, with global reset state '1' x (width of output wire).

regr(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regr(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regr(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously reset register.

regr(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously reset register.

regr(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously reset register with instance name given by the String parameter.

regr(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously reset register with instance name given by the String parameter.

regr(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regr(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regr(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regr(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regr(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regr(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regr(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regr(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regr(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regr(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regr_o(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously reset register with instance name given by the String parameter.

regr_o(Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously reset register.

regr_o(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously reset register with instance name given by the String parameter.

regr_o(Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously reset register with instance name given by the String parameter.

regre(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regre(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regre(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously reset register.

regre(Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously reset register.

regre(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously reset register with instance name given by the String parameter.

regre(Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously reset register with instance name given by the String parameter.

regre(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regre(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regre(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regre(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regre(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regre(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regre(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regre(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regre(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regre(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regre_o(Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously reset register.

regre_o(Wire, Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously reset register.

regre_o(Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously reset register with instance name given by the String parameter.

regre_o(Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously reset register with instance name given by the String parameter.

regs(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regs(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regs(Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously preset register.

regs(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously preset register.

regs(Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously preset register with instance name given by the String parameter.

regs(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously preset register with instance name given by the String parameter.

regs(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regs(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regs(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regs(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regs(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regs(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regs(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regs(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regs(Cell, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regs(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regs_o(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously preset register.

regs_o(Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously preset register.

regs_o(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously preset register with instance name given by the String parameter.

regs_o(Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new synchronously preset register with instance name given by the String parameter.

regse(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regse(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

regse(Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously preset register.

regse(Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously preset register.

regse(Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously preset register with instance name given by the String parameter.

regse(Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously preset register with instance name given by the String parameter.

regse(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regse(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.TechMapper

regse(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regse(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex.VirtexTechMapper

regse(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regse(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.Virtex2.Virtex2TechMapper

regse(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regse(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

regse(Cell, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regse(Cell, Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

regse_o(Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously preset register.

regse_o(Wire, Wire, Wire, Wire, Wire) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously preset register.

regse_o(Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously preset register with instance name given by the String parameter.

regse_o(Wire, Wire, Wire, Wire, Wire, String) - Method in class byucc.jhdl.Logic.LogicGates

Constructs a new clock-enabled synchronously preset register with instance name given by the String parameter.

rehashClassPath() - Method in class byucc.jhdl.util.cli.CLIComplete

rehashClassPath() - Method in class byucc.jhdl.util.cli.CLInterpreter

rehashCmd - class byucc.jhdl.util.cli.rehashCmd.

relDec(int) - Static method in class byucc.jhdl.base.Debug

Decrement the number of spaces preceeding a debug message

relInc(int) - Static method in class byucc.jhdl.base.Debug

Increment the number of spaces preceeding a debug message

releaseTb() - Method in class byucc.jhdl.apps.Tbone.Tbone

rem() - Method in class byucc.jhdl.Fsm.WirePile

remainder(FloatingPoint) - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.helpers.FloatingPoint

Returns the remainder of this FloatingPoint divided by another (that is, this % val).

remainderCalc(long, int, long, int, boolean) - Method in class byucc.jhdl.contrib.modgen.IntDividePack.tbcomp_IntDivide

remove(int, int) - Method in class byucc.jhdl.apps.Viewers.text.FormattedDocument

remove(String) - Method in class byucc.jhdl.base.PropertyList

Deletes the property for the given name, if it exists, otherwise does nothing.

removeAlias(String) - Method in class byucc.jhdl.util.cli.CLICommandObject

removeAllUnconnectedPorts() - Method in class byucc.jhdl.base.Cell

removeAutobuildListener(AutobuildListener) - Static method in class byucc.jhdl.apps.dtb.DynamicTestBench

removes the given AutobuildListener from the list of listeners

removeCircuitView(Cell) - Method in class byucc.jhdl.apps.Jab.BrowserCore

Deprecated.

removeCircuitView(String) - Method in class byucc.jhdl.apps.Jab.BrowserCore

Deprecated.

removeCircuitView(Cell) - Method in interface byucc.jhdl.apps.Viewers.Schematic.CircuitViewListener

removeCircuitView(String) - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeCircuitView, unregister circuit view

removeCircuitView(Cell) - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeCircuitView, unregister circuit view

removeClassView(String) - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeClassView, unregister classView

removeData(int) - Method in class byucc.jhdl.apps.Viewers.Waves.WavesDataManager

This is called to remove data from various vectors after a wire has been removed.

removeEdge(Edge) - Method in class byucc.jhdl.synth.graph.EdgeVector

Removes an edge from this EdgeVector This method identifies the edge to be removed by using the equals method in Edge.

removeEdge(Vertex, Vertex) - Method in class byucc.jhdl.synth.graph.Graph

Removes an Edge from the graph.

removeEdge(Edge) - Static method in class byucc.jhdl.synth.graph.Graph

Removes an Edge from the graph using an existing Edge object.

removeFromMergePortList(String) - Static method in class byucc.jhdl.parsers.edif.EdifParser

Removes nam from a list of ports that the JHDL Generator will attempt to merge into a single bus port.

removeFromMergePortList(String) - Static method in class byucc.jhdl.parsers.edif.NewJHDLGenerator.NewJHDLGenerator

removeFromMergePortList(String) - Static method in class byucc.jhdl.parsers.edif.sablecc.EdifParser

Removes nam from a list of ports that the JHDL Translator will attempt to merge into a single bus port.

removeFromMergePortList(String) - Static method in class byucc.jhdl.parsers.edif.sablecc.translation.EdifToJHDLTranslator

removeJHDLMouseEventGenerator(JHDLMouseEventGenerator) - Method in class byucc.jhdl.apps.Viewers.Event.JHDLAbstractHostPanel

This method will take the passed in JHDLMouseEventGenerator, and call removeJHDLMouseEventListener on it, passing in the designated JHDLMouseEventListener.

removeJHDLMouseEventGenerator(JHDLMouseEventGenerator) - Method in interface byucc.jhdl.apps.Viewers.Event.JHDLHostWidgetInterface

This method will take the passed in JHDLMouseEventGenerator, and call removeJHDLMouseEventListener on it, passing in the designated JHDLMouseEventListener.

removeJHDLMouseEventGenerator(JHDLMouseEventGenerator) - Method in class byucc.jhdl.apps.Viewers.cvt.cvtPanel

This method must call removeJHDLWidgetEventListener on whichever containing widget is designated as the JHDLWidgetEventListener, unless it defines the method, and removes the listener from its own list of listeners, itself.

removeJHDLMouseEventListener(JHDLMouseEventListener) - Method in interface byucc.jhdl.apps.Viewers.Event.JHDLMouseEventGenerator

This method will remove a JHDLMouseEventListener from this widget's list of listeners.

removeJHDLMouseEventListener(JHDLMouseEventListener) - Method in class byucc.jhdl.apps.Viewers.Event.JHDLWidgetPanel

Removes a JHDLMouseEventListener from this widget's list of listeners.

removeJHDLMouseEventListener(JHDLMouseEventListener) - Method in class byucc.jhdl.apps.Viewers.Event.JHDLWidgetScrollPane

Removes a JHDLMouseEventListener from this widget's list of listeners.

removeJHDLWidgetEventListener(JHDLWidgetEventListener) - Method in class byucc.jhdl.apps.Viewers.Event.JHDLAbstractHostPanel

This method must call removeJHDLWidgetEventListener on whichever containing widget is designated as the JHDLWidgetEventListener, unless it defines the method, and removes the listener from its own list of listeners, itself.

removeJHDLWidgetEventListener(JHDLWidgetEventListener) - Method in class byucc.jhdl.apps.Viewers.Event.JHDLAbstractWidgetEventGenerator

Removes a JHDLWidgetEventListener from this widget's list of listeners.

removeJHDLWidgetEventListener(JHDLWidgetEventListener) - Method in interface byucc.jhdl.apps.Viewers.Event.JHDLHostWidgetInterface

This method must call removeJHDLWidgetEventListener on whichever containing widget is designated as the JHDLWidgetEventListener, unless it defines the method, and removes the listener from its own list of listeners, itself.

removeJHDLWidgetEventListener(JHDLWidgetEventListener) - Method in interface byucc.jhdl.apps.Viewers.Event.JHDLWidgetEventGenerator

This method will remove a JHDLWidgetEventListener from this widget's list of listeners.

removeJHDLWidgetEventListener(JHDLWidgetEventListener) - Method in class byucc.jhdl.apps.Viewers.cvt.cvtPanel

This method will take the passed in JHDLMouseEventGenerator, and call removeJHDLMouseEventListener on it, passing in the designated JHDLMouseEventListener.

removeLayoutView(Cell) - Method in interface byucc.jhdl.apps.Viewers.FloorPlan.LayoutViewListener

removeLayoutView(Cell) - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeLayoutView(String) - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeListener(DTBListener) - Method in class byucc.jhdl.apps.dtb.DynamicTestBench

Removes the given DTBListener from the all of the lists of listeners

removeListener(ValueGUIListener) - Method in class byucc.jhdl.apps.dtb.gui.ValueDisplay

Unregisters the given ValueGUIListener

removeListener(CLICommandListener) - Method in class byucc.jhdl.util.cli.CLICommandListenerElement

removeListener(CLICommandListener) - Method in class byucc.jhdl.util.cli.CLICommandListenerQueue

removeMemoryView(String) - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeMemoryView, unregister memory view

removePanel(String) - Method in class byucc.jhdl.apps.Viewers.GenericFrame

removePort(String) - Method in class byucc.jhdl.base.Cell

Removes a port from the cell, after it has been created.

removeProperty(String) - Method in class byucc.jhdl.base.Cell

Used to remove a named property of a Cell.

removeProperty(Property) - Method in class byucc.jhdl.base.PropertyList

Removes the property if it exists, otherwise does nothing.

removeProperty(Cell, String) - Method in class byucc.jhdl.base.Wire

Used to remove a named property of a Wire at the scope of the given cell.

removeProperty(String) - Method in class byucc.jhdl.base.Wire

Used to remove a named property of a Wire at the scope of the wire origin.

removeProperty(String) - Method in class byucc.jhdl.parsers.xnf.XNFCell

removeProperty(Property) - Method in class byucc.jhdl.parsers.xnf.XNFCell

removeReadBack(int) - Method in class byucc.jhdl.platforms.util.readback.ReadBackManager

Reinitializes the readback data structures to a "clean" state.

removeSchematicActionListener(SchematicActionListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicCanvas

Deprecated.

removeSchematicActionListener(SchematicActionListener) - Method in interface byucc.jhdl.apps.Viewers.Schematic.SchematicInterface

Deprecated.

removeSchematicActionListener(SchematicActionListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicScrollPane

Deprecated.

removeSchematicActionListener(SchematicActionListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicViewerFrame

Deprecated.

removeSchematicActionListener(SchematicActionListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicViewerInternalFrame

Deprecated.

removeSchematicActionListener(SchematicActionListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicViewerPanel

Deprecated.

removeSchematicCanvasListener(SchematicCanvasListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicCanvas

Removes a schematic canvas listener from the listener list.

removeSchematicCanvasListener(SchematicCanvasListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicScrollPane

removeSchematicCanvasListener(SchematicCanvasListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicViewerPanel

removeSchematicMouseListener(SchematicMouseListener) - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicCanvas

Removes a schematic mouse listener from the listener list.

removeSelected() - Method in class byucc.jhdl.apps.Viewers.Waves.WatchInterface

removeSelected() - Method in class byucc.jhdl.apps.Viewers.Waves.WavesWireManager

removeSelectedCell(Cell) - Method in class byucc.jhdl.apps.Viewers.BrowserMainFrame.BrowserTree

removeSelectionListener(CircuitSelectionListener) - Method in class byucc.jhdl.Xilinx.XC4000.techmap.XC4000FloorPlanCanvas

removeSelectionListener(CircuitSelectionListener) - Method in class byucc.jhdl.apps.Viewers.BrowserMainFrame.BrowserTree

removeSelectionListener(CircuitSelectionListener) - Method in interface byucc.jhdl.util.gui.CircuitSelector

removeSimControlActionListener(SimControlActionListener) - Method in class byucc.jhdl.apps.Viewers.SimControl.SimControlPanel

removeSimControlActionListener(SimControlActionListener) - Method in class byucc.jhdl.apps.Viewers.SimControl.SimControlToolBar

removeSimulatorCallback(SimulatorCallback) - Method in class byucc.jhdl.base.HWSystem

Adds a SimulatorCallback to the circuit.

removeSimulatorCallback(SimulatorCallback) - Method in class byucc.jhdl.base.Node

removeStepButton() - Method in class byucc.jhdl.apps.Viewers.GenericFrame

removeStepButton() - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeStepButton() - Method in class byucc.jhdl.apps.Viewers.Waves.WatchInterface

removeSubGraph(DFSubGraph) - Method in class byucc.jhdl.synth.DataFlowGraph

Remove a subGraph from this DataFlowGraph.

removeTool(Tool) - Method in class byucc.jhdl.apps.Viewers.ViewManager

addCircuitView, create a new circuit view and register it

removeTopLevelComponent(Component) - Static method in class byucc.jhdl.util.ui.ChangeableMetalTheme

removeTreeBrowserActionListener(TreeBrowserActionListener) - Method in class byucc.jhdl.apps.Viewers.TreeBrowser.TreeBrowserFrame

Deprecated.

removeTreeBrowserActionListener(TreeBrowserActionListener) - Method in class byucc.jhdl.apps.Viewers.TreeBrowser.TreeBrowserPanel

Deprecated.

removeTreeModelListener(TreeModelListener) - Method in class byucc.jhdl.util.gui.TreeModelSupport

removeVertex(Vertex) - Method in class byucc.jhdl.synth.DataFlowGraph

Overrides removeVertex in Graph so that when a Vertex is removed from the graph it will also be cleared from the hashes of any subGraph which may contain the vertex.

removeVertex(Vertex) - Method in class byucc.jhdl.synth.graph.Graph

Removes a Vertex from the graph, as well as all edges associated with the Vertex.

removeVertex(Vertex) - Method in class byucc.jhdl.synth.graph.VertexVector

Removes a vertex from this VertexVector

removeVirtualPort(String) - Method in class byucc.jhdl.platforms.util.GenericInterfaceCell

removeVirtualPort(String) - Method in class byucc.jhdl.platforms.util.GenericProcessingElement

removeWatch(String) - Method in class byucc.jhdl.apps.Jab.BrowserCore

Deprecated.

removeWatch(String) - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeWatch, remove the given wire from the watch list

removeWatch(String) - Method in class byucc.jhdl.apps.Viewers.Waves.WatchInterface

removeWatch(String) - Method in class byucc.jhdl.apps.Viewers.Waves.WavesWireManager

removeWaveView() - Method in class byucc.jhdl.apps.Viewers.ViewManager

removeWavesListener(BrowserWavesListener) - Method in class byucc.jhdl.apps.Viewers.Waves.BrowserWavesPanel

Removes a waves listener from the listener list.

removeWavesWatch(Wire) - Method in class byucc.jhdl.apps.Broker.Broker

removeWire(String) - Method in class byucc.jhdl.apps.Stimulator.Stimulator

Removes the wire of the given name from the wires stimulated by this Stimulator

removeWire(String) - Method in class byucc.jhdl.apps.Stimulator.TriStateStimulator

Since instances of TriStateStimulator can only be associated with one wire and cannot be directly instanced by the user, it makes sense to just can the whole Stimulator object to remove it from the simulator.

removeWireFromAllStimulators(String) - Static method in class byucc.jhdl.apps.Stimulator.Stimulator

If the named wire is currently added to any existing Stimulator, then it is removed.

removeWiresTableActionListener(WiresTableActionListener) - Method in class byucc.jhdl.apps.Viewers.WiresTable.WiresTableFrame

Deprecated.

removeWiresTableActionListener(WiresTableActionListener) - Method in class byucc.jhdl.apps.Viewers.WiresTable.WiresTableInternalFrame

Deprecated.

removeWiresTableActionListener(WiresTableActionListener) - Method in class byucc.jhdl.apps.Viewers.WiresTable.WiresTablePanel

Deprecated.

rename - class byucc.jhdl.parsers.edif.syntaxtree.rename.

Grammar production: f0 -> f1 -> f2 -> ( ident() | name() ) f3 -> ( | stringDisplay() ) f4 ->

rename(NodeToken, NodeToken, NodeChoice, NodeChoice, NodeToken) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.rename

rename(NodeChoice, NodeChoice) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.rename

renderColorDerivative(BufferedImage, int, int) - Static method in class byucc.jhdl.apps.Viewers.NewTreeBrowser.TreeBrowserCellRenderer

Creates a series of icons based on a source image, with varying colorings.

renderColorDerivatives(BufferedImage, int, int) - Static method in class byucc.jhdl.apps.Viewers.NewTreeBrowser.TreeBrowserCellRenderer

Creates a series of icons based on a source image, with varying colorings.

renderer - Variable in class byucc.jhdl.apps.Viewers.NewTreeBrowser.TreeBrowserPanel

repaint() - Method in class byucc.jhdl.apps.Viewers.Waves.BrowserDataCanvas

replaceBy(Node) - Method in class byucc.jhdl.parsers.edif.sablecc.node.Node

replaceBy(Node) - Method in class byucc.jhdl.parsers.xnf.node.Node

replaceLastStateEncodings() - Method in class byucc.jhdl.Fsm.FsmData

Replace last row in truth with encodings

replaceProperty(String, String) - Method in class byucc.jhdl.base.Cell

Used to replace a string property of a Cell.

replaceProperty(Property) - Method in class byucc.jhdl.base.Cell

Used to replace a property of a Cell.

replaceProperty(Cell, String, String) - Method in class byucc.jhdl.base.Wire

Used to replace a string property of a Wire.

replaceProperty(Cell, Property) - Method in class byucc.jhdl.base.Wire

Used to replace a property of a Wire.

replaceProperty(String, String) - Method in class byucc.jhdl.base.Wire

Used to replace a string property of a Wire, within the scope of the wire origin.

replaceProperty(Property) - Method in class byucc.jhdl.base.Wire

Used to replace a property of a Wire, within the scope of the wire origin.

rerouteWires() - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicCanvas

reset() - Method in class byucc.jhdl.CSRC.dff_dp

reset() - Method in class byucc.jhdl.CSRC.dffe_dp

reset() - Method in class byucc.jhdl.CSRC.dffr_dp

reset() - Method in class byucc.jhdl.CSRC.dffre_dp

reset() - Method in class byucc.jhdl.CSRC.dffs_dp

reset() - Method in class byucc.jhdl.CSRC.dffse_dp

reset() - Method in class byucc.jhdl.DRC.Tester.DesignRuleCheckerTester

reset() - Method in class byucc.jhdl.Logic.LibrarySelfTester

Performs the reset cycle test behavior of the library test.

reset() - Method in class byucc.jhdl.Logic.Modules.Cordic

reset() - Method in class byucc.jhdl.Logic.Modules.DigitSerial.DScontrol

reset() - Method in class byucc.jhdl.Logic.Modules.DigitSerial.tb_DS_FIR

reset() - Method in class byucc.jhdl.Logic.Modules.Encoder

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix2.tb_FPDiv_radix2

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix4.tb_FPDiv_radix4

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Array_div_radix8.tb_FPDiv_radix8

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.FPAddSub

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.FPDivide

Used by the simulator.

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.FPDividePack.UIntDivide

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.FPMult

Resets the output to zero

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix2.tb_FPDiv_radix2

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix4.tb_FPDiv_radix4

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Iterative_div_radix8.tb_FPDiv_radix8

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix2.tb_FPDiv_radix2

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix4.tb_FPDiv_radix4

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.Pipeline_div_radix8.tb_FPDiv_radix8

reset() - Method in class byucc.jhdl.Logic.Modules.FloatingPoint.toFloat

Used by the simulator.

reset() - Method in class byucc.jhdl.Logic.Modules.FreeRunTimer

reset() - Method in class byucc.jhdl.Logic.Modules.IntDivide

Reset method puts zeros on quotient, remainder and divideByZero outputs and clears behavioral delay arrays.

reset() - Method in class byucc.jhdl.Logic.Modules.arrayMult

Reset method simply puts zeros onto pout wire and clears behavioral delay array.

reset() - Method in class byucc.jhdl.Logic.Modules.helpers.tb_Template

Puts values on the input wires when the circuit is reset (called by getSystem().reset() )

reset() - Method in class byucc.jhdl.TERA.tera_dff

reset() - Method in class byucc.jhdl.Xilinx.BasicMemory

reset() - Method in class byucc.jhdl.Xilinx.Virtex.BlockRamView

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack.tb_VirtexKCMMultiplier

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.PriorityEncoder

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.ReversePriorityEncoder

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.SRLFifo

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.arrayMult

Reset method simply puts zeros onto pout wire and clears behavioral delay array.

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.delay

Resets the output to zero

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.downcnt

Resets the output to the user-provided reset state.

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.ramrom

Resets the output to zero

reset() - Method in class byucc.jhdl.Xilinx.Virtex.Modules.upcnt

Resets the output to the user-provided reset state.

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fd

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fd_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdc

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdc_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdc_g

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdce

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdce_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdce_g

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdcp

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdcp_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdcpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdcpe_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fde

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fde_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdp

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdp_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdp_g

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdpe_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdr

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdr_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdre

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdre_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdrs

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdrs_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdrse

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdrse_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fds

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fds_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdse

reset() - Method in class byucc.jhdl.Xilinx.Virtex.fdse_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.helpers.tb_adder

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ifd_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ifdi_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ifdx

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ifdxi

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ildx_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ildxi_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ld

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ld_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldc

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldc_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldce

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldce_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldcp

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldcp_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldcpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldcpe_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.lde

reset() - Method in class byucc.jhdl.Xilinx.Virtex.lde_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldp

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldp_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ldpe_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ofdx

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ofdxi

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ram16x1d

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ram16x1s

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ram32x1s

reset() - Method in class byucc.jhdl.Xilinx.Virtex.ram32x1s_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.srl16

reset() - Method in class byucc.jhdl.Xilinx.Virtex.srl16_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.srl16e

reset() - Method in class byucc.jhdl.Xilinx.Virtex.srl16e_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex.tb_BlockRam

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.BlockRamView

Deprecated.

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.BlockRamViewParity

Deprecated.

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSub

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDivide

Used by the simulator.

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack.DelayS

Resets the output to zero

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack.FPMantissaDivide

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPMult

Resets the output to zero

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.PriorityEncoder

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.ReversePriorityEncoder

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.SRLFifo

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.arrayMult

Reset method simply puts zeros onto pout wire and clears behavioral delay array.

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.delay

Resets the output to zero

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.downcnt

Resets the output to the user-provided reset state.

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.ramrom

Resets the output to zero

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.upcnt

Resets the output to the user-provided reset state.

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.RamPack.BlockRamView

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.RamPack.BlockRamViewL

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Rom128x1View

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Rom256x1View

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.Rom64x1View

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.bufgce

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.bufgce_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fd

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fd_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdc

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdc_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdce

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdce_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdce_g

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdcp

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdcp_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdcpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdcpe_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fde

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fde_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdp

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdp_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdp_g

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdpe_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdr

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdr_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdre

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdre_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdrs

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdrs_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdrse

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdrse_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fds

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fds_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fds_g

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdse

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.fdse_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.helpers.tb_adder

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.icap_virtex2

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ifd_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ifdi_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ifdx

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ifdxi

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ildx_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ildxi_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.iobufds

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ld

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ld_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldc

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldc_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldce

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldce_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldcp

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldcp_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldcpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldcpe_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.lde

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.lde_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldp

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldp_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ldpe_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.mult18x18s

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ofddrcpe

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ofddrrse

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ofdx

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ofdxi

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram128x1s

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram16x1d

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram16x1s

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram32x1d

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram32x1d_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram32x1s

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram32x1s_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram64x1d

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram64x1d_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram64x1s

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.ram64x1s_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.roc

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.rocbuf

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.srl16

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.srl16_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.srl16e

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.srl16e_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.srlc16

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.srlc16_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.srlc16e

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.srlc16e_1

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.startbuf_architecture

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.toc

reset() - Method in class byucc.jhdl.Xilinx.Virtex2.tocbuf

reset() - Method in class byucc.jhdl.Xilinx.XC4000.Modules.arrayMult

Reset method simply puts zeros onto pout wire and clears behavioral delay array.

reset() - Method in class byucc.jhdl.Xilinx.XC4000.Modules.delay

Resets the output to zero

reset() - Method in class byucc.jhdl.Xilinx.XC4000.Modules.downcnt

Resets the output to the user-provided reset state.

reset() - Method in class byucc.jhdl.Xilinx.XC4000.Modules.ramrom

Resets the output to zero

reset() - Method in class byucc.jhdl.Xilinx.XC4000.Modules.upcnt

Resets the output to the user-provided reset state.

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fd

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fd_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdc

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdc_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdce

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdce_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdce_g

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fde

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fde_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdp

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdp_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdpe

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdpe_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdr

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdr_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdre_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdrs

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdrs_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdrse

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdrse_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fds

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fds_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdse

reset() - Method in class byucc.jhdl.Xilinx.XC4000.fdse_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ifd_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ifdi_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ifdx

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ifdxi

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ildx_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ildxi_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ilffx

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ilffxi

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ilflx_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ilflxi_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ldce

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ldce_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ldpe_1

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ofdx

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ofdxi

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ram16x1d

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ram16x1s

reset() - Method in class byucc.jhdl.Xilinx.XC4000.ram32x1s

reset() - Method in class byucc.jhdl.Xilinx.XC4000.tb_andX

reset() - Method in class byucc.jhdl.Xilinx.XC4000.techmap.XC4000FloorPlanModule

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fd

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fd_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdc

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdc_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdce

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdce_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdce_g

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdcp

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdcpe

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fde

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fde_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdp

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdp_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdp_g

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdpe

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdpe_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdr_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdre

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdre_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdrs

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdrs_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdrse

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdrse_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fds

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fds_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdse

reset() - Method in class byucc.jhdl.Xilinx.XC9000.fdse_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ftcp

reset() - Method in class byucc.jhdl.Xilinx.XC9000.helpers.tb_adder

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ifd_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ifdi_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ifdx

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ifdxi

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ildx_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ildxi_1

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ld

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ofdx

reset() - Method in class byucc.jhdl.Xilinx.XC9000.ofdxi

reset() - Method in class byucc.jhdl.Xilinx.ram_prop

Deprecated.

reset() - Method in class byucc.jhdl.Xilinx.ram_prop_1

Deprecated.

reset() - Method in class byucc.jhdl.Xilinx.ram_synch

Deprecated.

reset() - Method in class byucc.jhdl.Xilinx.ram_synch_1

Deprecated.

reset() - Method in class byucc.jhdl.Xilinx.ram_synch_shift

Deprecated.

reset() - Method in class byucc.jhdl.Xilinx.ramd_prop

Deprecated.

reset() - Method in class byucc.jhdl.Xilinx.ramd_prop_1

Deprecated.

reset() - Method in class byucc.jhdl.apps.Stimulator.Stimulator

Resets all of the registered wires according to the reset method of the ValueForcers for each wire

reset() - Method in class byucc.jhdl.apps.Tbone.Tbone

reset() - Method in interface byucc.jhdl.apps.Viewers.FloorPlan.FloorPlanModule

reset() - Method in class byucc.jhdl.apps.Viewers.Waves.BrowserWaves

reset() - Method in class byucc.jhdl.apps.Viewers.Waves.BrowserWavesPanel

reset() - Method in class byucc.jhdl.apps.Viewers.Waves.BrowserWavesTable

reset() - Method in class byucc.jhdl.apps.Viewers.Waves.WatchInterface

reset() - Method in class byucc.jhdl.apps.Viewers.Waves.WavesDataManager

reset() - Method in interface byucc.jhdl.apps.Viewers.Waves.WavesViewable

reset() - Method in class byucc.jhdl.apps.Viewers.Waves.WavesWire

reset() - Method in class byucc.jhdl.apps.Viewers.Waves.WavesWireManager

reset() - Method in class byucc.jhdl.apps.Viewers.cvt.DesktopTest

reset() - Method in interface byucc.jhdl.base.Clockable

When this method is called, the synchronous element must behave as would be expected when the reset pin of the hardware is pushed.

reset() - Method in class byucc.jhdl.base.HWSystem

This will reset the simulation.

reset() - Method in class byucc.jhdl.base.Structural

If you define a behavior, you must also define a reset method for resetting the synchonous part of your model.

reset() - Method in class byucc.jhdl.contrib.modgen.Add

Deprecated.

reset() - Method in class byucc.jhdl.contrib.modgen.Adsu

Deprecated.

reset() - Method in class byucc.jhdl.contrib.modgen.Cordic

reset() - Method in class byucc.jhdl.contrib.modgen.CordicRP

reset() - Method in class byucc.jhdl.contrib.modgen.IntDivide

Reset method puts zeros on quotient, remainder and divideByZero outputs and clears behavioral delay arrays.

reset() - Method in class byucc.jhdl.contrib.modgen.IntDividePack.tbcomp_IntDivide

reset() - Method in class byucc.jhdl.contrib.modgen.LFSR4

Resets the output to its first state

reset() - Method in class byucc.jhdl.contrib.modgen.Sub

Deprecated.

reset() - Method in class byucc.jhdl.contrib.modgen.accum

Resets the output to zero

reset() - Method in class byucc.jhdl.contrib.modgen.arrayMult

Reset method simply puts zeros onto pout wire and clears behavioral delay array.

reset() - Method in class byucc.jhdl.contrib.modgen.booth

Sets finished to 1; resets everything else to zero

reset() - Method in class byucc.jhdl.contrib.modgen.downcnt

Resets the output to the user-provided reset state.

reset() - Method in class byucc.jhdl.contrib.modgen.eq

Resets the output to zero

reset() - Method in class byucc.jhdl.contrib.modgen.gt

Resets the output to zero

reset() - Method in class byucc.jhdl.contrib.modgen.lt

Resets the output to zero

reset() - Method in class byucc.jhdl.contrib.modgen.rounder

reset() - Method in class byucc.jhdl.contrib.modgen.upcnt

Resets the output to the user-provided reset state.

reset() - Method in class byucc.jhdl.examples.Calculator

reset() - Method in class byucc.jhdl.platforms.util.multicontext.MultiContextTestBench

reset() - Method in class byucc.jhdl.util.cli.CLICommandListenerQueue

resetBehavioralModelsToDefaults() - Method in class byucc.jhdl.base.Cell

This resets all of the behavioral models from this cell down, to their defaults.

resetExternallyUpdated() - Method in class byucc.jhdl.Xilinx.Memory

reset externally updated status, must be called in the memory's clock method if it was externally updated

resetExternallyUpdated() - Method in class byucc.jhdl.Xilinx.Memory_1

reset externally updated status, must be called in the memory's clock method if it was externally updated

resetFont() - Method in class byucc.jhdl.apps.Viewers.Schematic.UDNImplementation

resetFont() - Method in interface byucc.jhdl.apps.Viewers.Schematic.UserDefinedNode

resetO() - Method in interface byucc.jhdl.base.Observable

Deprecated. Reset the view of the observable

resetSimulator() - Method in class byucc.jhdl.apps.Broker.Broker

resetSimulator() - Method in class byucc.jhdl.apps.Broker.InternalBroker

resetState() - Method in class byucc.jhdl.DRC.DesignRule

Resets all flags to their default values in this instance of DesignRule

resetVisit() - Method in class byucc.jhdl.synth.graph.Vertex

Clear the visited attribute on this vertex, (subsequent calls to isVisited will return false.

resetVisited() - Method in class byucc.jhdl.synth.graph.Graph

Reset the visited flag for all vertices in the graph.

resolveInputSignalsAndConstants() - Method in class byucc.jhdl.synth.DFSubGraph

Resolve the state of this subGraph in terms of input signals and constants.

resolveInputWidths(DFVertex) - Method in interface byucc.jhdl.synth.OperatorSynthesizer

Determine the widths for one or more inputs to the given operator vertex based on the output width and other inputs with established widths.

resolveInputWidths(DFVertex) - Method in class byucc.jhdl.synth.operators.LogicSynthesizer

Determine the widths for one or more inputs to the given operator vertex based on the output width and other inputs with established widths.

resolveInputWidths(DFVertex) - Method in class byucc.jhdl.synth.operators.MuxSynthesizer

Determine the widths for one or more inputs to the given operator vertex based on the output width and other inputs with established widths.

resolveOutputWidth(DFVertex) - Method in interface byucc.jhdl.synth.OperatorSynthesizer

Determine the width for the output of the given operator based on one or more of the inputs with established widths.

resolveOutputWidth(DFVertex) - Method in class byucc.jhdl.synth.operators.LogicSynthesizer

Determine the width for the output of the given operator based on one or more of the inputs with established widths.

resolveOutputWidth(DFVertex) - Method in class byucc.jhdl.synth.operators.MuxSynthesizer

Determine the width for the output of the given operator based on one or more of the inputs with established widths.

resolveTargets() - Method in class byucc.jhdl.synth.classparse.AttributeCode

resolveTargets(AttributeCode) - Method in class byucc.jhdl.synth.classparse.OpCodeSwitch

resolves - class byucc.jhdl.parsers.edif.syntaxtree.resolves.

Grammar production: f0 -> f1 -> f2 -> ( logicNameRef() )* f3 ->

resolves(NodeToken, NodeToken, NodeListOptional, NodeToken) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.resolves

resolves(NodeListOptional) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.resolves

result - Variable in class byucc.jhdl.util.xmac.DocumentMaker

This StringBuffer contains the results of the parse operation.

resultsToString() - Method in class byucc.jhdl.Logic.Modules.helpers.tb_Template

Shows the input and output results as a String

return_value - Variable in class byucc.jhdl.platforms.util.hwi.RemoteDataReturn

reverse(BV) - Static method in class byucc.jhdl.base.BV

Reverses the order of the bits from most to least significant.

reverse(BV, BV) - Static method in class byucc.jhdl.base.BV

Reverses the order of the bits from most to least significant.

reverseBitOrder(Wire) - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack.BarrelShiftR

reverseBitOrder(Wire) - Method in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack.NormalizePE

reverseBits(String) - Static method in class byucc.jhdl.Xilinx.BasicMemory

reverseBits(String) - Static method in class byucc.jhdl.Xilinx.MemUtils

reversed - Variable in class byucc.jhdl.parsers.edif.NewJHDLGenerator.Port

reversed - Variable in class byucc.jhdl.parsers.edif.sablecc.translation.EdifPort

roc - class byucc.jhdl.Xilinx.Virtex2.roc.

roc(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.roc

Used only by child classes to pass up the parent cell.

roc(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.roc

Used only by child classes to pass up the parent cell and instance name.

roc(Node, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.roc

Constructs a new roc.

roc(Node, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.roc

Constructs a new roc.

roc(Node, String, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.roc

Constructs a new roc, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

roc(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.roc

Constructs a new roc, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

roc(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.roc

Constructs a new roc, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rocbuf - class byucc.jhdl.Xilinx.Virtex2.rocbuf.

rocbuf(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rocbuf

Used only by child classes to pass up the parent cell.

rocbuf(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rocbuf

Used only by child classes to pass up the parent cell and instance name.

rocbuf(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rocbuf

Constructs a new rocbuf.

rocbuf(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rocbuf

Constructs a new rocbuf.

rocbuf(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rocbuf

Constructs a new rocbuf, connecting each Wire to the port whose name is given by the accompanying String parameter

rocbuf(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rocbuf

Constructs a new rocbuf, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rocbuf(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rocbuf

Constructs a new rocbuf, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rocbuf(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rocbuf

Constructs a new rocbuf, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom(Cell, Wire, Wire, long[], String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

rom(Cell, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

rom(Cell, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

rom128x1 - class byucc.jhdl.Xilinx.Virtex2.rom128x1.

ROM128X1 is a 128-word by 1-bit ROM.

rom128x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new single-ported BlockRam.

rom128x1(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new named, single-ported BlockRam.

rom128x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new rom128x1.

rom128x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new rom128x1.

rom128x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new rom128x1.

rom128x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new rom128x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom128x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new rom128x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom128x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new rom128x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom128x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

Constructs a new rom128x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom128x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

rom128x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

rom128x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom128x1

rom16x1 - class byucc.jhdl.Xilinx.Virtex.rom16x1.

ROM16X1 is a 16-word by 1-bit ROM.

rom16x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

rom16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

rom16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

rom16x1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Used only by child classes to pass up the parent cell.

rom16x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Used only by child classes to pass up the parent cell and instance name.

rom16x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1.

rom16x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom16x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom16x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom16x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom16x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom16x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom16x1

Constructs a new rom16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom16x1 - class byucc.jhdl.Xilinx.Virtex2.rom16x1.

ROM16X1 is a 16-word by 1-bit ROM.

rom16x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

rom16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

rom16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

rom16x1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Used only by child classes to pass up the parent cell.

rom16x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Used only by child classes to pass up the parent cell and instance name.

rom16x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1.

rom16x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom16x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom16x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom16x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom16x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom16x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom16x1

Constructs a new rom16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom16x1 - class byucc.jhdl.Xilinx.XC4000.rom16x1.

ROM16X1 is a 16-word by 1-bit ROM.

rom16x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

rom16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

rom16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

rom16x1(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Used only by child classes to pass up the parent cell.

rom16x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Used only by child classes to pass up the parent cell and instance name.

rom16x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1.

rom16x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1.

rom16x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom16x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom16x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom16x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom16x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom16x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom16x1

Constructs a new rom16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom256x1 - class byucc.jhdl.Xilinx.Virtex2.rom256x1.

ROM256X1 is a 256-word by 1-bit ROM.

rom256x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new single-ported BlockRam.

rom256x1(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new named, single-ported BlockRam.

rom256x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new rom256x1.

rom256x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new rom256x1.

rom256x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new rom256x1.

rom256x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new rom256x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom256x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new rom256x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom256x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new rom256x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom256x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

Constructs a new rom256x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom256x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

rom256x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

rom256x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom256x1

rom32x1 - class byucc.jhdl.Xilinx.Virtex.rom32x1.

ROM32X1 is a 32-word by 1-bit ROM.

rom32x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

rom32x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

rom32x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

rom32x1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Used only by child classes to pass up the parent cell.

rom32x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Used only by child classes to pass up the parent cell and instance name.

rom32x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1.

rom32x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom32x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom32x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom32x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom32x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom32x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.rom32x1

Constructs a new rom32x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom32x1 - class byucc.jhdl.Xilinx.Virtex2.rom32x1.

ROM32X1 is a 32-word by 1-bit ROM.

rom32x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

rom32x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

rom32x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

rom32x1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Used only by child classes to pass up the parent cell.

rom32x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Used only by child classes to pass up the parent cell and instance name.

rom32x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1.

rom32x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom32x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom32x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom32x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom32x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom32x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom32x1

Constructs a new rom32x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom32x1 - class byucc.jhdl.Xilinx.XC4000.rom32x1.

ROM32X1 is a 32-word by 1-bit ROM.

rom32x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

rom32x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

rom32x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

rom32x1(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Used only by child classes to pass up the parent cell.

rom32x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Used only by child classes to pass up the parent cell and instance name.

rom32x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1.

rom32x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1.

rom32x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom32x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom32x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom32x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom32x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom32x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.rom32x1

Constructs a new rom32x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

rom64x1 - class byucc.jhdl.Xilinx.Virtex2.rom64x1.

ROM64X1 is a 64-word by 1-bit ROM.

rom64x1(Node, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new single-ported BlockRam.

rom64x1(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new named, single-ported BlockRam.

rom64x1(Node, String, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new rom64x1.

rom64x1(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new rom64x1.

rom64x1(Node, String, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new rom64x1.

rom64x1(Node, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new rom64x1, connecting each Wire to the port whose name is given by the accompanying String parameter

rom64x1(Node, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new rom64x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

rom64x1(Node, String, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new rom64x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom64x1(Node, String, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

Constructs a new rom64x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

rom64x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

rom64x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

rom64x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.rom64x1

rootCell() - Method in class byucc.jhdl.apps.Viewers.cvt.cvtFrame

rootCell() - Method in class byucc.jhdl.apps.Viewers.cvt.cvtPanel

rotate(Wire, int) - Method in class byucc.jhdl.Logic.Logic

Rotates the source of the specified wire by the specifed number of degrees in a counter-clockwise direction.

rotate(Cell, int) - Method in class byucc.jhdl.Logic.Logic

Rotates the specified cell by the specifed number of degrees in a counter-clockwise direction.

rotl(int, Wire, String) - Method in class byucc.jhdl.examples.des.DESLogic

rotr(int, Wire, String) - Method in class byucc.jhdl.examples.des.DESLogic

rounder - class byucc.jhdl.Logic.Modules.rounder.

General Description

rounder(Node, Wire, boolean, Wire) - Constructor for class byucc.jhdl.Logic.Modules.rounder

rounder(Node, Wire, boolean, Wire, String) - Constructor for class byucc.jhdl.Logic.Modules.rounder

rounder - class byucc.jhdl.contrib.modgen.rounder.

rounder(Node, Wire, Wire) - Constructor for class byucc.jhdl.contrib.modgen.rounder

rounder(Node, Wire, Wire, boolean) - Constructor for class byucc.jhdl.contrib.modgen.rounder

rounder(Node, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.contrib.modgen.rounder

rounder(Node, Wire, Wire, Wire, boolean, String) - Constructor for class byucc.jhdl.contrib.modgen.rounder

row(int) - Method in class byucc.jhdl.Fsm.TruthTable

rst - Variable in class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Single

rstA - Variable in class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Dual

rstB - Variable in class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Dual

ruleNameDef - class byucc.jhdl.parsers.edif.syntaxtree.ruleNameDef.

Grammar production: f0 -> nameDef()

ruleNameDef(nameDef) - Constructor for class byucc.jhdl.parsers.edif.syntaxtree.ruleNameDef

run() - Method in class byucc.jhdl.DRC.DesignRuleBrowser

run() - Method in class byucc.jhdl.apps.Jab.BrowserCore

Deprecated.

run() - Method in class byucc.jhdl.apps.Jab.TextConsole

run() - Method in class byucc.jhdl.apps.Viewers.Schematic.SchematicCounter

run() - Method in class byucc.jhdl.apps.Viewers.ZeroWing.Animator

run() - Method in class byucc.jhdl.base.HWProcess

run() - Method in class byucc.jhdl.util.gui.MessageBox

This prevents the caller from blocking on ask(), which if this class is used on an awt event thread would cause a deadlock.

runTest(Cell, Cell, Vector) - Static method in class byucc.jhdl.DRC.DesignRuleChecker

A static utility methods to check a set of rules against a component set for the purpose of checking the integrity of this class.

runTestVector() - Method in class byucc.jhdl.Logic.Modules.helpers.tb_Template

User-defined test vector

runningRegression - Static variable in class byucc.jhdl.Xilinx.XC4000.techmap.TESTTechmap