byucc.jhdl.platforms.util.readback.Xilinx.XC4000
Class XC4KToJHDLSyms

java.lang.Object
  byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XC4KToJHDLSyms

public class XC4KToJHDLSyms

extends java.lang.Object

This class builds hardware symbol tables (.rbentry) for Xilinx XC4000-based designs described in JHDL. The program takes several command-line arguments for adjusting the symbol table output. The command-line usage of the command is:

java XC4KToJHDLSyms [-rbheader <size in bits>] [-byteMirrored] <partType> <basename>

The options have the following meanings:

[-rbheader <size in bits>]

Optional: defines the length of the XC4000 readback header (all bits up to but not including the first frame's start bit). The standard size if 5, but it can vary based on the hardware retrieving the readback data.

[-byteMirrored]

Optional: defines how the bits in a byte are addressed. Without this option, the left-most bit (the most significant bit, or MSB) in each byte has an address of 0 while the right-most bit has an address of 7. This is usual ordering for bits in a configuration bitstream. When this option is used, the right-most bit has an address of 0 and the left-most bit in the byte has an address of 7. This may be necessary for some FPGA systems where the readback data is packed into bytes in the reverse order with respect to normal configuration bitstreams.

<partType>

Required: The specific XC4000 FPGA part used for the design.

<basename>

Required: The name of the design without any file extensions. For instance, if the design was netlist as "xp_mydesign.edn", then the <basename> would be just "xp_mydesign" (without the quotes, of course). The name of the symbol table, in this case, would be "xp_mydesign.rbentry".

Unlike VirtexToJHDLSyms, no -nets option is available for creating listings of the physical IOB/CLB outputs driving FPGA design's physical nets.

The class requires a .rbsym file, the Xilinx Logical Allocation (.ll) file, the Xilinx Map Report (.mrp) file, and the Xilinx Design Language (.xdl) file for the design. The .rbsym file should be created by the testbench at netlist time using calls to ReadBackSymbolWriter. The xdl program's -nopips option can be used to reduce the .xdl file size.

Field Summary

static java.lang.String

ArrayChars The delimiters used to parse signal array elements

Constructor Summary

XC4KToJHDLSyms(java.lang.String new_baseName, java.util.Hashtable new_RAMGroupHash, java.util.Hashtable new_NetHashBlock, java.util.Hashtable new_MergedSignalsHash, java.util.Hashtable newInstanceHash, java.util.Hashtable newRBSymHash, java.lang.String partType, int headerBits, boolean byteMirrored)
The base constructor which takes information derived from the command line and the various parsers (LL_4K, MRP_4K, XDL_4K, ReadRBSymFile(String)) and initializes the fields of the object.

Method Summary

void	associateBlocksAndLL() Associates the state elements found in each IOB or CLB with the readback bitstream locations for their state using the .ll file information.
void	associateBlocksAndRBSyms() Tries to correlate the ExternallyUpdateable and elements found in the .rbsym file with Blocks found in the physical design in XDL format.
static java.lang.String	EDIFToJHDLName(java.lang.String EDIFName) Converts an EDIF design name into its JHDL equivalent by replacing all occurences of "__" with "-".
java.lang.String	getBaseName() Returns the file base name for the design (in other words, the file name without a extension).
static void	main(java.lang.String[] args) Creates the .rbentry file from the .rbsym, .ll, .mrp, and .xdl files for the design.
static java.util.Hashtable	ReadRBSymFile(java.lang.String baseName) Creates a Hashtable of RBSym objects keyed on the state elements' instance names from the design's .rbsym file.
static void	usageMessage() Prints the usage message for the program to System.err .

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail

ArrayChars

public static final java.lang.String ArrayChars

The delimiters used to parse signal array elements

See Also:

Constant Field Values

Constructor Detail

XC4KToJHDLSyms

public XC4KToJHDLSyms(java.lang.String new_baseName,
                      java.util.Hashtable new_RAMGroupHash,
                      java.util.Hashtable new_NetHashBlock,
                      java.util.Hashtable new_MergedSignalsHash,
                      java.util.Hashtable newInstanceHash,
                      java.util.Hashtable newRBSymHash,
                      java.lang.String partType,
                      int headerBits,
                      boolean byteMirrored)

The base constructor which takes information derived from the command line and the various parsers (LL_4K, MRP_4K, XDL_4K, ReadRBSymFile(String)) and initializes the fields of the object.

Parameters:

new_baseName - The base file name for the design.

new_RAMGroupHash - The RAMGroupHash from the XDL_4K parser class.

new_NetHashBlock - The NetHashBlock from the XDL_4K parser class.

new_MergedSignalsHash - The MergedSignalsHash from the MRP_4K parser class.

newInstanceHash - The InstanceHash from the XDL_4K parser class.

newRBSymHash - The RBSymHash generated by ReadRBSymFile(String).

partType - The XC4000 part type compatible with XC4KBitstreamParams.

headerBits - The length of the header (all bits up to but not including the first frame's start bit). The standard size if 5, but it can vary based on the hardware retrieving the readback data.

byteMirrored - A boolean which is "true" if the LSB (right-most bit) of the bytes in the byte array holding the readback bitstream is accessed as address 0 within the byte. Otherwise, the MSB (left-most bit) of the byte addressed as bit 0.

Method Detail

getBaseName

public java.lang.String getBaseName()

Returns the file base name for the design (in other words, the file name without a extension).

usageMessage

public static void usageMessage()

Prints the usage message for the program to System.err .

main

public static void main(java.lang.String[] args)

Creates the .rbentry file from the .rbsym, .ll, .mrp, and .xdl files for the design.

Parameters:

args - The command-line arguments for the program.

ReadRBSymFile

public static java.util.Hashtable ReadRBSymFile(java.lang.String baseName)

Creates a Hashtable of RBSym objects keyed on the state elements' instance names from the design's .rbsym file.

Parameters:

baseName - The base file name for the design (design file name without an file extension.

Returns:

A Hashtable of RBSym objects reflecting the JHDL logical state elements and some of their connectivity information.

EDIFToJHDLName

public static java.lang.String EDIFToJHDLName(java.lang.String EDIFName)

Converts an EDIF design name into its JHDL equivalent by replacing all occurences of "__" with "-". This is method is required since EDIF names and JHDL names are not exactly the same due to limitations in EDIF. I stole this from Joe Hawkins' ll2sym code.

Parameters:

EDIFName - The EDIF instance name to convert.

Returns:

The JHDL equivalent name.

associateBlocksAndLL

public void associateBlocksAndLL()

Associates the state elements found in each IOB or CLB with the readback bitstream locations for their state using the .ll file information. The bitstream entries added to the Block entries are arrays since the RAMs have multiple readback bitstream entries. FF's are entered as a single entry array. When no bitstream information can be found, for some reason, all zero bitstream entries are added as padding to maintain the parallel Vector construct.

associateBlocksAndRBSyms

public void associateBlocksAndRBSyms()

Tries to correlate the ExternallyUpdateable and elements found in the .rbsym file with Blocks found in the physical design in XDL format. This effectively correlates logical JHDL state elements to both a physical FPGA resource and its state data in the readback bitstream.