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Wire(parent, num_of_wires, name).
Wire.Wire(Cell, Wire[], String), which has most significant bits in slot 0
Wire.get(source) or related call on the wire.Wire to the port whose name is given by the accompanying String parameter
Wire to the port whose name is given by the accompanying String parameter
The initial String parameter specifies the instance name.
String-Wire pairs in the ArgBlockList.
String-Wire pairs in the ArgBlockList.
int reflecting the Xilinx part type of
the PE.
Node as parent.
Node as parent.
Node as parent.
Node as parent.
Wire to the port whose name is given by the accompanying String parameter
Wire to the port whose name is given by the accompanying String parameter
The initial String parameter specifies the instance name.
String-Wire pairs in the ArgBlockList.
String-Wire pairs in the ArgBlockList.
'\n' characters with a call to JHDLPrintWriter.println().
.rbsym file for a design assuming that
the only child of the HWSystem is the
cell to be processed.
.rbsym file for a design starting with
the Cell c as the top-level
Cell.
.rbsym file for a design starting with
the Cell c as the top-level
Cell, but adds a prefix to all names in the .rbsym
file.
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