byucc.jhdl.synth
Interface OperatorSynthesizer

All Known Implementing Classes:
LogicSynthesizer

public interface OperatorSynthesizer

An interface which specifies a class that is responsible for translating DFVertex operators to JHDL cells. (Most of the classes which implement OperatorSynthesizer should be found in byucc.jhdl.synth.operators)


Method Summary
 Wire createCell(Logic parent, DFVertex operator, Wire[] inputWires)
          Create a cell from the given DFVertex operator.
 void resolveInputWidths(DFVertex operator)
          Determine the widths for one or more inputs to the given operator vertex based on the output width and other inputs with established widths.
 void resolveOutputWidth(DFVertex operator)
          Determine the width for the output of the given operator based on one or more of the inputs with established widths.
 

Method Detail

resolveOutputWidth

public void resolveOutputWidth(DFVertex operator)
Determine the width for the output of the given operator based on one or more of the inputs with established widths.

Parameters:
operator - The operator vertex whose output width is to be resolved.

resolveInputWidths

public void resolveInputWidths(DFVertex operator)
Determine the widths for one or more inputs to the given operator vertex based on the output width and other inputs with established widths.

Parameters:
operator - The operator vertex whose input widths are to be resolved.

createCell

public Wire createCell(Logic parent,
                       DFVertex operator,
                       Wire[] inputWires)
Create a cell from the given DFVertex operator. This method will create the appropriate cell with parent as its parent and input wires from inputWires. It will return a new wire created for the output. The new cell should implement the function defined by operator.getOperation()

Parameters:
operator - an operator in a DataFlowGraph specifying the operation to be performed by the new cell.
inputWires - an array of wires to be used as inputs for the new cells
Returns:
the output wire of the newly created cell.


Copyright ? 2006 Brigham Young University, Configurable Computing Laboratory. All Rights Reserved.