byucc.jhdl.platforms.util.readback.Xilinx.Virtex
Class VirtexXpressToJHDLSyms

java.lang.Object
  byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressToJHDLSyms

public class VirtexXpressToJHDLSyms

extends java.lang.Object

Field Summary

static java.lang.String	arrayChars The delimiters used to parse signal array elements
static int	NO_OFFSET Constant indicating that no readback bitstream offset exists for the given symbol

Constructor Summary

VirtexXpressToJHDLSyms(java.lang.String base_name, java.util.Hashtable ram_group_hash, java.util.Hashtable net_hash_block, java.util.Hashtable merged_signals_hash, java.util.Hashtable instance_hash, java.util.Hashtable rbsym_hash, java.lang.String part_type, boolean use_absolute)

Method Summary

void	associateBlocksAndLL() Associates the state elements found in each IOB or slice with the readback bitstream locations for their state using the .ll file information.
void	associateBlocksAndRBSyms() Tries to correlate the ExternallyUpdateable and LargeExternallyUpdateable elements found in the .rbsym file with Blocks found in the physical design in XDL format.
static java.lang.String	EDIFToJHDLName(java.lang.String EDIFName) Converts an EDIF design name into its JHDL equivalent by replacing all occurences of "__" with "-".
java.lang.String	getBaseName() Returns the file base name for the design (in other words, the file name without a extension).
static void	main(java.lang.String[] args)
static java.util.Hashtable	ReadRBSymFile(java.lang.String base_name)
static void	usageMessage()

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail

arrayChars

public static final java.lang.String arrayChars

The delimiters used to parse signal array elements

See Also:

Constant Field Values

NO_OFFSET

public static final int NO_OFFSET

Constant indicating that no readback bitstream offset exists for the given symbol

See Also:

Constant Field Values

Constructor Detail

VirtexXpressToJHDLSyms

public VirtexXpressToJHDLSyms(java.lang.String base_name,
                              java.util.Hashtable ram_group_hash,
                              java.util.Hashtable net_hash_block,
                              java.util.Hashtable merged_signals_hash,
                              java.util.Hashtable instance_hash,
                              java.util.Hashtable rbsym_hash,
                              java.lang.String part_type,
                              boolean use_absolute)

Method Detail

getBaseName

public java.lang.String getBaseName()

Returns the file base name for the design (in other words, the file name without a extension).

usageMessage

public static void usageMessage()

main

public static void main(java.lang.String[] args)

ReadRBSymFile

public static java.util.Hashtable ReadRBSymFile(java.lang.String base_name)

EDIFToJHDLName

public static java.lang.String EDIFToJHDLName(java.lang.String EDIFName)

Converts an EDIF design name into its JHDL equivalent by replacing all occurences of "__" with "-". This is method is required since EDIF names and JHDL names are not exactly the same due to limitations in EDIF. I stole this from Joe Hawkins' ll2sym code.

Parameters:

EDIFName - The EDIF instance name to convert.

Returns:

The JHDL equivalent name.

associateBlocksAndLL

public void associateBlocksAndLL()

Associates the state elements found in each IOB or slice with the readback bitstream locations for their state using the .ll file information. The bitstream entries added to the Block entries are arrays since the RAMs have multiple readback bitstream entries. FF's are entered as a single entry array. When no bitstream information can be found, for some reason, all zero bitstream entries are added as padding to maintain the parallel Vector construct.

associateBlocksAndRBSyms

public void associateBlocksAndRBSyms()

Tries to correlate the ExternallyUpdateable and LargeExternallyUpdateable elements found in the .rbsym file with Blocks found in the physical design in XDL format. This effectively correlates logical JHDL state elements to both a physical FPGA resource and its state data in the readback bitstream.