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Uses of Interface
byucc.jhdl.apps.Viewers.Schematic.PreDefinedSchematic

Packages that use PreDefinedSchematic
byucc.jhdl.base   
byucc.jhdl.CSRC   
byucc.jhdl.TERA   
byucc.jhdl.Xilinx   
byucc.jhdl.Xilinx.Virtex   
byucc.jhdl.Xilinx.Virtex.helpers   
byucc.jhdl.Xilinx.Virtex.Modules   
byucc.jhdl.Xilinx.Virtex2   
byucc.jhdl.Xilinx.XC4000   
byucc.jhdl.Xilinx.XC9000   
 

Uses of PreDefinedSchematic in byucc.jhdl.base
 

Classes in byucc.jhdl.base that implement PreDefinedSchematic
 class CompiledCodeGenerator
          This class is a generic interface for compiled code simulators.
 

Uses of PreDefinedSchematic in byucc.jhdl.CSRC
 

Classes in byucc.jhdl.CSRC that implement PreDefinedSchematic
 class and2_dp
          This class implements and asynchronous 2-input and gate.
 class and2_dp_g
          This class implements and asynchronous 2-input and gate.
 class and3_dp
          This class implements and asynchronous 3-input and gate.
 class and3_dp_g
          This class implements and asynchronous 3-input and gate.
 class and4_dp
          This class implements and asynchronous 4-input and gate.
 class and5_dp
          This class implements and asynchronous 5-input and gate.
 class and6_dp
          This class implements and asynchronous 6-input and gate.
 class and7_dp
          This class implements and asynchronous 7-input and gate.
 class and8_dp
          This class implements and asynchronous 8-input and gate.
 class and9_dp
          This class implements and asynchronous 9-input and gate.
 class dff_dp
          The dff_dp is a simple D-flipflop.
 class dff_dpX
          This instantiates a generic width dff_dp.
 class dffe_dp
          The dffe_dp is a D-flipflop with a clock enable.
 class dffe_dpX
          This instantiates a generic width dffe_dp.
 class dffr_dp
          The dffr_dp is a D-flipflop with a synchronous reset.
 class dffr_dpX
          This instantiates a generic width dffs_dp.
 class dffre_dp
          The dffre_dp is a D-flipflop with a synchronous reset and a clock enable.
 class dffre_dpX
          This instantiates a generic width dffre_dp.
 class dffs_dp
          The dffs_dp is a D-flipflop with a synchronous set.
 class dffs_dpX
          This instantiates a generic width dffr_dp.
 class dffse_dp
          The dffse_dp is a D-flipflop with a synchronous set and a clock enable.
 class dffse_dpX
          This instantiates a generic width dffse_dp.
 class DL_ONE
          Returns a logic one.
 class DL_ZERO
          Returns a logic zero.
 class IB
          This is an input buffer.
 class IBX
          Generic width output buffer.
 class maj3
          3-input majority gate.
 class mux_dpX
          Generic width 2-1 Mux.
 class mux3_dp
          2-1 Mux.
 class nand2_dp
          This class implements and asynchronous 2-input nand gate.
 class nand2_dp_g
          This class implements and asynchronous 2-input nand gate.
 class nand3_dp
          This class implements and asynchronous 3-input nand gate.
 class nand3_dp_g
          This class implements and asynchronous 3-input nand gate.
 class nand4_dp
          This class implements and asynchronous 4-input nand gate.
 class nand5_dp
          This class implements and asynchronous 5-input nand gate.
 class nand6_dp
          This class implements and asynchronous 6-input nand gate.
 class nand7_dp
          This class implements and asynchronous 7-input nand gate.
 class nand8_dp
          This class implements and asynchronous 8-input nand gate.
 class nand9_dp
          This class implements and asynchronous 9-input nand gate.
 class nor2_dp
          This class implements and asynchronous 2-input nor gate.
 class nor2_dp_g
          This class implements and asynchronous 2-input nor gate.
 class nor3_dp
          This class implements and asynchronous 3-input nor gate.
 class nor3_dp_g
          This class implements and asynchronous 3-input nor gate.
 class nor4_dp
          This class implements and asynchronous 4-input nor gate.
 class nor5_dp
          This class implements and asynchronous 5-input nor gate.
 class nor6_dp
          This class implements and asynchronous 6-input nor gate.
 class nor7_dp
          This class implements and asynchronous 7-input nor gate.
 class nor8_dp
          This class implements and asynchronous 8-input nor gate.
 class nor9_dp
          This class implements and asynchronous 9-input nor gate.
 class not_dp
          Inverter.
 class OB
          This is an output buffer.
 class OBT
          This is an output buffer with a (high?) asserted output enable.
 class OBTX
          Generic width output buffer.
 class OBX
          Generic width output buffer.
 class or2_dp
          This class implements and asynchronous 2-input or gate.
 class or2_dp_g
          This class implements and asynchronous 2-input or gate.
 class or3_dp
          This class implements and asynchronous 3-input or gate.
 class or3_dp_g
          This class implements and asynchronous 3-input or gate.
 class or4_dp
          This class implements and asynchronous 4-input or gate.
 class or5_dp
          This class implements and asynchronous 5-input or gate.
 class or6_dp
          This class implements and asynchronous 6-input or gate.
 class or7_dp
          This class implements and asynchronous 7-input or gate.
 class or8_dp
          This class implements and asynchronous 8-input or gate.
 class or9_dp
          This class implements and asynchronous 9-input or gate.
 class xnor2_dp
          This class implements and asynchronous 2-input xnor gate.
 class xnor2_dp_g
          This class implements and asynchronous 2-input xnor gate.
 class xnor3_dp
          This class implements and asynchronous 3-input xnor gate.
 class xnor3_dp_g
          This class implements and asynchronous 3-input xnor gate.
 class xnor4_dp
          This class implements and asynchronous 4-input xnor gate.
 class xnor5_dp
          This class implements and asynchronous 5-input xnor gate.
 class xnor6_dp
          This class implements and asynchronous 6-input xnor gate.
 class xnor7_dp
          This class implements and asynchronous 7-input xnor gate.
 class xnor8_dp
          This class implements and asynchronous 8-input xnor gate.
 class xnor9_dp
          This class implements and asynchronous 9-input xnor gate.
 class xor2_dp
          This class implements and asynchronous 2-input xor gate.
 class xor2_dp_g
          This class implements and asynchronous 2-input xor gate.
 class xor3_dp
          This class implements and asynchronous 3-input xor gate.
 class xor3_dp_g
          This class implements and asynchronous 3-input xor gate.
 class xor4_dp
          This class implements and asynchronous 4-input xor gate.
 class xor5_dp
          This class implements and asynchronous 5-input xor gate.
 class xor6_dp
          This class implements and asynchronous 6-input xor gate.
 class xor7_dp
          This class implements and asynchronous 7-input xor gate.
 class xor8_dp
          This class implements and asynchronous 8-input xor gate.
 class xor9_dp
          This class implements and asynchronous 9-input xor gate.
 

Uses of PreDefinedSchematic in byucc.jhdl.TERA
 

Classes in byucc.jhdl.TERA that implement PreDefinedSchematic
 class addsubX
          Generic width adder-subtractor.
 class addX
          Generic width adder.
 class bufX
          This cell buffers each input wire.
 class gndX
          This instantiates a generic width vcc.
 class muxX
          Generic width 2-1 Mux.
 class notX
          This cell inverts each input wire.
 class regX
          This instantiates a generic width dff.
 class subX
          Generic width subtractor.
 class tera_add
          Full Adder teramac style.
 class tera_and2
          This class implements and asynchronous 2-input and gate.
 class tera_and2_g
          This class implements and asynchronous 2-input and gate.
 class tera_and3
          This class implements and asynchronous 3-input and gate.
 class tera_and3_g
          This class implements and asynchronous 3-input and gate.
 class tera_and4
          This class implements and asynchronous 4-input and gate.
 class tera_and4_g
          This class implements and asynchronous 4-input and gate.
 class tera_and5
          This class implements and asynchronous 5-input and gate.
 class tera_and5_g
          This class implements and asynchronous 5-input and gate.
 class tera_and6
          This class implements and asynchronous 6-input and gate.
 class tera_and6_g
          This class implements and asynchronous 6-input and gate.
 class tera_and7
          This class implements and asynchronous 7-input and gate.
 class tera_and7_g
          This class implements and asynchronous 7-input and gate.
 class tera_and8
          This class implements and asynchronous 8-input and gate.
 class tera_and8_g
          This class implements and asynchronous 8-input and gate.
 class tera_buf
          Buffer.
 class tera_dff
          The tera_dff is a simple D-flipflop.
 class tera_high
          Returns a logic one.
 class tera_inv
          Inverter.
 class tera_low
          Returns a logic zero.
 class tera_mem
          Buffer.
 class tera_mux2
          Mux2
 class tera_mux4
          Mux4
 class tera_nand2
          This class implements and asynchronous 2-input nand gate.
 class tera_nand2_g
          This class implements and asynchronous 2-input nand gate.
 class tera_nand3
          This class implements and asynchronous 3-input nand gate.
 class tera_nand3_g
          This class implements and asynchronous 3-input nand gate.
 class tera_nand4
          This class implements and asynchronous 4-input nand gate.
 class tera_nand4_g
          This class implements and asynchronous 4-input nand gate.
 class tera_nand5
          This class implements and asynchronous 5-input nand gate.
 class tera_nand5_g
          This class implements and asynchronous 5-input nand gate.
 class tera_nand6
          This class implements and asynchronous 6-input nand gate.
 class tera_nand6_g
          This class implements and asynchronous 6-input nand gate.
 class tera_nand7
          This class implements and asynchronous 7-input nand gate.
 class tera_nand7_g
          This class implements and asynchronous 7-input nand gate.
 class tera_nand8
          This class implements and asynchronous 8-input nand gate.
 class tera_nand8_g
          This class implements and asynchronous 8-input nand gate.
 class tera_nor2
          This class implements and asynchronous 2-input nor gate.
 class tera_nor2_g
          This class implements and asynchronous 2-input nor gate.
 class tera_nor3
          This class implements and asynchronous 3-input nor gate.
 class tera_nor3_g
          This class implements and asynchronous 3-input nor gate.
 class tera_nor4
          This class implements and asynchronous 4-input nor gate.
 class tera_nor4_g
          This class implements and asynchronous 4-input nor gate.
 class tera_nor5
          This class implements and asynchronous 5-input nor gate.
 class tera_nor5_g
          This class implements and asynchronous 5-input nor gate.
 class tera_nor6
          This class implements and asynchronous 6-input nor gate.
 class tera_nor6_g
          This class implements and asynchronous 6-input nor gate.
 class tera_nor7
          This class implements and asynchronous 7-input nor gate.
 class tera_nor7_g
          This class implements and asynchronous 7-input nor gate.
 class tera_nor8
          This class implements and asynchronous 8-input nor gate.
 class tera_nor8_g
          This class implements and asynchronous 8-input nor gate.
 class tera_or2
          This class implements and asynchronous 2-input or gate.
 class tera_or2_g
          This class implements and asynchronous 2-input or gate.
 class tera_or3
          This class implements and asynchronous 3-input or gate.
 class tera_or3_g
          This class implements and asynchronous 3-input or gate.
 class tera_or4
          This class implements and asynchronous 4-input or gate.
 class tera_or4_g
          This class implements and asynchronous 4-input or gate.
 class tera_or5
          This class implements and asynchronous 5-input or gate.
 class tera_or5_g
          This class implements and asynchronous 5-input or gate.
 class tera_or6
          This class implements and asynchronous 6-input or gate.
 class tera_or6_g
          This class implements and asynchronous 6-input or gate.
 class tera_or7
          This class implements and asynchronous 7-input or gate.
 class tera_or7_g
          This class implements and asynchronous 7-input or gate.
 class tera_or8
          This class implements and asynchronous 8-input or gate.
 class tera_or8_g
          This class implements and asynchronous 8-input or gate.
 class tera_xnor2
          This class implements and asynchronous 2-input xnor gate.
 class tera_xnor2_g
          This class implements and asynchronous 2-input xnor gate.
 class tera_xnor3
          This class implements and asynchronous 3-input xnor gate.
 class tera_xnor3_g
          This class implements and asynchronous 3-input xnor gate.
 class tera_xnor4
          This class implements and asynchronous 4-input xnor gate.
 class tera_xnor4_g
          This class implements and asynchronous 4-input xnor gate.
 class tera_xnor5
          This class implements and asynchronous 5-input xnor gate.
 class tera_xnor5_g
          This class implements and asynchronous 5-input xnor gate.
 class tera_xnor6
          This class implements and asynchronous 6-input xnor gate.
 class tera_xnor6_g
          This class implements and asynchronous 6-input xnor gate.
 class tera_xnor7
          This class implements and asynchronous 7-input xnor gate.
 class tera_xnor7_g
          This class implements and asynchronous 7-input xnor gate.
 class tera_xnor8
          This class implements and asynchronous 8-input xnor gate.
 class tera_xnor8_g
          This class implements and asynchronous 8-input xnor gate.
 class tera_xor2
          This class implements and asynchronous 2-input xor gate.
 class tera_xor2_g
          This class implements and asynchronous 2-input xor gate.
 class tera_xor3
          This class implements and asynchronous 3-input xor gate.
 class tera_xor3_g
          This class implements and asynchronous 3-input xor gate.
 class tera_xor4
          This class implements and asynchronous 4-input xor gate.
 class tera_xor4_g
          This class implements and asynchronous 4-input xor gate.
 class tera_xor5
          This class implements and asynchronous 5-input xor gate.
 class tera_xor5_g
          This class implements and asynchronous 5-input xor gate.
 class tera_xor6
          This class implements and asynchronous 6-input xor gate.
 class tera_xor6_g
          This class implements and asynchronous 6-input xor gate.
 class tera_xor7
          This class implements and asynchronous 7-input xor gate.
 class tera_xor7_g
          This class implements and asynchronous 7-input xor gate.
 class tera_xor8
          This class implements and asynchronous 8-input xor gate.
 class tera_xor8_g
          This class implements and asynchronous 8-input xor gate.
 class vccX
          This instantiates a generic width vcc.
 

Uses of PreDefinedSchematic in byucc.jhdl.Xilinx
 

Classes in byucc.jhdl.Xilinx that implement PreDefinedSchematic
 class bufg
          The BUFG cell is a global buffer which distributes high-fanout clock signals throughout the device.
 class bufgp
          The BUFG cell is a global buffer which distributes high-fanout clock signals throughout the device.
 class Constant
          This class is a structural cell which drives a constant value on to its output wire.
 class gnd
          This class is the GND cell for the Xilinx tools as well as for JHDL simulation.
 class vcc
          This class is the VCC cell for the Xilinx tools as well as for JHDL simulation.
 class XilinxClockDriver
           
 

Uses of PreDefinedSchematic in byucc.jhdl.Xilinx.Virtex
 

Classes in byucc.jhdl.Xilinx.Virtex that implement PreDefinedSchematic
 class and2
          This class implements and asynchronous 2-input and gate.
 class and2_g
          This class implements and asynchronous 2-input and gate.
 class and2b1
          This class implements and asynchronous 2-input and gate.
 class and2b2
          This class implements and asynchronous 2-input and gate.
 class and3
          This class implements and asynchronous 3-input and gate.
 class and3_g
          This class implements and asynchronous 3-input and gate.
 class and3b1
          This class implements and asynchronous 3-input and gate.
 class and3b2
          This class implements and asynchronous 3-input and gate.
 class and3b3
          This class implements and asynchronous 3-input and gate.
 class and4
          This class implements and asynchronous 4-input and gate.
 class and4_g
          This class implements and asynchronous 4-input and gate.
 class and4b1
          This class implements and asynchronous 4-input and gate.
 class and4b2
          This class implements and asynchronous 4-input and gate.
 class and4b3
          This class implements and asynchronous 4-input and gate.
 class and4b4
          This class implements and asynchronous 4-input and gate.
 class and5
          This class implements and asynchronous 5-input and gate.
 class and6
          This class implements and asynchronous 6-input and gate.
 class and7
          This class implements and asynchronous 7-input and gate.
 class and8
          This class implements and asynchronous 8-input and gate.
 class and9
          This class implements and asynchronous 9-input and gate.
 class andX
          This class implements an AND gate with arbitrary number of inputs.
 class andX_g
           
 class bscan_virtex
          The BSCAN_VIRTEX symbol is used to create internal boundary scan chains in a Virtex or Virtex- E device.
 class buf
          BUF is a general purpose, non-inverting buffer.
 class buf_g
          The BUF_G is a generic-width non-inverting buffer cell.
 class bufcf
          BUFCF is a single fast connect buffer used to connect the outputs of the LUTs and some dedicated logic directly to the input of another LUT.
 class bufe
          BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple tristate buffers with inputs I, I3 - I0, I7 - I0, and I15 - I0, respectively; outputs O, O3 - O0, O7 - O0, and O15 - O0, respectively; and active-High output enable (E).
 class bufg_ann
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class bufge
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class bufgls
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class bufgs
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class buft
          BUFT is a 3-state buffer with input I, output O, and active-Low output enable (T).
 class buft_g
          The BUFT_G is a generic-width tristate buffer cell.
 class capture_virtex
          CAPTURE_VIRTEX provides user control over when to capture register (flip-flop and latch) information for readback.
 class clkdll
          CLKDLL is a clock delay locked loop used to minimize clock skew.
 class clkdllhf
          CLKDLLHF is a high frequency clock delay locked loop used to minimize clock skew.
 class d3_8e
          The d3_8e class implements an enabled 3:8 decoder.
 class fd
          D is a single D-type flip-flop with data input (D) and data output (Q).
 class fd_1
          FD_1 is a single D-type flip-flop with data input (D) and data output (Q).
 class fdc
          FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q).
 class fdc_1
          FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q).
 class fdc_1_g
          Implements an asynchronously clearable register in the XC4000 library.
 class fdc_g
          Implements an asynchronously clearable register in the XC4000 library.
 class fdce
          The FDCE is an asynchronously cleared, enabled D-type flip-flop.
 class fdce_1
          FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs, and data output (Q).
 class fdce_g
          The FDCE_G is a generic-width, asynchronously cleared, enabled D-type flip-flop.
 class fdcp
          FDCP is a single D-type flip-flop with data (D), asynchronous set (PRE), and asynchronous reset (CLR) inputs and data output (Q).
 class fdcp_1
          FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q).
 class fdcpe
          FDRSE is a single D-type flip-flop with synchronous reset (CLR), synchronous set (PRE), and clock enable (CE) inputs and data output (Q).
 class fdcpe_1
          FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q).
 class fde
          FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
 class fde_1
          FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
 class fdp
          FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
 class fdp_1
          FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
 class fdp_1_g
          Implements an asynchronously settable register in the XC4000 library.
 class fdp_g
          Implements an asynchronously settable register in the XC4000 library.
 class fdpe
          The FDPE is an asynchronously preset, enabled D-type flip-flop.
 class fdpe_1
          FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q).
 class fdpe_g
          The FDCE_P is a generic-width, asynchronously preset, enabled D-type flip-flop.
 class fdr
          FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
 class fdr_1
          FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
 class fdr_1_g
          FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
 class fdr_g
          FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
 class fdre
          FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
 class fdre_1
          FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
 class fdre_1_g
          FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
 class fdre_g
          FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
 class fdrs
          FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
 class fdrs_1
          FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
 class fdrs_1_g
          FDRS_1 is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
 class fdrs_g
          FDRS is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
 class fdrse
          FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
 class fdrse_1
          FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
 class fdrse_1_g
          FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
 class fdrse_g
          FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
 class fds
          FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
 class fds_1
          FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
 class fds_1_g
          FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
 class fds_g
          FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
 class fdse
          FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
 class fdse_1
          FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
 class fdse_1_g
          FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
 class fdse_g
          FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
 class fmap
          The FMAP symbol is used to control logic partitioning into XC4000 family 4-input function generators.
 class ibuf
          IBUF is a single input buffer.
 class ibuf_agp
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_ann
          IBUF is a single input buffer.
 class ibuf_ctt
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_g
          IBUF is a single input buffer.
 class ibuf_gtl
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_gtlp
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_hstl_i
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_hstl_iii
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_hstl_iv
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_lvcmos2
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_pci33_3
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_pci33_5
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_pci66_3
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_sstl2_i
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_sstl2_ii
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_sstl3_i
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibuf_sstl3_ii
          For Virtex and Spartan2, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard.
 class ibufg
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_agp
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_ctt
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_gtl
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_gtlp
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_hstl_i
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_hstl_iii
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_hstl_iv
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_lvcmos2
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_pci33_3
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_pci33_5
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_pci66_3
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_sstl2_i
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_sstl2_ii
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_sstl3_i
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufg_sstl3_ii
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ifd
          The IFD D-type flip-flop is contained in an input/output block (IOB).
 class ifd_1
          The IFD_1 D-type flip-flop is contained in an input/output block (IOB) except for XC5200.
 class ifdi
          The IFDI D-type flip-flop is contained in an input/output block (IOB).
 class ifdi_1
          The IFDI_1 D-type flip-flop is contained in an input/output block (IOB).
 class ifdx
          The IFDX D-type flip-flop is contained in an input/output block (IOB).
 class ifdxi
          The IFDXI D-type flip-flop is contained in an input/output block (IOB).
 class ildx_1
          ILDX_1 is a transparent data latch, which can be used to hold transient data entering a chip.
 class ildxi_1
          ILDXI_1 is a transparent data latch, which can hold transient data entering a chip.
 class inv
          The INV cell is an asynchronous inverter.
 class inv_g
          The INV_G is a generic-width inverter cell.
 class iobuf
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_agp
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_ctt
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_f_12
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_f_16
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_f_2
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_f_24
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_f_4
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_f_6
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_f_8
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_gtl
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_gtlp
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_hstl_i
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_hstl_iii
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_hstl_iv
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_lvcmos2
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_pci33_3
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_pci33_5
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_pci66_3
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_s_12
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_s_16
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_s_2
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_s_24
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_s_4
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_s_6
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_s_8
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_sstl2_i
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_sstl2_ii
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_sstl3_i
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobuf_sstl3_ii
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iopad
          Deprecated. iopads are not necessary. All that is necessary is an ibuf, and an obuft, with the input wire assigned to the perscribed pin.
 class ipad
          Deprecated. ipads are not necessary. All that is necessary is an ibuf, with the input wire assigned to the perscribed pin.
 class ipad_sim
          Deprecated. ipads are not necessary. All that is necessary is an ibuf, with the input wire assigned to the perscribed pin.
 class keeper
           
 class ld
          LD is a transparent data latch.
 class ld_1
          LD_1 is a transparent data latch with an inverted gate.
 class ldc
          LDC is a transparent data latch with asynchronous clear.
 class ldc_1
          LDC_1 is a transparent data latch with asynchronous clear and inverted gate.
 class ldce
          LDCE is a transparent data latch with asynchronous clear and gate enable.
 class ldce_1
          LDCE_1 is a transparent data latch with asynchronous clear, gate enable, and inverted gate.
 class ldcp
          LDCP is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs.
 class ldcp_1
          LDCP_1 is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs.
 class ldcpe
          LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), and gate enable (GE).
 class ldcpe_1
          LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), and gate enable (GE).
 class lde
          LDE is a transparent data latch with data (D) and gate enable (GE) inputs.
 class lde_1
          LDE_1 is a transparent data latch with data (D) and gate enable (GE) inputs.
 class ldp
          LDP is a transparent data latch with asynchronous preset (PRE).
 class ldp_1
          LDP_1 is a transparent data latch with asynchronous preset (PRE).
 class ldpe
          LDPE is a transparent data latch with asynchronous preset and gate enable.
 class ldpe_1
          LDPE_1 is a transparent data latch with asynchronous preset, gate enable, and inverted gated.
 class lut1
          LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
 class lut1_d
          LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
 class lut1_l
          LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
 class lut2
          LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
 class lut2_d
          LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
 class lut2_l
          LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
 class lut3
          LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O).
 class lut3_d
          LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
 class lut3_l
          LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
 class lut4
          LUT4 is a 4-bit look-up-table (LUT) with general output (O).
 class lut4_d
          LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
 class lut4_l
          LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer.
 class m2_1
          The M2_1 multiplexer chooses one data bit from two sources (D1 or D0) under the control of the select input (S0).
 class m2_1_g
          The M2_1 multiplexer is a generic-width 2:1 multiplexer.
 class mult_and
          MULT_AND is an AND component used exclusively for building fast and smaller multipliers.
 class muxcy
          MUXCY is used to implement a 1-bit high-speed carry propagate function.
 class muxcy_d
          MUXCY_D is used to implement a 1-bit high-speed carry propagate function.
 class muxcy_l
          MUXCY_L is used to implement a 1-bit high-speed carry propagate function.
 class muxf5
          MUXF5 provides a multiplexer function in one half of a Virtex CLB for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
 class muxf5_d
          MUXF5_D provides a multiplexer function in one half of a Virtex or Spartan2 CLB for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
 class muxf5_l
          MUXF5_L provides a multiplexer function in one half of a Virtex or Spartan2 CLB for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
 class muxf6
          MUXF6 provides a multiplexer function in a full Virtex CLB for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s.
 class muxf6_d
          MUXF6_D provides a multiplexer function in a full Virtex or Spartan2 CLB for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s.
 class muxf6_l
          MUXF6_L provides a multiplexer function in a full Virtex or Spartan2 CLB for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s.
 class nand2
          This class implements and asynchronous 2-input nand gate.
 class nand2_g
          This class implements and asynchronous 2-input nand gate.
 class nand2b1
          This class implements and asynchronous 2-input nand gate.
 class nand2b2
          This class implements and asynchronous 2-input nand gate.
 class nand3
          This class implements and asynchronous 3-input nand gate.
 class nand3_g
          This class implements and asynchronous 3-input nand gate.
 class nand3b1
          This class implements and asynchronous 3-input nand gate.
 class nand3b2
          This class implements and asynchronous 3-input nand gate.
 class nand3b3
          This class implements and asynchronous 3-input nand gate.
 class nand4
          This class implements and asynchronous 4-input nand gate.
 class nand4_g
          This class implements and asynchronous 4-input nand gate.
 class nand4b1
          This class implements and asynchronous 4-input nand gate.
 class nand4b2
          This class implements and asynchronous 4-input nand gate.
 class nand4b3
          This class implements and asynchronous 4-input nand gate.
 class nand4b4
          This class implements and asynchronous 4-input nand gate.
 class nand5
          This class implements and asynchronous 5-input nand gate.
 class nand6
          This class implements and asynchronous 6-input nand gate.
 class nand7
          This class implements and asynchronous 7-input nand gate.
 class nand8
          This class implements and asynchronous 8-input nand gate.
 class nand9
          This class implements and asynchronous 9-input nand gate.
 class nandX
          This class implements an NAND gate with arbitrary number of inputs.
 class nandX_g
           
 class nor2
          This class implements and asynchronous 2-input nor gate.
 class nor2_g
          This class implements and asynchronous 2-input nor gate.
 class nor2b1
          This class implements and asynchronous 2-input nor gate.
 class nor2b2
          This class implements and asynchronous 2-input nor gate.
 class nor3
          This class implements and asynchronous 3-input nor gate.
 class nor3_g
          This class implements and asynchronous 3-input nor gate.
 class nor3b1
          This class implements and asynchronous 3-input nor gate.
 class nor3b2
          This class implements and asynchronous 3-input nor gate.
 class nor3b3
          This class implements and asynchronous 3-input nor gate.
 class nor4
          This class implements and asynchronous 4-input nor gate.
 class nor4_g
          This class implements and asynchronous 4-input nor gate.
 class nor4b1
          This class implements and asynchronous 4-input nor gate.
 class nor4b2
          This class implements and asynchronous 4-input nor gate.
 class nor4b3
          This class implements and asynchronous 4-input nor gate.
 class nor4b4
          This class implements and asynchronous 4-input nor gate.
 class nor5
          This class implements and asynchronous 5-input nor gate.
 class nor6
          This class implements and asynchronous 6-input nor gate.
 class nor7
          This class implements and asynchronous 7-input nor gate.
 class nor8
          This class implements and asynchronous 8-input nor gate.
 class nor9
          This class implements and asynchronous 9-input nor gate.
 class norX
          This class implements an NOR gate with arbitrary number of inputs.
 class norX_g
           
 class obuf
          OBUF is a single output buffer.
 class obuf_agp
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_ann
          OBUF is a single output buffer.
 class obuf_ctt
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_f_12
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_f_16
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_f_2
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_f_24
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_f_4
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_f_6
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_f_8
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_g
          OBUF is a single output buffer.
 class obuf_gtl
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_gtlp
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_hstl_i
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_hstl_iii
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_hstl_iv
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_lvcmos2
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_pci33_3
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_pci33_5
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_pci66_3
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_s_12
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_s_16
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_s_2
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_s_24
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_s_4
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_s_6
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_s_8
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_sstl2_i
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_sstl2_ii
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_sstl3_i
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_sstl3_ii
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuft
          OBUFT is a single 3-state output buffer with active-low enable.
 class obuft_agp
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_ctt
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_f_12
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_f_16
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_f_2
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_f_24
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_f_4
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_f_6
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_f_8
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_g
          OBUFT is a single 3-state output buffer with active-low enable.
 class obuft_gtl
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_gtlp
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_hstl_i
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_hstl_iii
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_hstl_iv
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_lvcmos2
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_pci33_3
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_pci33_5
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_pci66_3
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_s_12
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_s_16
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_s_2
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_s_24
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_s_4
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_s_6
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_s_8
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_sstl2_i
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_sstl2_ii
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_sstl3_i
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuft_sstl3_ii
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class ofd
          OFD, OFD4, OFD8, and OFD16 are single and multiple output D flip-flops except for XC5200 and XC9000.
 class ofde
          OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops whose outputs are enabled by tristate buffers.
 class ofdi
          OFDI is contained in an input/output block (IOB).
 class ofdt
          OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers.
 class ofdtx
          OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers.
 class ofdtxi
          OFDTXI and its output buffer are contained in an input/output block (IOB).
 class ofdx
          OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops.
 class ofdxi
          OFDXI is contained in an input/output block (IOB).
 class opad
          Deprecated. ipads are not necessary. All that is necessary is an obuf, with the input wire assigned to the perscribed pin.
 class opad_sim
          Deprecated. ipads are not necessary. All that is necessary is an obuf, with the input wire assigned to the perscribed pin.
 class or2
          This class implements and asynchronous 2-input or gate.
 class or2_g
          This class implements and asynchronous 2-input or gate.
 class or2b1
          This class implements and asynchronous 2-input or gate.
 class or2b2
          This class implements and asynchronous 2-input or gate.
 class or3
          This class implements and asynchronous 3-input or gate.
 class or3_g
          This class implements and asynchronous 3-input or gate.
 class or3b1
          This class implements and asynchronous 3-input or gate.
 class or3b2
          This class implements and asynchronous 3-input or gate.
 class or3b3
          This class implements and asynchronous 3-input or gate.
 class or4
          This class implements and asynchronous 4-input or gate.
 class or4_g
          This class implements and asynchronous 4-input or gate.
 class or4b1
          This class implements and asynchronous 4-input or gate.
 class or4b2
          This class implements and asynchronous 4-input or gate.
 class or4b3
          This class implements and asynchronous 4-input or gate.
 class or4b4
          This class implements and asynchronous 4-input or gate.
 class or5
          This class implements and asynchronous 5-input or gate.
 class or6
          This class implements and asynchronous 6-input or gate.
 class or7
          This class implements and asynchronous 7-input or gate.
 class or8
          This class implements and asynchronous 8-input or gate.
 class or9
          This class implements and asynchronous 9-input or gate.
 class orX
          This class implements an OR gate with arbitrary number of inputs.
 class orX_g
           
 class pulldown
          PULLDOWN resistor elements are available in each XC4000 Input/Output Block (IOB).
 class pulldown_g
          The PULLDOWN_G is a generic-width pulldown resistor cell.
 class pullup
          The pull-up element establishes a High logic level for open-drain elements and macros (DECODE, WAND, WORAND) or 3-state nodes (TBUF) when all the drivers are off.
 class pullup_g
          The PULLUP_G is a generic-width pullup resistor cell.
 class ram16x1d
          RAM16X1D is a 16-word by 1-bit static dual-ported RAM.
 class ram16x1d_1
          RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.
 class ram16x1s
          RAM16X1S is a synchronous 16-word by 1-bit static RAM.
 class ram16x1s_1
          RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.
 class ram16x2d
          RAM16X2D is a 16-word by 2-bit static dual-ported RAM.
 class ram16x2s
          RAM16X2S is a synchronous 16-word by 2-bit static RAM.
 class ram16x4d
          RAM16X4D is a 16-word by 4-bit static dual-ported RAM.
 class ram16x4s
          RAM16X4S is a synchronous 16-word by 4-bit static RAM.
 class ram16x8d
          RAM16X8D is a 16-word by 8-bit static dual-ported RAM.
 class ram16x8s
          RAM16X8S is a synchronous 16-word by 8-bit static RAM.
 class ram32x1s
          RAM32X1S is a synchronous 32-word by 1-bit static RAM.
 class ram32x1s_1
          RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability.
 class ram32x1s_ack
           
 class ram32x2s
          RAM32X2S is a synchronous 32-word by 2-bit static RAM.
 class ram32x4s
          RAM32X4S is a synchronous 32-word by 4-bit static RAM.
 class ram32x8s
          RAM32X8S is a synchronous 32-word by 8-bit static RAM.
 class rom16x1
          ROM16X1 is a 16-word by 1-bit ROM.
 class rom32x1
          ROM32X1 is a 32-word by 1-bit ROM.
 class srl16
          SRL16 is a shift register look up table (LUT).
 class srl16_1
          SRL16_1 is a shift register look up table (LUT).
 class srl16e
          SRL16E is a shift register look up table (LUT).
 class srl16e_1
          SRL16E_1 is a shift register look up table (LUT).
 class startup_virtex
          The STARTUP_VIRTEX primitive is used for Global Set/Reset, global 3-state control, and the user configuration clock.
 class upad
          A UPAD allows the use of any unbonded IOBs in a device.
 class xnor2
          This class implements and asynchronous 2-input xnor gate.
 class xnor2_g
          This class implements and asynchronous 2-input xnor gate.
 class xnor3
          This class implements and asynchronous 3-input xnor gate.
 class xnor3_g
          This class implements and asynchronous 3-input xnor gate.
 class xnor4
          This class implements and asynchronous 4-input xnor gate.
 class xnor4_g
          This class implements and asynchronous 4-input xnor gate.
 class xnor5
          This class implements and asynchronous 5-input xnor gate.
 class xnor6
          This class implements and asynchronous 6-input xnor gate.
 class xnor7
          This class implements and asynchronous 7-input xnor gate.
 class xnor8
          This class implements and asynchronous 8-input xnor gate.
 class xnor9
          This class implements and asynchronous 9-input xnor gate.
 class xnorX
          This class implements an XNOR gate with arbitrary number of inputs.
 class xor2
          This class implements and asynchronous 2-input xor gate.
 class xor2_g
          This class implements and asynchronous 2-input xor gate.
 class xor3
          This class implements and asynchronous 3-input xor gate.
 class xor3_g
          This class implements and asynchronous 3-input xor gate.
 class xor4
          This class implements and asynchronous 4-input xor gate.
 class xor4_g
          This class implements and asynchronous 4-input xor gate.
 class xor5
          This class implements and asynchronous 5-input xor gate.
 class xor6
          This class implements and asynchronous 6-input xor gate.
 class xor7
          This class implements and asynchronous 7-input xor gate.
 class xor8
          This class implements and asynchronous 8-input xor gate.
 class xor9
          This class implements and asynchronous 9-input xor gate.
 class xorcy
          XORCY is a special XOR with general O output used for generating faster and smaller arithmetic functions.
 class xorcy_d
          XORCY_D is a special XOR used for generating faster and smaller arithmetic functions.
 class xorcy_l
          XORCY_L is a special XOR with general O output used for generating faster and smaller arithmetic functions.
 class xorX
          This class implements an XOR gate with arbitrary number of inputs.
 

Uses of PreDefinedSchematic in byucc.jhdl.Xilinx.Virtex.helpers
 

Classes in byucc.jhdl.Xilinx.Virtex.helpers that implement PreDefinedSchematic
 class adder
          Class used by the TechMapper.
 class adderSubtractor
          Class used by the TechMapper.
 class Subtractor
          Class used by the TechMapper.
 

Uses of PreDefinedSchematic in byucc.jhdl.Xilinx.Virtex.Modules
 

Classes in byucc.jhdl.Xilinx.Virtex.Modules that implement PreDefinedSchematic
 class Mux
          implements and arbitrary -width and -height mux, optimized to use all of the Virtex internal mux primitives.
 class mux41
          Class used by the TechMapper.
 class mux81
          Class used by the TechMapper.
 class Shifter
          Class used by the TechMapper.
 

Uses of PreDefinedSchematic in byucc.jhdl.Xilinx.Virtex2
 

Classes in byucc.jhdl.Xilinx.Virtex2 that implement PreDefinedSchematic
 class bscan_virtex2
          The BSCAN_VIRTEX2 symbol is used to create internal boundary scan chains in a Virtex2 or Virtex2- E device.
 class bufgce
          BUFGCE is a multiplexed global clock buffer with a single gated input.
 class bufgce_1
          BUFGCE_1 is a multiplexed global clock buffer with a single gated input.
 class bufgdll
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class bufgmux
          BUFGMUX is a multiplexed global clock buffer that can select between two input clocks I0 and I1.
 class bufgmux_1
          BUFGMUX_1 is a multiplexed global clock buffer that can select between two input clocks I0 and I1.
 class capture_virtex2
          CAPTURE_VIRTEX2 provides user control over when to capture register (flip-flop and latch) information for readback.
 class dcm
          DCM is a digital clock manager that provides multiple functions.
 class fddrcpe
          FDDRCPE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1).
 class fddrrse
          FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1).
 class ibuf_lvttl
          IBUF is a single input buffer.
 class ibufds
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_blvds_25
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_diff_out
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_ldt_25
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvds_25
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvds_25_dci
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvds_33
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvds_33_dci
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvdsext_25
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvdsext_25_dci
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvdsext_33
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvdsext_33_dci
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvpecl_25
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_lvpecl_33
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufds_ulvds_25
          IBUFDS is an input buffer that supports low-voltage, differential signaling.
 class ibufg_lvttl
          IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL.
 class ibufgds
          IBUFGDS is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or DCM.
 class ibufgds_lvds_25
          IBUFGDS is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or DCM.
 class ibufgds_lvdsext_25
          IBUFGDS is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or DCM.
 class icap_virtex2
           
 class ifddrcpe
          IFDDRCPE is a dual data rate (DDR) input D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR).
 class ifddrrse
          FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1).
 class iobuf_sstl2_ii_dci
          IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard.
 class iobufds
           
 class mult18x18
          MULT18X18 is a combinational signed 18-bit by 18-bit multiplier.
 class mult18x18s
          MULT18X18S is a signed 18-bit by 18-bit multiplier with output registered.
 class muxf7
          MUXF7 provides a multiplexer function in a full Virtex-II CLB for creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables.
 class muxf7_d
          MUXF7_D provides a multiplexer function in one full Virtex-II CLB for creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables.
 class muxf7_l
          MUXF7_L provides a multiplexer function in a full Virtex-II CLB for creating a func-tion- of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables.
 class muxf8
          MUXF8 provides a multiplexer function in two full Virtex-II CLBs for creating a func-tion- of-7 lookup table or a 32-to-1 multiplexer in combination with the associated lookup tables and two MUXF8s.
 class muxf8_d
          MUXF8_D provides a multiplexer function in two full Virtex-II CLBs for creating a function-of-8 lookup table or a 32-to-1 multiplexer in combination with the associated four lookup tables and two MUXF8s.
 class muxf8_l
          MUXF8_L provides a multiplexer function in two full Virtex-II CLBs for creating a function-of-8 lookup table or a 32-to-1 multiplexer in combination with the associated four lookup tables and two MUXF8s.
 class obuf_lvttl_f_12
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obuf_sstl2_i_dci
          OBUF and its variants (listed below) are single output buffers whose I/O interface corresponds to a specific I/O standard.
 class obufds
          OBUFDS is a single output buffer that supports low-voltage, differential signaling (1.8v CMOS).
 class obufds_lvds_25
          OBUFDS is a single output buffer that supports low-voltage, differential signaling (1.8v CMOS).
 class obufds_lvdsext_25
          OBUFDS is a single output buffer that supports low-voltage, differential signaling (1.8v CMOS).
 class obuft_sstl2_i_dci
          OBUFT and its variants (listed below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard.
 class obuftds
          OBUFTDS is a single 3-state, differential signaling output buffer with active Low enable and a selectIO interface.
 class ofddrcpe
          OFDDRCPE is a dual data rate (DDR) output D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR).
 class ofddrrse
          OFDDRRSE is a dual data rate (DDR) output D flip-flop with synchronous reset (R) and set (S) and clock enable (CE).
 class ofddrtcpe
          OFDDRTCPE is a dual data rate (DDR) D flip-flop with clock enable (CE) and asynchronous preset and clear whose output is enabled by a 3-state buffer.
 class ofddrtrse
          OFDDRTRSE is a dual data rate (DDR) D flip-flop with clock enable (CE) and synchronous reset and set whose output is enabled by a 3-state buffer.
 class orcy
          ORCY is a special OR with general O output used for generating faster and smaller arithmetic functions.
 class ram128x1s
          RAM128X1S is a 128-word by 1-bit static random access memory with synchronous write capability.
 class ram128x1s_1
          RAM128X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability.
 class ram32x1d
          RAM32X1D is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.
 class ram32x1d_1
          RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
 class ram64x1d
          RAM64X1D is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a positive-edge clock.
 class ram64x1d_1
          RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
 class ram64x1s
          RAM64X1S is a 64-word by 1-bit static random access memory with synchronous write capability.
 class ram64x1s_1
          RAM64X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability and a negative-edge clock.
 class ram64x2s
          RAM64X2S is a 64-word by 2-bit static random access memory with synchronous write capability.
 class roc
           
 class rocbuf
           
 class srlc16
          SRLC16 is a shift register look up table (LUT).
 class srlc16_1
          SRLC16_1 is a shift register look up table (LUT).
 class srlc16e
          SRLC16E is a shift register look up table (LUT) with carry, clock enable, and asynchro-nous clear.
 class srlc16e_1
          SRLC16E_1 is a shift register look up table (LUT).
 class startbuf_architecture
           
 class startup_virtex2
          The STARTUP_VIRTEX2 primitive is used for Global Set/Reset, global 3-state control, and the user configuration clock.
 class toc
           
 class tocbuf
           
 

Uses of PreDefinedSchematic in byucc.jhdl.Xilinx.XC4000
 

Classes in byucc.jhdl.Xilinx.XC4000 that implement PreDefinedSchematic
 class bscan
          The BSCAN symbol indicates that boundary scan logic should be enabled after the programmable logic device (PLD) configuration is complete.
 class buffclk
          BUFFCLK (FastCLK buffer) provides the fastest way to bring a clock into the XC4000X device.
 class bufge_ann
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class bufgls_ann
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class bufgp_ann
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class bufgs_ann
          Each of the BUF*_ANN classes implements an Annotation-only buffer, i.e.
 class hmap
          The HMAP symbol is used to control logic partitioning into XC4000 family 3-input H funciton generators.
 class ilffx
          ILFFX, an optional latch that drives the input flip-flop, allows the very fast capture of input data.
 class ilffxi
          ILFFXI, an optional latch that drives the input flip-flop, allows the very fast capture of input data.
 class ilflx_1
          ILFLX_1, an optional latch that drives the input latch, allows the very fast capture of input data.
 class ilflxi_1
          ILFLXI_1, an optional latch that drives the input latch, allows the very fast capture of input data.
 class md0
          The MD0 input pad is connected to the Mode 0 (MO) input pin, which is used to determine the configuration mode on an XC4000 device.
 class md1
          The MD1 input pad is connected to the Mode 1 (M1) input pin, which is used to determine the configuration mode on an XC4000 device.
 class md2
          The MD2 input pad is connected to the Mode 2 (M2) input pin, which is used to determine the configuration mode on an XC4000 device.
 class oand2
          OAND2 is a 2-input AND gate that is implemented in the output multiplexer of the XC4000X IOB.
 class omux2
          The OMUX2 multiplexer chooses one data bit from two sources (D1 or D0) under the control of the select input (S0).
 class onand2
          ONAND2 is a 2-input NAND gate that is implemented in the output multiplexer of the XC4000X IOB.
 class onor2
          ONOR2 is a 2-input NOR gate that is implemented in the output multiplexer of the XC4000X IOB.
 class oor2
          OOR2 is a 2-input OR gate that is implemented in the output multiplexer of the XC4000X IOB.
 class oxnor2
          OXNOR2 is a 2-input exclusive NOR gate that is implemented in the output multiplexer of the XC4000X and SpartanXL IOB.
 class oxor2
          OXOR2 is a 2-input exclusive OR gate that is implemented in the output multiplexer of the XC4000X IOB.
 class ram16x1
          RAM16X1 is a 16-word by 1-bit static RAM.
 class ram32x1
          RAM32X1 is a 32-word by 1-bit static RAM.
 class startup
          The STARTUP symbol is used for initializing the Global Set/Reset, global 3-state control, and the user configuration clock.
 class tck
          The TCK input pad is connected to the boundary scan test clock, which shifts the serial data and instructions into and out of the boundary scan data registers.
 class tdi
          The TDI input pad is connected to the boundary scan TDI input.
 class tdo
          The TDO data output pad is connected to the boundary scan TDO output.
 class tms
          The TMS input pad is connected to the boundary scan TMS input.
 class wand
          WAND1, WAND4, WAND8, and WAND16 are single and multiple open-drain buffers.
 class wor2and
          WOR2AND is a 2-input (I1 and I2) OR gate/buffer with an open-drain output (O).
 

Uses of PreDefinedSchematic in byucc.jhdl.Xilinx.XC9000
 

Classes in byucc.jhdl.Xilinx.XC9000 that implement PreDefinedSchematic
 class add1
          See the Xilinx Libraries Guide for details.
 class adsu1
          See the Xilinx Libraries Guide for details.
 class and5_g
          This class implements and asynchronous 5-input and gate.
 class and6_g
          This class implements and asynchronous 6-input and gate.
 class and7_g
          This class implements and asynchronous 7-input and gate.
 class and8_g
          This class implements and asynchronous 8-input and gate.
 class and9_g
          This class implements and asynchronous 9-input and gate.
 class bufgsr
          See the Xilinx Libraries guide for details.
 class fdcp_g
          Implements an asynchronously settable/clearable register in the XC4000 library.
 class ftcp
          Asynchronously presettable/clearable toggle flip-flop.
 class nand5_g
          This class implements and asynchronous 5-input nand gate.
 class nand6_g
          This class implements and asynchronous 6-input nand gate.
 class nand7_g
          This class implements and asynchronous 7-input nand gate.
 class nand8_g
          This class implements and asynchronous 8-input nand gate.
 class nand9_g
          This class implements and asynchronous 9-input nand gate.
 class nor5_g
          This class implements and asynchronous 5-input nor gate.
 class nor6_g
          This class implements and asynchronous 6-input nor gate.
 class nor7_g
          This class implements and asynchronous 7-input nor gate.
 class nor8_g
          This class implements and asynchronous 8-input nor gate.
 class nor9_g
          This class implements and asynchronous 9-input nor gate.
 class or5_g
          This class implements and asynchronous 5-input or gate.
 class or6_g
          This class implements and asynchronous 6-input or gate.
 class or7_g
          This class implements and asynchronous 7-input or gate.
 class or8_g
          This class implements and asynchronous 8-input or gate.
 class or9_g
          This class implements and asynchronous 9-input or gate.
 class xnor5_g
          This class implements and asynchronous 5-input xnor gate.
 class xnor6_g
          This class implements and asynchronous 6-input xnor gate.
 class xnor7_g
          This class implements and asynchronous 7-input xnor gate.
 class xnor8_g
          This class implements and asynchronous 8-input xnor gate.
 class xnor9_g
          This class implements and asynchronous 9-input xnor gate.
 class xor5_g
          This class implements and asynchronous 5-input xor gate.
 class xor6_g
          This class implements and asynchronous 6-input xor gate.
 class xor7_g
          This class implements and asynchronous 7-input xor gate.
 class xor8_g
          This class implements and asynchronous 8-input xor gate.
 class xor9_g
          This class implements and asynchronous 9-input xor gate.
 

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Copyright ? 2006 Brigham Young University, Configurable Computing Laboratory. All Rights Reserved.