Uses of Class
byucc.jhdl.Xilinx.XilinxMemorySynch_1

Packages that use XilinxMemorySynch_1

byucc.jhdl.Xilinx
byucc.jhdl.Xilinx.Virtex
byucc.jhdl.Xilinx.Virtex2

Uses of XilinxMemorySynch_1 in byucc.jhdl.Xilinx

Constructors in byucc.jhdl.Xilinx with parameters of type XilinxMemorySynch_1

ramd_prop_1(XilinxMemorySynch_1 parent, int width, Wire a, Wire dpra, Wire spo, Wire dpo)
Deprecated.

ram_synch_1(XilinxMemorySynch_1 parent, int width, Wire d, Wire we, Wire a)
Deprecated.

ram_synch_1(XilinxMemorySynch_1 parent, int width, Wire d, Wire we, Wire a, Wire clk)
Deprecated.

Uses of XilinxMemorySynch_1 in byucc.jhdl.Xilinx.Virtex

Subclasses of XilinxMemorySynch_1 in byucc.jhdl.Xilinx.Virtex

class	ram16x1d_1 RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.
class	ram16x1s_1 RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.
class	ram32x1s_1 RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability.

Uses of XilinxMemorySynch_1 in byucc.jhdl.Xilinx.Virtex2

Subclasses of XilinxMemorySynch_1 in byucc.jhdl.Xilinx.Virtex2

class	ram128x1s_1 RAM128X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability.
class	ram32x1d_1 RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
class	ram64x1d_1 RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock.
class	ram64x1s_1 RAM64X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability and a negative-edge clock.