Uses of Class
byucc.jhdl.Xilinx.XilinxFD

Packages that use XilinxFD

byucc.jhdl.Xilinx
byucc.jhdl.Xilinx.Virtex
byucc.jhdl.Xilinx.Virtex2
byucc.jhdl.Xilinx.XC9000

Uses of XilinxFD in byucc.jhdl.Xilinx

Subclasses of XilinxFD in byucc.jhdl.Xilinx

class

XilinxFD_1

Uses of XilinxFD in byucc.jhdl.Xilinx.Virtex

Subclasses of XilinxFD in byucc.jhdl.Xilinx.Virtex

class	fd D is a single D-type flip-flop with data input (D) and data output (Q).
class	fd_1 FD_1 is a single D-type flip-flop with data input (D) and data output (Q).
class	fdc FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q).
class	fdc_1 FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q).
class	fdc_1_g Implements an asynchronously clearable register in the XC4000 library.
class	fdc_g Implements an asynchronously clearable register in the XC4000 library.
class	fdce The FDCE is an asynchronously cleared, enabled D-type flip-flop.
class	fdce_1 FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs, and data output (Q).
class	fdce_g The FDCE_G is a generic-width, asynchronously cleared, enabled D-type flip-flop.
class	fdcp FDCP is a single D-type flip-flop with data (D), asynchronous set (PRE), and asynchronous reset (CLR) inputs and data output (Q).
class	fdcp_1 FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q).
class	fdcpe FDRSE is a single D-type flip-flop with synchronous reset (CLR), synchronous set (PRE), and clock enable (CE) inputs and data output (Q).
class	fdcpe_1 FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q).
class	fde FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
class	fde_1 FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
class	fdp FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
class	fdp_1 FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
class	fdp_1_g Implements an asynchronously settable register in the XC4000 library.
class	fdp_g Implements an asynchronously settable register in the XC4000 library.
class	fdpe The FDPE is an asynchronously preset, enabled D-type flip-flop.
class	fdpe_1 FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q).
class	fdpe_g The FDCE_P is a generic-width, asynchronously preset, enabled D-type flip-flop.
class	fdr FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdr_1 FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdr_1_g FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdr_g FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdre FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdre_1 FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdre_1_g FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdre_g FDRE is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdrs FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrs_1 FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrs_1_g FDRS_1 is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrs_g FDRS is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrse FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fdrse_1 FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fdrse_1_g FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fdrse_g FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fds FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fds_1 FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fds_1_g FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fds_g FDS is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fdse FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fdse_1 FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fdse_1_g FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fdse_g FDSE is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	ifd The IFD D-type flip-flop is contained in an input/output block (IOB).
class	ifd_1 The IFD_1 D-type flip-flop is contained in an input/output block (IOB) except for XC5200.
class	ifdi The IFDI D-type flip-flop is contained in an input/output block (IOB).
class	ifdi_1 The IFDI_1 D-type flip-flop is contained in an input/output block (IOB).
class	ifdx The IFDX D-type flip-flop is contained in an input/output block (IOB).
class	ifdxi The IFDXI D-type flip-flop is contained in an input/output block (IOB).
class	ofd OFD, OFD4, OFD8, and OFD16 are single and multiple output D flip-flops except for XC5200 and XC9000.
class	ofde OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops whose outputs are enabled by tristate buffers.
class	ofdi OFDI is contained in an input/output block (IOB).
class	ofdt OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers.
class	ofdtx OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers.
class	ofdtxi OFDTXI and its output buffer are contained in an input/output block (IOB).
class	ofdx OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops.
class	ofdxi OFDXI is contained in an input/output block (IOB).

Uses of XilinxFD in byucc.jhdl.Xilinx.Virtex2

Subclasses of XilinxFD in byucc.jhdl.Xilinx.Virtex2

class	ifddrcpe IFDDRCPE is a dual data rate (DDR) input D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR).
class	ifddrrse FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1).
class	ofddrtcpe OFDDRTCPE is a dual data rate (DDR) D flip-flop with clock enable (CE) and asynchronous preset and clear whose output is enabled by a 3-state buffer.
class	ofddrtrse OFDDRTRSE is a dual data rate (DDR) D flip-flop with clock enable (CE) and synchronous reset and set whose output is enabled by a 3-state buffer.

Uses of XilinxFD in byucc.jhdl.Xilinx.XC9000

Subclasses of XilinxFD in byucc.jhdl.Xilinx.XC9000

class	fdcp_g Implements an asynchronously settable/clearable register in the XC4000 library.
class	ftcp Asynchronously presettable/clearable toggle flip-flop.