The Simulator - Overview
The simulator is used to help you debug the behavior of your circuit. For
most users, the simulator is accessed either through the
cvt GUI environment or through a test bench.
cvt, or a Test Bench, places values on wires and then makes requests
to the simulator to propagate those changes through the circuit to
show its behavior. The basic calls to the simulator
are reset, step, and cycle. These commands are accessed by clicking
the appropriate buttons in cvt, by typing them to the CLI console in
cvt, or by making calls to the simulator API from a test bench.
Basic Commands
The three basic simulator commands are reset, step, and
cycle. If cvt is being used to simulate a circuit, the first call
made to the simulator is always reset. cvt makes the reset call
automatically when you cycle or step for the first time. If cvt's dtb
was used to load your circuit as described in a previous section of
this user's manual, the call to reset will also put 0's on
all your input wires. If you are using your own test bench to
simulate the circuit then the test bench must have a reset
method that will be called.
You can do a reset at any time during a simulation to
reset everything back to its initial state, preparatory to restarting
the simulation.
The step command is used to run the circuit to the next
changing clock edge or if there are multiple clocks the circuit will
be run until one of the clocks change.
The cycle command is similar to the step command, except
that it runs the circuit to the end of the current clock cycle. For
example, the default clock has a schedule of "01" and a cycle
command will set the clock low and propagate the circuit and then set
the clock high and propagate the circuit. In the special case that
the user has called step prior to a cycle command,
a subsequent cycle command will simply finish out the current
cycle.
Basic Errors
Errors may occur during the simulation of a circuit. Some of the most
common simulation errors are putting multiple values on the same wire
during a clock step or not puting a value on a wire during a clock
step (floating
wire). In both these cases a simulation exception is thrown. If you
are using cvt to simulate your circuit the exception will be caught
and the error will be displayed in the cvt console. Also the value of
the wire that is floating or has multiple puts will have an 'X' value
shown. When
this occurs you should check the validity of your design.
Restrictions
The main limitation to the simulator is its inability to handle
asynchronous loops. The simulator checks for this problem at build
time and if there are any asynchronous loops it will throw a build
exception, indicating that there was a problem building your circuit.
If you are using the cvt environment it will catch this exception and
inform you in the cvt Console the reason for the problem in building
your design.
JHDL 0.3.45
Copyright (c) 1998-2003 Brigham Young University. All rights reserved.
Last updated on 11 May 2006
