Simple Netlisting and Pads - Overview
- Netlisting
- A netlist is a description of a circuit, including hierarchy, wires, and
how it all connects together. Once a circuit has been sufficiently
simulated, the next step in the process is to generate a netlist of
the circuit which the FPGA vendors' tools can then convert to a
bitstream for downloading to hardware. EDIF is the netlist format
produced by JHDL.
- Pads and I/O Buffers
- When a design is netlisted in JHDL, one has the option of telling
the netlister to automatically insert (or not insert) pads and I/O
buffers into the design. If they are inserted, the design is complete
(contains no top level ports but instead has buffers and pads)
and can be converted to a bitstream by the vendor's backend tools.
To do manual insertion of I/O pads requires the use of a test bench,
covered later in this user's manual. The simplest form of netlisting
(which inserts I/O pads for the user automatically) is covered here.
Consult I/O Circuitry Insertion
and Advanced Netlisting Using Test Benches to learn how to do
manual pad insertion and netlisting.
Netlisting A Complete Circuit From Within cvt
Netlisting from within cvt is easy:
netlist -insertpads t -f filename.edn
Before doing this, you should select the cell to be netlisted from
within the tree view in cvt (alternatively, you can specify the full
pathname to the cell of interest before the "-insertpads" part). When
you execute this command, it will do a number of things:
- It will insert
pads and buffers appopriate for the technology. In
Xilinx, input ports will get IBUF's and output ports will get OBUF's.
The default clock will get an
IBUFG and a BUFG. NOTE: inout ports will be ignored. Thus you should
read on below for how to insert buffers for those manually.
- For each port, a new wire will be created which represents the
wire attached to the chip's pad. Its name will be derived from the
port name. For inputs, the name will be portName_IPAD_IN. For
outputs it will be portName_OPAD_OUT. For the default clock,
it will be c_IPAD_IN. These are the wire names that should be used to
constrain pin placement in a Xilinx .UCF file. For more detail,
consult the generated EDIF file.
There are a number of caveats you should be aware of when you use this
method for netlisting. The first is that all inout ports are ignored.
The second si that you may have no control over the inclusion of
clocking cells like CLKDLL's. Finally, this method is only really
useful when your design uses default clocking.
Thus, this method is useful mainly for trivial designs or for when you
just want to quickly netlist a cell to run through the backend tools
to get sizing and timing estimates. If this method does not do what you want, you will
have to do manual pad insertion. However, to get control over the
netlisting process to successfully do so requires the use of a test
bench, which is covered later in this user's manual. To learn about
how to manually insert pads and get a resulting netlist using a test
bench, go to I/O Circuitry Insertion
and Advanced Netlisting Using Test Benches.
Creating an EDIF "Black-Box" Module
It is also possible to netlist a JHDL circuit and make an EDIF
module - that is, a circuit with top level ports without any
I/O pads. This circuit can be then be used within
another design (in another CAD tool). To do this, execute the netlist
command like this:
netlist -insertpads f -f filename.edn
This will leave the top-level ports intact and not insert any I/O
circuitry. This can then be inserted into other design flows.
Consult their documentation on how to incorporate such "black box"
modules into those flows.
JHDL 0.3.45
Copyright (c) 1998-2003 Brigham Young University. All rights reserved.
Last updated on 11 May 2006
