Uses of Class
byucc.jhdl.Xilinx.XilinxLatch_1

Packages that use XilinxLatch_1

byucc.jhdl.Xilinx.Virtex
byucc.jhdl.Xilinx.Virtex2

Uses of XilinxLatch_1 in byucc.jhdl.Xilinx.Virtex

Subclasses of XilinxLatch_1 in byucc.jhdl.Xilinx.Virtex

class	ld_1 LD_1 is a transparent data latch with an inverted gate.
class	ldc_1 LDC_1 is a transparent data latch with asynchronous clear and inverted gate.
class	ldcp_1 LDCP_1 is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs.
class	ldcpe_1 LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), and gate enable (GE).
class	lde_1 LDE_1 is a transparent data latch with data (D) and gate enable (GE) inputs.
class	ldp_1 LDP_1 is a transparent data latch with asynchronous preset (PRE).
class	ldpe_1 LDPE_1 is a transparent data latch with asynchronous preset, gate enable, and inverted gated.

Uses of XilinxLatch_1 in byucc.jhdl.Xilinx.Virtex2

Subclasses of XilinxLatch_1 in byucc.jhdl.Xilinx.Virtex2

class

ldce_1 LDCE_1 is a transparent data latch with asynchronous clear, gate enable, and inverted gate.