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An example of this would be a module generator for delay lines. The only way to build this in a technology-independent way is to string together the proper number of flip flops in a serial chain. This may be very large. However, if the technology were XC4000, the best way to build delays would be with a counter and a dual-ported memory. In Virtex the SRL cell would be an even more efficient solution. However, the Logic.Modules version will be required to use flip flops.
To alleviate this, a small set of technology-optimized module generators have been created. These include delays, array multipliers, and a few other items. Technology-optimized modules may often operate slightly differently than the technology-independent ones in Logic.Modules. This is to be expected since slight changes in a module's functionality can often make it possible to take advantage of some technology feature. Thus, it is incumbent on designers to carefully read the documentation for these modules to determine if they will serve their needs.
import byucc.jhdl.Xilinx.Virtex.Modules.*;Similar packages will exist for other technologies.
An simple example might be an array multiplier for the Virtex technology. The class to directly instance it might have a constructor like this:
public arraymultiplier(Node parent, Wire a, Wire b, Wire q, String instanceName, boolean signed, int pipelineStyle) {The corresponding MULTIPLIERS class might support the following static method calls:
MULTIPLIERS.Unsigned_ArrayMultiplier(Node parent, Wire a, Wire b, Wire q, String instanceName, int pipelineStyle); MULTIPLIERS.Signed_ArrayMultiplier(Node parent, Wire a, Wire b, Wire q, String instanceName, int pipelineStyle);As always, examine the API documentation for the package in question to understand what is available.
We actively solicit the contribution of designs and module generators for inclusion in this package for future releases. No specific requirements have been set for materials to be included in this package. If you have something to contribute, contact the JHDL development team.
This is the end of the series of sections in the Users Manual on the
levels of design in JHDL. The remainder of the
Users Manual
sections deal with other specialized topics such as clocking, how to
run the JHDL tool suite for simulation, and netlisting JHDL designs.
Read on!
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Last updated on 11 May 2006