Uses of Class
byucc.jhdl.Xilinx.XilinxFD_1

Packages that use XilinxFD_1

byucc.jhdl.Xilinx.Virtex

Uses of XilinxFD_1 in byucc.jhdl.Xilinx.Virtex

Subclasses of XilinxFD_1 in byucc.jhdl.Xilinx.Virtex

class	fd_1 FD_1 is a single D-type flip-flop with data input (D) and data output (Q).
class	fdc_1 FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q).
class	fdc_1_g Implements an asynchronously clearable register in the XC4000 library.
class	fdce_1 FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs, and data output (Q).
class	fdcp_1 FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q).
class	fdcpe_1 FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q).
class	fde_1 FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).
class	fdp_1 FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q).
class	fdp_1_g Implements an asynchronously settable register in the XC4000 library.
class	fdpe_1 FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q).
class	fdr_1 FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdr_1_g FDR is a D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q).
class	fdre_1 FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdre_1_g FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q).
class	fdrs_1 FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrs_1_g FDRS_1 is a D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q).
class	fdrse_1 FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fdrse_1_g FDRSE is a D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q).
class	fds_1 FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fds_1_g FDS_1 is a D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q).
class	fdse_1 FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	fdse_1_g FDSE_1 is a D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q).
class	ifd_1 The IFD_1 D-type flip-flop is contained in an input/output block (IOB) except for XC5200.
class	ifdi_1 The IFDI_1 D-type flip-flop is contained in an input/output block (IOB).