What JHDL Provides
- a library that supports Xilinx 4K, Virtex, and Virtex II series devices.
- a graphical debugging tool that allows designers to simulate, debug and
hierarchically navigate their designs. This tool can display a schematic
view annotated with simulation or execution data, provide a waveform
view of any desired signals, and allows the designer to invoke any
public methods implemented by the circuit class (via Java reflection).
- a schematic generator that can automatically create a high-quality
schematic view of a JHDL description.
- an EDIF 2.0 netlist class that generates output compatible with current
Xilinx M2 place and route software.
- an EDIF parser allowing the user to import externally-generated designs
and modules into JHDL.
- simulation models and transparent run-time support for the Annapolis
Microsystems WildForce platform and the SLAAC1 platform.
- a table-based state-machine generator.
- facilities for instrumenting both simulation and hardware execution to
streamline the circuit verification process.
- a graphical floorplanner (under development) that will be used
cooperatively with the schematic view to manually floor-plan designs.
In addition to these specific design aids, JHDL provides a unified
design environment where a single, user interface can be used for both
simulation and execution. This allows the designer to request either simulation
or execution (or a mixture of the two) using the exact same commands for both.
For example, within this unified environment, commands such as
set-breakpoint, examine-variable, single-step, etc., are the same whether
performing simulation or execution. This is a big advantage for designers
because they can learn a single debugging environment that works for both
simulation and execution --in contrast with current systems where execution
and simulation environments are distinct and very different.
Moreover, this is what makes it possible to use the same program for both
software simulation and hardware execution. Design views are unified as well;
for example, the schematic view can display either
simulated values or values retrieved from the FPGA platform during execution
using the same view and interface.
JHDL 0.3.45
Copyright (c) 1998-2003 Brigham Young University. All rights reserved.
Last updated on 11 May 2006
