JHDL Applets

Main Menu


	\| Mailing List \| BYU Configurable Computing Laboratory \| Bug Reports \|

JHDL Applets

This page contains a number of Java Applets that demonstrate JHDL features and the ability to provide FPGA circuit modules using the web. These Applets are currently in Beta form but are made available on-line to encourage experimentation and obtain user feedback. The applet code is currently not distributed with the online JHDL distributions but may be available as the Applet code matures. Please contact Prof. Mike Wirthlin for questions or feedback regarding these applets.

Before executing these applets, please read the instructions and license shown below - the applets may not run correctly in all web browsers.

Applet Description

ArrayMult An Array Multiplier Applet targeting the Virtex FPGA

VirtexKCM A KCM Multiplier Applet targeting the Virtex FPGA

Digit Serial Multiplier A Digit Serial Multiplier allowing all parellel inputs and using converters targeting the Virtex FPGA

VirtexKCM with lisencing levels The KCM Multiplier Applet only this time it has has a pull down box that lets you set the applet at different levels. This demonstrates how different licenses can be used to give different levels of visibility to the applet.

Applet Instructions

To run these applets, your web browser must support the Java 1.3 run-time environment. The JHDL design environment requires Java 1.3 and web browsers without Java 1.3 support will not be able to run these demonstrations.

Note that these applet require the loading of relatively large jar files (about 1 MB total). Please wait for the applets to be completely loaded before experimenting with the demonstrations.

Applet License

To be determined.

wirthlin@ee.byu.edu